EP1763083A2 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- EP1763083A2 EP1763083A2 EP06019023A EP06019023A EP1763083A2 EP 1763083 A2 EP1763083 A2 EP 1763083A2 EP 06019023 A EP06019023 A EP 06019023A EP 06019023 A EP06019023 A EP 06019023A EP 1763083 A2 EP1763083 A2 EP 1763083A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- diffusion layer
- layer
- region
- type diffusion
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000009792 diffusion process Methods 0.000 claims abstract description 168
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims description 16
- 230000008878 coupling Effects 0.000 claims description 11
- 238000010168 coupling process Methods 0.000 claims description 11
- 238000005859 coupling reaction Methods 0.000 claims description 11
- 239000010410 layer Substances 0.000 description 212
- 239000000758 substrate Substances 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 210000000746 body region Anatomy 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum-silicon-copper Chemical compound 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Definitions
- the present invention relates to a semiconductor device of high withstand voltage, which improves withstand voltage characteristics of its inactive region.
- a conventional semiconductor device such as an N channel type MOS transistor, is formed in an elliptical shape.
- the semiconductor device includes an N type drain region disposed in its center region, an N type buffer region disposed circularly surrounding the N type drain region, and an N type drift region disposed circularly surrounding the N type buffer region.
- the semiconductor device also includes a P type well region disposed surrounding the N type drift region, and an N type source region disposed in each of linear regions of the P type well region.
- a conventional semiconductor device such as an N channel type MOS transistor, is formed in an elliptical shape as previously mentioned.
- the semiconductor device includes a P type semiconductor substrate, a semiconductor layer formed on the P type semiconductor substrate, a P type body region formed on the semiconductor layer, and an N type source region and a P type contact region which are formed in the P type body region.
- the semiconductor device also includes a drain region formed on the semiconductor layer, and a field oxide film formed between the drain region and the body region.
- the semiconductor device further includes four P type floating field rings disposed circularly under the field oxide film. This technology is described for instance in Japanese Patent Application Publication No. 2005-93696 , pp. 6 and 7, and Figs. 1 and 2.
- the conventional semiconductor device is formed in the elliptical shape.
- the semiconductor device includes the P type well region in a circular form, which is formed in linear regions and round regions to be used as active regions and inactive regions, respectively.
- the conventional semiconductor device has a problem that it is difficult to achieve desired withstand voltage characteristics, since the inactive regions in particular, with the same structure as that of the linear regions, is prone to convergence of an electric field due to its round shape when the MOS transistor is off.
- the conventional N channel type MOS transistor includes the four P type floating field rings, which are circularly disposed between the drain region and the body region, in order to improve the withstand voltage characteristics of the round region.
- the conventional MOS transistor has a problem that it is difficult to achieve desired current characteristics, since the P type floating field rings form barriers against the flow of free carriers (electrons) between the drain and source regions and thus lead to an increase in the on-state resistance value.
- the conventional semiconductor device includes the field oxide film formed between the drain and source regions, as mentioned above. With this structure, the conventional semiconductor device has a problem that it is difficult to achieve desired current characteristics, since the field oxide film forms a barrier against the flow of free carriers (electrons) between the drain and source regions and thus leads to an increase in the on-state resistance value.
- the invention provides a semiconductor device that includes a semiconductor layer having an active region and an inactive region.
- the active region has a source region, a drain region and a gate electrode formed therein, and the inactive region has neither a source region, a drain region nor a gate electrode.
- the device also includes an insulating layer disposed on the semiconductor layer, a first diffusion layer formed in the inactive region so as to be floating, a second diffusion layer formed in the active and inactive regions so as to be floating, and a metal layer disposed on the insulating film so as to form capacitive coupling with the first and second diffusion layers where the first diffusion layer merges with the second diffusion layer.
- Fig. 1 is a plan view for explaining an N channel type MOS transistor according to the embodiment.
- Fig. 2 is a cross-sectional view taken along the line A-A of Fig. 1, for explaining the N channel type MOS transistor according to the embodiment.
- Fig. 3 is a cross-sectional view taken along the line B-B of Fig. 1, for explaining the N channel type MOS transistor according to the embodiment.
- Fig. 4A is a view for explaining the potential distribution in a reverse state of the N channel type MOS transistor according to the embodiment.
- Fig. 4B is a view for explaining an impact ionization region of the N channel type MOS transistor according to the embodiment.
- Fig. 5A is a view for explaining the potential distribution in a reverse bias state of the N channel type MOS transistor according to the embodiment.
- Fig. 5B is a view for explaining the impact ionization region of the N channel type MOS transistor according to the embodiment.
- the N channel type MOS transistor 1 is formed in an elliptical shape, for example.
- Linear regions L in the elliptical shape include a source region disposed in its center region, and drain regions disposed on both sides of the source region.
- the linear regions L let a current pass between the drain and source regions, i.e., along the x axis.
- the linear regions L are used as active regions which let the current pass.
- round regions R in the elliptical shape are used as inactive regions which do not let the current pass.
- a P type diffusion layer 2 is circularly formed, extending across both the active and inactive regions.
- the P type diffusion layer 2 is disposed in a region shown by the dash-dot line in Fig. 1, and is disposed between the source and drain regions in the active regions.
- P type diffusion layers 3 and 4 respectively shown by the dash-double-dot line and the dotted line in Fig. 1, are formed in order to improve the withstand voltage characteristics in the inactive regions, although the detailed description thereof will be given later with reference to Figs. 4A to 5B.
- the P type diffusion layer 2 in the embodiment corresponds to a "second diffusion layer” of the present invention.
- the P type diffusion layers 3 in the embodiment correspond to "first diffusion layers” of the present invention.
- the P type diffusion layer 4 in the embodiment corresponds to a "third diffusion layer” of the present invention.
- Reference numerals enclosed within parentheses in Fig. 1 correspond to reference numerals given in Figs. 2 and 3.
- a cross-section taken along the line A-A of Fig. 1 shows a cross-section of the active region of the MOS transistor 1.
- the MOS transistor 1 is configured mainly with: the P type diffusion layer 2; a P type single crystal silicon substrate 5; an N type buried diffusion layer 6; an N type epitaxial layer 7; P type diffusion layers 8, 9, 10 and 11 to be used as back gate regions; an N type diffusion layer 12 to be used as the source region; N type diffusion layers 13, 14 and 15 to be used as the drain regions; and a gate electrode 16.
- the P type diffusion layer 2 is formed in the epitaxial layer 7. As mentioned above, the P type diffusion layer 2 is circularly formed as surrounding the P type diffusion layer 8 which is used as the back gate region.
- the P type diffusion layer 2 is formed, for example, under conditions of diffusion where the surface of the P type diffusion layer 2 has an impurity concentration of about 1.0 ⁇ 10 15 to 1.0 ⁇ 10 16 (1/cm 3 ) and a diffusion depth of about 1 to 3 ( ⁇ m).
- the P type diffusion layer 2 is formed as a floating diffusion layer and forms capacitive coupling with metal layers 25 and 26 above the P type diffusion layer 2.
- the P type diffusion layer 2 is designed to have the impurity concentration in consideration of the withstand voltage characteristics and the on-state resistance value, because the on-state resistance value increases when the P type diffusion layer 2 is formed in the active regions.
- the N type epitaxial layer 7 is formed above the P type single crystal silicon substrate 5.
- the N type buried diffusion layer 6 is formed between the substrate 5 and the epitaxial layer 7.
- the substrate 5 and the epitaxial layer 7 in the embodiment correspond to a "semiconductor layer" of the present invention.
- the "semiconductor layer" of the embodiment of the present invention may be formed of the substrate alone or may be formed of the substrate and a plurality of epitaxial layers deposited thereon.
- the substrate may be formed of an N type single crystal silicon substrate or a compound semiconductor substrate.
- the P type diffusion layer 8 is formed in the epitaxial layer 7.
- the P type diffusion layers 9, 10 and 11 are formed in the P type diffusion layer 8 in such a manner that the diffusion layers 9, 10 and 11 are superposed on the diffusion layer 8.
- the P type diffusion layer 9 being superposed on the P type diffusion layer 8 achieves reduction in the resistance value of the back gate region and hence achieves prevention of operation of a parasitic NPN transistor.
- the N type diffusion layer 12 is formed in the P type diffusion layer 9.
- the N type diffusion layer 12 is used as the source region.
- the N type diffusion layer 12 and the P type diffusion layer 11 are connected to source electrodes S and are at the same potential.
- the P type diffusion layers 10 and 11 are disposed as being surrounded by the N type diffusion layer 12, and are used as back gate lead regions.
- the P type diffusion layers 10 and 11 are formed as high-concentration impurity regions, thereby making it possible to reduce contact resistance.
- the N type diffusion layers 13, 14 and 15 are formed in the epitaxial layer 7.
- the N type diffusion layers 13, 14 and 15 are used as the drain regions.
- the N type diffusion layer 13 is circularly disposed, extending across both the active and inactive regions.
- the N type diffusion layers 14 and 15 are disposed in the active regions on both sides of the N type diffusion layer 12 which forms the source region.
- the P type diffusion layers 8 and 9, which are located under the gate electrode 16 and which are located between the N type diffusion layers 12 and 15, are used as channel regions.
- the gate electrode 16 is formed on a top surface of a gate oxide film 17.
- the gate electrode 16 is made of, for example, a polycide film which is a deposited film formed of a polysilicon film and a tungsten silicide (WSi) film.
- the gate electrode 16 is formed with a desired film thickness.
- the gate electrode 16 may be made of a single layer film formed of a polysilicon film, other various single layer films or deposited films, or the like.
- the insulating layer 18 is formed on a top surface of the epitaxial layer 7.
- the insulating layer 18 is made of a BPSG (boron phospho silicate glass) film, an SOG (spin on glass) film, or the like.
- BPSG boron phospho silicate glass
- SOG spin on glass
- photolithography technology is used for, for example, dry etching using CHF 3 +O 2 base gas to form contact holes 19, 20 and 21 in the insulating layer 18.
- Metal layers 22, 23 and 24 are buried in the contact holes 19, 20 and 21, respectively.
- the metal layers 22, 23 and 24 each have a structure formed of, for example, an aluminum-silicon (Al-Si) layer, an aluminum-copper (Al-Cu) layer or an aluminum-silicon-copper (Al-Si-Cu) layer deposited on a barrier metal layer.
- the metal layers 22, 23 and 24 may be each formed of a barrier metal layer and a metal layer in each of the contact holes 19, 20 and 21.
- the metal layer made of a high melting point metal such as tungsten (W) is buried in the barrier metal layer.
- a metal layer composed almost exclusively of aluminum is formed on the metal layer made of the high melting point metal.
- the metal layers 25 and 26 are formed on a top surface of the insulating layer 18 to cover the P type diffusion layer 2.
- the metal layers 25 and 26 are wiring layers, although not shown, connected to the source electrodes S.
- the P type diffusion layer 2 forms capacitive coupling with the metal layers 25 and 26 through the gate oxide film 17, the insulating layer 18, and so on interposed in between. Desired potentials are applied to the P type diffusion layer 2, although the potentials are slightly higher than a source potential.
- the P type diffusion layer 2 is biased in a direction reverse to the N type epitaxial layer 7, thereby improving the withstand voltage characteristics of the MOS transistor 1.
- a cross-section taken along the line B-B of Fig. 1 shows a cross-section of the inactive regions of the MOS transistor 1.
- omitted is the cross-section of the active regions which are the linear regions L in the elliptical shape, and mainly shown is the cross-section of the inactive regions which are the round regions R in the elliptical shape.
- the cross-section shown on the right side of the omitted part corresponds to a lower section along the y axis in Fig. 1.
- the cross-section shown on the left side of the omitted part corresponds to an upper section along the y axis in Fig. 1.
- LOCOS oxide films 27 and 28 are each formed between the P type diffusion layer 8 and the N type diffusion layer 13.
- the LOCOS oxide films 27 and 28 are each formed only in the inactive regions which are the round regions R, and are not formed in the active regions which are the linear regions L.
- respective ends of the gate electrode 16 are disposed on the LOCOS oxide films 27 or 28.
- the LOCOS oxide films 27 and 28 cause the gate electrode 16 to be apart from the surface of the epitaxial layer 7, so that this structure makes it possible to improve the withstand voltage characteristics.
- the LOCOS oxide films 27 and 28 in the embodiment correspond to "field oxide films" of the present invention.
- a metal layer 30 is connected to the gate electrode 16 through a contact hole 29 formed in the insulating layer 18.
- the metal layer 30 extends toward an isolation region 31 to cover the P type diffusion layer 2.
- the P type diffusion layer 2 forms capacitive coupling with the metal layer 30 through the gate oxide film 17, the insulating layer 18, and so on interposed in between.
- metal layer 32 is formed as being located above the P type diffusion layer 2.
- the metal layer 32 is connected to the source electrodes S, and the P type diffusion layer 2 forms capacitive coupling with the metal layer 32 through the gate oxide film 17, the insulating layer 18, and so on interposed in between.
- one of the P type diffusion layers 3 is formed on an end of the LOCOS oxide film 27 and in its vicinity to coincide with the shape of the round regions R, as shown by the dash-double-dot lines in Fig. 1.
- the corresponding P type diffusion layer 3 is formed as a floating diffusion layer in such a manner that a formation region of the P type diffusion layer 2 and a formation region of the P type diffusion layer 3 are superposed on each other.
- the P type diffusion layer 4 is formed to correspond to a region, in a vicinity of the contact hole 29, where a width W1 of the LOCOS oxide film 27 is greater.
- the width W1 of the LOCOS oxide film 27 is greater than a width W2 of the LOCOS oxide film 28.
- the reason is that a flat region is required above the LOCOS oxide film 27 in order to connect the metal layer 30 to the gate electrode 16, as mentioned above.
- the width of the LOCOS oxide film 27 is equal to the width W2 in regions other than the vicinity of the contact hole 29.
- the P type diffusion layers 3 and 4 form capacitive coupling with the metal layer 30 on the top surface of the insulating layer 18, as in the case of the P type diffusion layer 2.
- the P type diffusion layers 3 are formed, for example, under conditions of diffusion where each of the surfaces of the P type diffusion layers 3 has an impurity concentration of about 1.0 ⁇ 10 17 to 1.0 ⁇ 10 18 (1/cm 3 ) and a diffusion depth of about 2 to 4 ( ⁇ m).
- the P type diffusion layer 4 is formed, for example, under conditions of diffusion where the surface of the P type diffusion layer 4 has an impurity concentration of about 1.0 ⁇ 10 16 to 1.0 ⁇ 10 17 (1/cm 3 ) and a diffusion depth of about 5 to 6 ( ⁇ m).
- one of the P type diffusion layers 3 is formed on an end of the LOCOS oxide film 28 and in its vicinity to coincide with the shape of the round regions R.
- the corresponding P type diffusion layer 3 is formed as a floating diffusion layer in such a manner that the P type diffusion layer 2 and the P type diffusion layer 3 are superposed on each other.
- the corresponding P type diffusion layer 3 forms capacitive coupling with the metal layer 32 on the top surface of the insulating layer 18, as in the case of the P type diffusion layer 2.
- each of the inactive regions has a structure which is prone to convergence of an electric field due to its round shape.
- the P type diffusion layers 2, 3 and 4 are disposed in one of the inactive regions, so that it is possible to further improve the withstand voltage characteristics in the corresponding inactive region, as compared to the active regions.
- the P type diffusion layers 3 and 4 are disposed only in the inactive regions and are not disposed in the active regions.
- the active regions are the linear regions whose structure is less prone to convergence of an electric field than the inactive regions.
- the active regions have the structure in which only the P type diffusion layer 2 is disposed, so that the withstand voltage characteristics of the MOS transistor 1 are determined by the withstand voltage characteristics of the active regions.
- the active regions do not have to have P type diffusion layers more than necessary, thus making it possible to prevent an increase in the on-state resistance value of the MOS transistor 1 due to excess P type diffusion layers becoming barriers. This structure also makes it possible to prevent an increase in device size.
- Fig. 4A there is shown a region, near the LOCOS oxide film 27 in the vicinity of the contact hole 29, where the P type diffusion layer 4 is formed.
- the bold solid lines show end regions of a depletion layer
- the dotted lines show equipotential lines
- the dash-dot line shows an equipotential line at 359 V.
- the P type diffusion layers 2, 3 and 4 are formed as the floating diffusion layers, there is a region to which a potential slightly higher than a gate potential is applied.
- the region where the P type diffusion layers 2, 3 and 4 are superposed on one another is a high-concentration impurity region, and an undepleted region is present as shown by the solid line. The reason is that the undepleted P type diffusion layers 2, 3 and 4 form capacitive coupling with the metal layer 30, as mentioned above.
- the P type diffusion layer 4 is diffused to the same depth as the depth of the P type diffusion layer 8.
- a depletion layer which extends from a boundary between the P type diffusion layer 4 and the epitaxial layer 7, extends over a wide region in a horizontal direction, as in the case of a depletion layer which extends from a boundary between the P type diffusion layer 8 and the epitaxial layer 7.
- the P type diffusion layer 2 is formed as extending toward the isolation region 31.
- the region where only the P type diffusion layer 2 is formed is a low-concentration impurity region and is depleted as shown in Fig. 4A.
- distances between each of the equipotential lines change gradually.
- the P type diffusion layer 2 totally depleted is disposed outside the outermost periphery of the source region.
- this structure reduces a change in curvature of the end regions of the depletion layer, thus improving the withstand voltage characteristics of the MOS transistor 1.
- Fig. 5A there is shown a region near the LOCOS oxide film 27 where the P type diffusion layer 4 is not formed, or a region near the LOCOS oxide film 28.
- a bold solid lines show end regions of the depletion layer
- a dotted lines show equipotential lines
- a dash-dot line shows an equipotential line at 344 V.
- the P type diffusion layers 2 and 3 are formed as the floating diffusion layers, there is a region to which a potential slightly higher than the source potential is applied.
- the region where the P type diffusion layers 2 and 3 are superposed on each other is a high-concentration impurity region, and an undepleted region is present as shown by the solid line. The reason is that the undepleted P type diffusion layers 2 and 3 form capacitive coupling with the metal layer 32, as mentioned above.
- each of the P type diffusion layers 3 is formed as having the diffusion depth which is greater than that of the P type diffusion layer 2 and which is shallower than that of the P type diffusion layer 4, so that it is possible to prevent deterioration in the withstand voltage due to the width W2. In other words, it is possible to avoid a state where convergence of an electric field is prone to occur due to shortened distances between each of the equipotential lines under the LOCOS oxide film 28.
- the P type diffusion layer 2 is formed as extending toward the isolation region 31.
- the region where only the P type diffusion layer 2 is formed is the low-concentration impurity region and is depleted as shown in Fig. 5A.
- distances between each of the equipotential lines change gradually.
- the P type diffusion layer 2 totally depleted is disposed outside the outermost periphery of the source region.
- this structure reduces a change in curvature of the end regions of the depletion layer, thus improving the withstand voltage characteristics of the MOS transistor 1.
- a conductive plate 33 (see Fig. 1) having the same potential as that of the epitaxial layer 7 is formed between a device region and an isolation layer near the region where the P type diffusion layer 4 is formed.
- the conductive plate 33 is made of, for example, the same material as that of the gate electrode or the same material as that of the metal layers.
- a wiring layer or the like connected to the source electrode or the gate electrode is disposed above the conductive plate 33 with an insulating layer interposed in between.
- the conductive plate 33 shields a depletion layer extending from the device region, and hence has an effect of shielding the wiring layer.
- the conductive plate 33 relieves convergence of an electric field in a vicinity of an end portion of the isolation region 31 located under the wiring layer, thus it is possible to improve the withstand voltage characteristics of the MOS transistor 1.
- the P type diffusion layer 4 may be disposed to coincide with the shape of the round regions R, as in the case of the P type diffusion layers 3.
- Any change can be made in the design of each of the P type diffusion layers 2, 3 and 4 to be formed as the floating diffusion layers so that the P type diffusion layers 2, 3 and 4 may each have an impurity concentration, a diffusion depth, or the like depending on the withstand voltage characteristics of the MOS transistor 1.
- various changes can be made without departing from the gist of the embodiment of the present invention.
- the N channel type MOS transistor is disposed in the elliptical shape, and round regions are used as the inactive regions.
- P type diffusion layers in the floating state are formed in the epitaxial layer in the inactive regions.
- the P type diffusion layer having a lower impurity concentration is formed on the outermost periphery.
- the P type diffusion layer having a lower impurity concentration and a shallower diffusion depth is circularly formed. This structure makes it possible to improve the withstand voltage characteristics of the MOS transistor.
- LOCOS oxide films are disposed only in the inactive regions, respectively.
- the P type diffusion layer having a greater diffusion depth is formed in a region where one of the LOCOS oxide films has a greater width.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- The present invention relates to a semiconductor device of high withstand voltage, which improves withstand voltage characteristics of its inactive region.
- A conventional semiconductor device, such as an N channel type MOS transistor, is formed in an elliptical shape. The semiconductor device includes an N type drain region disposed in its center region, an N type buffer region disposed circularly surrounding the N type drain region, and an N type drift region disposed circularly surrounding the N type buffer region. The semiconductor device also includes a P type well region disposed surrounding the N type drift region, and an N type source region disposed in each of linear regions of the P type well region. With this structure, it is intended to achieve an improvement in on-state withstand voltage characteristics of the device. This technology is described for instance in
Japanese Patent Application Publication No. 2000-156495 - A conventional semiconductor device, such as an N channel type MOS transistor, is formed in an elliptical shape as previously mentioned. The semiconductor device includes a P type semiconductor substrate, a semiconductor layer formed on the P type semiconductor substrate, a P type body region formed on the semiconductor layer, and an N type source region and a P type contact region which are formed in the P type body region. The semiconductor device also includes a drain region formed on the semiconductor layer, and a field oxide film formed between the drain region and the body region. The semiconductor device further includes four P type floating field rings disposed circularly under the field oxide film. This technology is described for instance in
Japanese Patent Application Publication No. 2005-93696 - As mentioned above, the conventional semiconductor device, specifically the N channel type MOS transistor, is formed in the elliptical shape. The semiconductor device includes the P type well region in a circular form, which is formed in linear regions and round regions to be used as active regions and inactive regions, respectively. The conventional semiconductor device has a problem that it is difficult to achieve desired withstand voltage characteristics, since the inactive regions in particular, with the same structure as that of the linear regions, is prone to convergence of an electric field due to its round shape when the MOS transistor is off.
- Moreover, the conventional N channel type MOS transistor includes the four P type floating field rings, which are circularly disposed between the drain region and the body region, in order to improve the withstand voltage characteristics of the round region. With this structure, the conventional MOS transistor has a problem that it is difficult to achieve desired current characteristics, since the P type floating field rings form barriers against the flow of free carriers (electrons) between the drain and source regions and thus lead to an increase in the on-state resistance value.
- The conventional semiconductor device includes the field oxide film formed between the drain and source regions, as mentioned above. With this structure, the conventional semiconductor device has a problem that it is difficult to achieve desired current characteristics, since the field oxide film forms a barrier against the flow of free carriers (electrons) between the drain and source regions and thus leads to an increase in the on-state resistance value.
- It is an object of this invention to provide a semiconductor device that lessens these difficulties.
- The solution according to the invention lies in the features of the independent claim and preferably in those of the dependent claims.
- The invention provides a semiconductor device that includes a semiconductor layer having an active region and an inactive region. The active region has a source region, a drain region and a gate electrode formed therein, and the inactive region has neither a source region, a drain region nor a gate electrode. The device also includes an insulating layer disposed on the semiconductor layer, a first diffusion layer formed in the inactive region so as to be floating, a second diffusion layer formed in the active and inactive regions so as to be floating, and a metal layer disposed on the insulating film so as to form capacitive coupling with the first and second diffusion layers where the first diffusion layer merges with the second diffusion layer.
-
- Fig. 1 is a plan view for explaining an N channel type MOS transistor according to an embodiment of the present invention.
- Fig. 2 is a cross-sectional view for explaining the N channel type MOS transistor according to the embodiment of the present invention.
- Fig. 3 is a cross-sectional view for explaining the N channel type MOS transistor according to the embodiment of the present invention.
- Fig. 4A is a view for explaining the potential distribution in a reverse bias state of the N channel type MOS transistor according to the embodiment of the present invention.
- Fig. 4B is a view for explaining an impact ionization region of the N channel type MOS transistor according to the embodiment of the present invention.
- Fig. 5A is a view for explaining the potential distribution in a reverse bias state of the N channel type MOS transistor according to the embodiment of the present invention.
- Fig. 5B is a view for explaining the impact ionization region of the N channel type MOS transistor according to the embodiment of the present invention.
- A semiconductor device according to one embodiment of the present invention will be described in detail below with reference to Figs. 1 to 5B. Fig. 1 is a plan view for explaining an N channel type MOS transistor according to the embodiment. Fig. 2 is a cross-sectional view taken along the line A-A of Fig. 1, for explaining the N channel type MOS transistor according to the embodiment. Fig. 3 is a cross-sectional view taken along the line B-B of Fig. 1, for explaining the N channel type MOS transistor according to the embodiment. Fig. 4A is a view for explaining the potential distribution in a reverse state of the N channel type MOS transistor according to the embodiment. Fig. 4B is a view for explaining an impact ionization region of the N channel type MOS transistor according to the embodiment.
Fig. 5A is a view for explaining the potential distribution in a reverse bias state of the N channel type MOS transistor according to the embodiment. Fig. 5B is a view for explaining the impact ionization region of the N channel type MOS transistor according to the embodiment. - As shown in Fig. 1, the N channel
type MOS transistor 1 is formed in an elliptical shape, for example. Linear regions L in the elliptical shape include a source region disposed in its center region, and drain regions disposed on both sides of the source region. The linear regions L let a current pass between the drain and source regions, i.e., along the x axis. In short, the linear regions L are used as active regions which let the current pass. On the other hand, round regions R in the elliptical shape are used as inactive regions which do not let the current pass. A Ptype diffusion layer 2 is circularly formed, extending across both the active and inactive regions. The Ptype diffusion layer 2 is disposed in a region shown by the dash-dot line in Fig. 1, and is disposed between the source and drain regions in the active regions. In the round regions R, Ptype diffusion layers - Incidentally, the P
type diffusion layer 2 in the embodiment corresponds to a "second diffusion layer" of the present invention. The Ptype diffusion layers 3 in the embodiment correspond to "first diffusion layers" of the present invention. The Ptype diffusion layer 4 in the embodiment corresponds to a "third diffusion layer" of the present invention. Reference numerals enclosed within parentheses in Fig. 1 correspond to reference numerals given in Figs. 2 and 3. - As shown in Fig. 2, a cross-section taken along the line A-A of Fig. 1 shows a cross-section of the active region of the
MOS transistor 1. TheMOS transistor 1 is configured mainly with: the Ptype diffusion layer 2; a P type singlecrystal silicon substrate 5; an N type burieddiffusion layer 6; an Ntype epitaxial layer 7; P type diffusion layers 8, 9, 10 and 11 to be used as back gate regions; an Ntype diffusion layer 12 to be used as the source region; N type diffusion layers 13, 14 and 15 to be used as the drain regions; and agate electrode 16. - The P
type diffusion layer 2 is formed in theepitaxial layer 7. As mentioned above, the Ptype diffusion layer 2 is circularly formed as surrounding the Ptype diffusion layer 8 which is used as the back gate region. The Ptype diffusion layer 2 is formed, for example, under conditions of diffusion where the surface of the Ptype diffusion layer 2 has an impurity concentration of about 1.0×1015 to 1.0×1016 (1/cm3) and a diffusion depth of about 1 to 3 (µm). Moreover, the Ptype diffusion layer 2 is formed as a floating diffusion layer and forms capacitive coupling withmetal layers type diffusion layer 2. When a reverse bias is applied to theMOS transistor 1, this structure causes a state where a certain potential is applied to the Ptype diffusion layer 2, thereby it is possible to improve the withstand voltage characteristics in the active regions. The Ptype diffusion layer 2 is designed to have the impurity concentration in consideration of the withstand voltage characteristics and the on-state resistance value, because the on-state resistance value increases when the Ptype diffusion layer 2 is formed in the active regions. - The N type
epitaxial layer 7 is formed above the P type singlecrystal silicon substrate 5. The N type burieddiffusion layer 6 is formed between thesubstrate 5 and theepitaxial layer 7. Thesubstrate 5 and theepitaxial layer 7 in the embodiment correspond to a "semiconductor layer" of the present invention. Moreover, in this embodiment, although the description is given for a case where thesingle epitaxial layer 7 is formed on thesubstrate 5, the present invention is not limited to this case. For example, the "semiconductor layer" of the embodiment of the present invention may be formed of the substrate alone or may be formed of the substrate and a plurality of epitaxial layers deposited thereon. Moreover, the substrate may be formed of an N type single crystal silicon substrate or a compound semiconductor substrate. - The P
type diffusion layer 8 is formed in theepitaxial layer 7. The P type diffusion layers 9, 10 and 11 are formed in the Ptype diffusion layer 8 in such a manner that the diffusion layers 9, 10 and 11 are superposed on thediffusion layer 8. The Ptype diffusion layer 9 being superposed on the Ptype diffusion layer 8 achieves reduction in the resistance value of the back gate region and hence achieves prevention of operation of a parasitic NPN transistor. - The N
type diffusion layer 12 is formed in the Ptype diffusion layer 9. The Ntype diffusion layer 12 is used as the source region. The Ntype diffusion layer 12 and the Ptype diffusion layer 11 are connected to source electrodes S and are at the same potential. The P type diffusion layers 10 and 11 are disposed as being surrounded by the Ntype diffusion layer 12, and are used as back gate lead regions. The P type diffusion layers 10 and 11 are formed as high-concentration impurity regions, thereby making it possible to reduce contact resistance. - The N type diffusion layers 13, 14 and 15 are formed in the
epitaxial layer 7. The N type diffusion layers 13, 14 and 15 are used as the drain regions. As shown in Fig. 1, the Ntype diffusion layer 13 is circularly disposed, extending across both the active and inactive regions. The N type diffusion layers 14 and 15 are disposed in the active regions on both sides of the Ntype diffusion layer 12 which forms the source region. The Ptype diffusion layers gate electrode 16 and which are located between the N type diffusion layers 12 and 15, are used as channel regions. - The
gate electrode 16 is formed on a top surface of agate oxide film 17. Thegate electrode 16 is made of, for example, a polycide film which is a deposited film formed of a polysilicon film and a tungsten silicide (WSi) film. Thegate electrode 16 is formed with a desired film thickness. Thegate electrode 16 may be made of a single layer film formed of a polysilicon film, other various single layer films or deposited films, or the like. - An insulating
layer 18 is formed on a top surface of theepitaxial layer 7. The insulatinglayer 18 is made of a BPSG (boron phospho silicate glass) film, an SOG (spin on glass) film, or the like. Heretofore known photolithography technology is used for, for example, dry etching using CHF3+O2 base gas to form contact holes 19, 20 and 21 in the insulatinglayer 18. - Metal layers 22, 23 and 24 are buried in the contact holes 19, 20 and 21, respectively. The metal layers 22, 23 and 24 each have a structure formed of, for example, an aluminum-silicon (Al-Si) layer, an aluminum-copper (Al-Cu) layer or an aluminum-silicon-copper (Al-Si-Cu) layer deposited on a barrier metal layer. The metal layers 22, 23 and 24 may be each formed of a barrier metal layer and a metal layer in each of the contact holes 19, 20 and 21. The metal layer made of a high melting point metal such as tungsten (W) is buried in the barrier metal layer. A metal layer composed almost exclusively of aluminum is formed on the metal layer made of the high melting point metal.
- The metal layers 25 and 26 are formed on a top surface of the insulating
layer 18 to cover the Ptype diffusion layer 2. The metal layers 25 and 26 are wiring layers, although not shown, connected to the source electrodes S. With this structure, the Ptype diffusion layer 2 forms capacitive coupling with the metal layers 25 and 26 through thegate oxide film 17, the insulatinglayer 18, and so on interposed in between. Desired potentials are applied to the Ptype diffusion layer 2, although the potentials are slightly higher than a source potential. With this structure, the Ptype diffusion layer 2 is biased in a direction reverse to the Ntype epitaxial layer 7, thereby improving the withstand voltage characteristics of theMOS transistor 1. - As shown in Fig. 3, a cross-section taken along the line B-B of Fig. 1 shows a cross-section of the inactive regions of the
MOS transistor 1. In Fig. 3, omitted is the cross-section of the active regions which are the linear regions L in the elliptical shape, and mainly shown is the cross-section of the inactive regions which are the round regions R in the elliptical shape. The cross-section shown on the right side of the omitted part corresponds to a lower section along the y axis in Fig. 1. The cross-section shown on the left side of the omitted part corresponds to an upper section along the y axis in Fig. 1. - In the round regions R,
LOCOS oxide films type diffusion layer 8 and the Ntype diffusion layer 13. TheLOCOS oxide films gate electrode 16 are disposed on theLOCOS oxide films LOCOS oxide films LOCOS oxide films gate electrode 16 to be apart from the surface of theepitaxial layer 7, so that this structure makes it possible to improve the withstand voltage characteristics. TheLOCOS oxide films - On the
LOCOS oxide film 27, ametal layer 30 is connected to thegate electrode 16 through acontact hole 29 formed in the insulatinglayer 18. On the insulatinglayer 18, themetal layer 30 extends toward anisolation region 31 to cover the Ptype diffusion layer 2. The Ptype diffusion layer 2 forms capacitive coupling with themetal layer 30 through thegate oxide film 17, the insulatinglayer 18, and so on interposed in between. On the other hand, near theLOCOS oxide film 28,metal layer 32 is formed as being located above the Ptype diffusion layer 2. Themetal layer 32 is connected to the source electrodes S, and the Ptype diffusion layer 2 forms capacitive coupling with themetal layer 32 through thegate oxide film 17, the insulatinglayer 18, and so on interposed in between. - As regards the
LOCOS oxide film 27, one of the P type diffusion layers 3 is formed on an end of theLOCOS oxide film 27 and in its vicinity to coincide with the shape of the round regions R, as shown by the dash-double-dot lines in Fig. 1. The corresponding Ptype diffusion layer 3 is formed as a floating diffusion layer in such a manner that a formation region of the Ptype diffusion layer 2 and a formation region of the Ptype diffusion layer 3 are superposed on each other. In addition, as shown by the dotted lines in Fig. 1, the Ptype diffusion layer 4 is formed to correspond to a region, in a vicinity of thecontact hole 29, where a width W1 of theLOCOS oxide film 27 is greater. In the vicinity of thecontact hole 29, the width W1 of theLOCOS oxide film 27 is greater than a width W2 of theLOCOS oxide film 28. The reason is that a flat region is required above theLOCOS oxide film 27 in order to connect themetal layer 30 to thegate electrode 16, as mentioned above. Even as regards theLOCOS oxide film 27, the width of theLOCOS oxide film 27 is equal to the width W2 in regions other than the vicinity of thecontact hole 29. - The P
type diffusion layers metal layer 30 on the top surface of the insulatinglayer 18, as in the case of the Ptype diffusion layer 2. The Ptype diffusion layers 3 are formed, for example, under conditions of diffusion where each of the surfaces of the P type diffusion layers 3 has an impurity concentration of about 1.0×1017 to 1.0×1018 (1/cm3) and a diffusion depth of about 2 to 4 (µm). The Ptype diffusion layer 4 is formed, for example, under conditions of diffusion where the surface of the Ptype diffusion layer 4 has an impurity concentration of about 1.0×1016 to 1.0×1017 (1/cm3) and a diffusion depth of about 5 to 6 (µm). - On the other hand, as regards the
LOCOS oxide film 28, one of the P type diffusion layers 3 is formed on an end of theLOCOS oxide film 28 and in its vicinity to coincide with the shape of the round regions R. The corresponding Ptype diffusion layer 3 is formed as a floating diffusion layer in such a manner that the Ptype diffusion layer 2 and the Ptype diffusion layer 3 are superposed on each other. The corresponding Ptype diffusion layer 3 forms capacitive coupling with themetal layer 32 on the top surface of the insulatinglayer 18, as in the case of the Ptype diffusion layer 2. - With this structure, near the
LOCOS oxide film 27 in the vicinity of thecontact hole 29, a space between the Ptype diffusion layer 8 and the Ptype diffusion layer 2 becomes greater, but a total depletion does not occur in a region where at least the P type diffusion layers 2, 3 and 4 are superposed on one another, so that the withstand voltage characteristics can be improved. On the other hand, near theLOCOS oxide film 27 not being in the vicinity of thecontact hole 29, or near theLOCOS oxide film 28, a total depletion does not occur in a region where at least the Ptype diffusion layers - Moreover, the P
type diffusion layers type diffusion layer 2 is disposed, so that the withstand voltage characteristics of theMOS transistor 1 are determined by the withstand voltage characteristics of the active regions. With this structure, the active regions do not have to have P type diffusion layers more than necessary, thus making it possible to prevent an increase in the on-state resistance value of theMOS transistor 1 due to excess P type diffusion layers becoming barriers. This structure also makes it possible to prevent an increase in device size. - In Fig. 4A, there is shown a region, near the
LOCOS oxide film 27 in the vicinity of thecontact hole 29, where the Ptype diffusion layer 4 is formed. As shown in Fig. 4A, the bold solid lines show end regions of a depletion layer, the dotted lines show equipotential lines, and the dash-dot line shows an equipotential line at 359 V. As shown in Fig. 4A, although the P type diffusion layers 2, 3 and 4 are formed as the floating diffusion layers, there is a region to which a potential slightly higher than a gate potential is applied. The region where the P type diffusion layers 2, 3 and 4 are superposed on one another is a high-concentration impurity region, and an undepleted region is present as shown by the solid line. The reason is that the undepleted P type diffusion layers 2, 3 and 4 form capacitive coupling with themetal layer 30, as mentioned above. - Moreover, the P
type diffusion layer 4 is diffused to the same depth as the depth of the Ptype diffusion layer 8. A depletion layer, which extends from a boundary between the Ptype diffusion layer 4 and theepitaxial layer 7, extends over a wide region in a horizontal direction, as in the case of a depletion layer which extends from a boundary between the Ptype diffusion layer 8 and theepitaxial layer 7. With this structure, the width W1 of theLOCOS oxide film 27 becomes greater in the vicinity of thecontact hole 29, but the Ptype diffusion layers LOCOS oxide film 27. - Moreover, the P
type diffusion layer 2 is formed as extending toward theisolation region 31. As mentioned above, the region where only the Ptype diffusion layer 2 is formed is a low-concentration impurity region and is depleted as shown in Fig. 4A. In the region where the Ptype diffusion layer 2 is formed, distances between each of the equipotential lines change gradually. In other words, the Ptype diffusion layer 2 totally depleted is disposed outside the outermost periphery of the source region. As shown in Fig. 4A, this structure reduces a change in curvature of the end regions of the depletion layer, thus improving the withstand voltage characteristics of theMOS transistor 1. - Incidentally, as shown by a hatched
region 33 in Fig. 4B, impact ionization occurs in a vicinity of an end portion of the Ptype diffusion layer 2 located near theisolation region 31. As can be also understood from Fig. 4B, the Ptype diffusion layers LOCOS oxide film 27 in the vicinity of thecontact hole 29, thus preventing deterioration in the withstand voltage under theLOCOS oxide film 27 having the width W1. - In Fig. 5A, there is shown a region near the
LOCOS oxide film 27 where the Ptype diffusion layer 4 is not formed, or a region near theLOCOS oxide film 28. As shown in Fig. 5A, a bold solid lines show end regions of the depletion layer, a dotted lines show equipotential lines, and a dash-dot line shows an equipotential line at 344 V. As shown in Fig. 5A, although the Ptype diffusion layers type diffusion layers type diffusion layers metal layer 32, as mentioned above. - Except the vicinity region of the
contact hole 29, there is no need to consider the region for connecting to thegate electrode 16, it is possible to set the width W2 of theLOCOS oxide film 28 at a minimum width. With this structure, each of the P type diffusion layers 3 is formed as having the diffusion depth which is greater than that of the Ptype diffusion layer 2 and which is shallower than that of the Ptype diffusion layer 4, so that it is possible to prevent deterioration in the withstand voltage due to the width W2. In other words, it is possible to avoid a state where convergence of an electric field is prone to occur due to shortened distances between each of the equipotential lines under theLOCOS oxide film 28. - Moreover, the P
type diffusion layer 2 is formed as extending toward theisolation region 31. As mentioned above, the region where only the Ptype diffusion layer 2 is formed is the low-concentration impurity region and is depleted as shown in Fig. 5A. In the region where the Ptype diffusion layer 2 is formed, distances between each of the equipotential lines change gradually. In other words, the Ptype diffusion layer 2 totally depleted is disposed outside the outermost periphery of the source region. As shown in Fig. 5A, this structure reduces a change in curvature of the end regions of the depletion layer, thus improving the withstand voltage characteristics of theMOS transistor 1. - As shown by a hatched
region 34 in Fig. 5B, impact ionization occurs in a vicinity of a region of intersection of the Ptype diffusion layers isolation region 31. As can be also understood from Fig. 5B, deterioration in the withstand voltage of theMOS transistor 1 is prevented in a portion under theLOCOS oxide film 27 where the Ptype diffusion layer 4 is not formed, or in a portion under theLOCOS oxide film 28. - Finally, although not shown in the cross-sectional view of Fig. 3, a conductive plate 33 (see Fig. 1) having the same potential as that of the
epitaxial layer 7 is formed between a device region and an isolation layer near the region where the Ptype diffusion layer 4 is formed. Theconductive plate 33 is made of, for example, the same material as that of the gate electrode or the same material as that of the metal layers. A wiring layer or the like connected to the source electrode or the gate electrode is disposed above theconductive plate 33 with an insulating layer interposed in between. With this structure, theconductive plate 33 shields a depletion layer extending from the device region, and hence has an effect of shielding the wiring layer. Thus, theconductive plate 33 relieves convergence of an electric field in a vicinity of an end portion of theisolation region 31 located under the wiring layer, thus it is possible to improve the withstand voltage characteristics of theMOS transistor 1. - Although the description has been given for the case where the P
type diffusion layer 4 is formed only in the region where theLOCOS oxide film 27 has the width W1, the present invention is not limited to this case. For example, the Ptype diffusion layer 4 may be disposed to coincide with the shape of the round regions R, as in the case of the P type diffusion layers 3. Any change can be made in the design of each of the P type diffusion layers 2, 3 and 4 to be formed as the floating diffusion layers so that the P type diffusion layers 2, 3 and 4 may each have an impurity concentration, a diffusion depth, or the like depending on the withstand voltage characteristics of theMOS transistor 1. In addition to the above, various changes can be made without departing from the gist of the embodiment of the present invention. - In this embodiment, the N channel type MOS transistor is disposed in the elliptical shape, and round regions are used as the inactive regions. P type diffusion layers in the floating state are formed in the epitaxial layer in the inactive regions. This structure makes it possible to improve the withstand voltage characteristics in the inactive regions, and thus makes it possible to improve the withstand voltage characteristics of the MOS transistor.
- Moreover, in this embodiment, the P type diffusion layer having a lower impurity concentration is formed on the outermost periphery. This structure makes it possible to reduce the change in curvature of the end regions of the depletion layer, and thus makes it possible to improve the withstand voltage characteristics of the MOS transistor.
- Moreover, in this embodiment, the P type diffusion layer having a lower impurity concentration and a shallower diffusion depth is circularly formed. This structure makes it possible to improve the withstand voltage characteristics of the MOS transistor.
- Furthermore, in this embodiment, LOCOS oxide films are disposed only in the inactive regions, respectively. With the disposition of the contact hole, the P type diffusion layer having a greater diffusion depth is formed in a region where one of the LOCOS oxide films has a greater width. This structure makes it possible for the depletion layer to extend in the horizontal direction, and thus makes it possible to improve the withstand voltage characteristics of the MOS transistor.
Claims (6)
- A semiconductor device comprising:- a semiconductor layer (7) comprising an active region (L) and an inactive region (R), the active region (L) having a source region (12), a drain region (13, 14, 15) and a gate electrode (16) formed therein and the inactive region (R) having neither a source region, a drain region nor a gate electrode;- an insulating layer (18) disposed on the semiconductor layer (7);- a first diffusion layer (3) formed in the inactive region (R) so as to be floating;- a second diffusion layer (2) formed in the active and inactive regions (L, R) so as to be floating; and- a metal layer (30) disposed on the insulating film (18) so as to form capacitive coupling with the first and second diffusion layers (3, 2) where the first diffusion layer (3) merges with the second diffusion layer (2).
- The semiconductor device of claim 1, wherein an impurity concentration of the second diffusion layer (2) is lower than an impurity concentration of the first diffusion layer (3), and an outer edge portion of the second diffusion layer (2) is positioned closer to a corresponding outer edge portion of the inactive region (R) than a corresponding outer edge portion of the first diffusion layer (3) is.
- The semiconductor device of claim 1 or 2, wherein the inactive region (R) is of a semi-circular shape, and the first and second diffusion layers (3, 2) are curved to follow the shape of the inactive region (R).
- The semiconductor device according to any of claims 1 to 3, further comprising a field oxide (27, 28) formed in the inactive region (R) so as to be positioned under a contact hole (29) formed in the insulating layer (18), and a third diffusion layer (4) formed in the inactive region (R) and near the contact hole so as to be floating, wherein the metal layer (30) forms capacitive coupling with the second and third diffusion layers (2, 4) where the second diffusion layer (2) merges with the third diffusion layer (4).
- The semiconductor device of claim 4, wherein an impurity concentration of the second diffusion layer (2) is lower than an impurity concentration of the third diffusion layer (4), and an outer edge portion of the second diffusion layer (2) is positioned closer to a corresponding outer edge portion of the inactive region (R) than a corresponding outer edge portion of the third diffusion layer (4) is.
- The semiconductor device of claim 4 or 5, wherein a diffusion depth of the third diffusion layer (4) is greater than a diffusion depth of the first diffusion layer (3).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005263468A JP4791113B2 (en) | 2005-09-12 | 2005-09-12 | Semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1763083A2 true EP1763083A2 (en) | 2007-03-14 |
EP1763083A3 EP1763083A3 (en) | 2008-05-28 |
EP1763083B1 EP1763083B1 (en) | 2010-02-03 |
Family
ID=37568596
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP06019023A Expired - Fee Related EP1763083B1 (en) | 2005-09-12 | 2006-09-12 | Semiconductor device |
Country Status (7)
Country | Link |
---|---|
US (1) | US7652307B2 (en) |
EP (1) | EP1763083B1 (en) |
JP (1) | JP4791113B2 (en) |
KR (1) | KR100749230B1 (en) |
CN (1) | CN100454580C (en) |
DE (1) | DE602006012106D1 (en) |
TW (1) | TW200713580A (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4956351B2 (en) * | 2007-09-28 | 2012-06-20 | オンセミコンダクター・トレーディング・リミテッド | Manufacturing method of DMOS transistor |
KR101418396B1 (en) * | 2007-11-19 | 2014-07-10 | 페어차일드코리아반도체 주식회사 | Power semiconductor device |
JP5329118B2 (en) * | 2008-04-21 | 2013-10-30 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | DMOS transistor |
JP2010278312A (en) * | 2009-05-29 | 2010-12-09 | Sanyo Electric Co Ltd | Semiconductor device |
KR101800371B1 (en) * | 2011-05-27 | 2017-11-23 | 삼성전자주식회사 | Semiconductor device |
CN102637743B (en) * | 2012-05-02 | 2015-04-29 | 杭州士兰微电子股份有限公司 | Power device and manufacturing method thereof |
US9536944B2 (en) * | 2012-12-04 | 2017-01-03 | Denso Corporation | Semiconductor device and method of manufacturing same |
JP2016092032A (en) * | 2014-10-29 | 2016-05-23 | サンケン電気株式会社 | Semiconductor device |
WO2018123968A1 (en) * | 2016-12-28 | 2018-07-05 | 株式会社ツーセル | Repair agent for living tissue damage and method for producing said repair agent |
US11049967B2 (en) * | 2018-11-02 | 2021-06-29 | Texas Instruments Incorporated | DMOS transistor having thick gate oxide and STI and method of fabricating |
KR102291317B1 (en) * | 2019-07-24 | 2021-08-18 | 주식회사 키 파운드리 | Semiconductor Device with Controllable Channel Length and Manufacturing Method thereof |
KR102233049B1 (en) | 2019-07-24 | 2021-03-26 | 주식회사 키 파운드리 | Semiconductor Device with Controllable Channel Length and Manufacturing Method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000156495A (en) | 1998-11-20 | 2000-06-06 | Fuji Electric Co Ltd | High breakdown voltage lateral semiconductor device |
JP2005093696A (en) | 2003-09-17 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Lateral mos transistor |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4348600A (en) * | 1978-02-14 | 1982-09-07 | Motorola, Inc. | Controlled current source for I2 L to analog interfaces |
NL8204105A (en) * | 1982-10-25 | 1984-05-16 | Philips Nv | SEMICONDUCTOR DEVICE. |
US5512774A (en) * | 1988-02-08 | 1996-04-30 | Kabushiki Kaisha Toshiba | Dielectrically isolated substrate and semiconductor device using the same |
JPH05121738A (en) * | 1991-10-24 | 1993-05-18 | Fuji Electric Co Ltd | Semiconductor device having misfets |
EP0571027A1 (en) | 1992-05-21 | 1993-11-24 | Koninklijke Philips Electronics N.V. | Semiconductor device comprising a lateral DMOST with breakdown voltage raising zones and provisions for exchanging charge with the back gate region |
JP3203858B2 (en) * | 1993-02-15 | 2001-08-27 | 富士電機株式会社 | High breakdown voltage MIS field-effect transistor |
BE1007657A3 (en) | 1993-10-14 | 1995-09-05 | Philips Electronics Nv | SEMICONDUCTOR DEVICE WITH A FAST LATERAL DMOST EQUIPPED WITH A HIGH VOLTAGE FEED ELECTRODE. |
KR950021600A (en) * | 1993-12-09 | 1995-07-26 | 가나이 쯔또무 | Semiconductor integrated circuit device and manufacturing method thereof |
DE69427904T2 (en) * | 1994-05-31 | 2002-04-04 | Stmicroelectronics S.R.L., Agrate Brianza | Integrated semiconductor diode |
JP3356586B2 (en) * | 1995-06-01 | 2002-12-16 | 日本電気株式会社 | High breakdown voltage lateral MOSFET semiconductor device |
JPH09120995A (en) * | 1995-08-22 | 1997-05-06 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
US5708287A (en) * | 1995-11-29 | 1998-01-13 | Kabushiki Kaisha Toshiba | Power semiconductor device having an active layer |
JPH1050985A (en) * | 1996-07-31 | 1998-02-20 | Denso Corp | Semiconductor device having mis structure |
KR100332625B1 (en) * | 1999-11-10 | 2002-04-17 | 곽정소 | resistor structure of semiconductor integrated circuit using epitaxial layer |
KR100535062B1 (en) * | 2001-06-04 | 2005-12-07 | 마츠시타 덴끼 산교 가부시키가이샤 | High-voltage semiconductor device |
JP2003101017A (en) * | 2001-09-27 | 2003-04-04 | Mitsubishi Electric Corp | Semiconductor device |
JP2003303961A (en) | 2002-04-09 | 2003-10-24 | Sanyo Electric Co Ltd | Mos semiconductor device |
JP2005085975A (en) * | 2003-09-09 | 2005-03-31 | Matsushita Electric Ind Co Ltd | Semiconductor device |
US20050145922A1 (en) * | 2003-12-30 | 2005-07-07 | Joseph Farley | EEPROM and flash EEPROM |
JP4839578B2 (en) * | 2004-04-26 | 2011-12-21 | 富士電機株式会社 | Horizontal semiconductor device |
-
2005
- 2005-09-12 JP JP2005263468A patent/JP4791113B2/en not_active Expired - Fee Related
-
2006
- 2006-09-07 US US11/516,733 patent/US7652307B2/en active Active
- 2006-09-08 TW TW095133192A patent/TW200713580A/en not_active IP Right Cessation
- 2006-09-11 KR KR1020060087349A patent/KR100749230B1/en not_active IP Right Cessation
- 2006-09-12 DE DE602006012106T patent/DE602006012106D1/en active Active
- 2006-09-12 CN CNB2006101272193A patent/CN100454580C/en not_active Expired - Fee Related
- 2006-09-12 EP EP06019023A patent/EP1763083B1/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000156495A (en) | 1998-11-20 | 2000-06-06 | Fuji Electric Co Ltd | High breakdown voltage lateral semiconductor device |
JP2005093696A (en) | 2003-09-17 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Lateral mos transistor |
Also Published As
Publication number | Publication date |
---|---|
KR100749230B1 (en) | 2007-08-13 |
CN1933179A (en) | 2007-03-21 |
EP1763083A3 (en) | 2008-05-28 |
EP1763083B1 (en) | 2010-02-03 |
CN100454580C (en) | 2009-01-21 |
JP2007080919A (en) | 2007-03-29 |
TW200713580A (en) | 2007-04-01 |
TWI315912B (en) | 2009-10-11 |
JP4791113B2 (en) | 2011-10-12 |
DE602006012106D1 (en) | 2010-03-25 |
KR20070030142A (en) | 2007-03-15 |
US7652307B2 (en) | 2010-01-26 |
US20070057321A1 (en) | 2007-03-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1763083B1 (en) | Semiconductor device | |
US6593621B2 (en) | LDMOS field effect transistor with improved ruggedness in narrow curved areas | |
US10121887B2 (en) | Insulated gate semiconductor device and method | |
US7525133B2 (en) | Trench-gate MOS transistor composed of multiple conductors | |
US7692240B2 (en) | Insulated gate semiconductor device | |
US20050121718A1 (en) | Semiconductor device and method of fabricating the same | |
US20040119091A1 (en) | Semiconductor device and method of manufacturing the same | |
JP4491875B2 (en) | Trench type MOS semiconductor device | |
US11600540B2 (en) | Semiconductor device | |
WO2001069684A2 (en) | Field-effect semiconductor devices | |
US11189703B2 (en) | Semiconductor device with trench structure having differing widths | |
US11362207B2 (en) | Semiconductor device | |
US20090166731A1 (en) | Vertical-type field-effect transistor and manufacturing method thereof | |
US10340147B2 (en) | Semiconductor device with equipotential ring contact at curved portion of equipotential ring electrode and method of manufacturing the same | |
US11664448B2 (en) | Semiconductor device | |
US6501155B2 (en) | Semiconductor apparatus and process for manufacturing the same | |
JP7188230B2 (en) | semiconductor equipment | |
CN112038407A (en) | Semiconductor power device integrated with electrostatic discharge protection diode | |
JP5269389B2 (en) | Semiconductor device | |
US20240170569A1 (en) | Semiconductor device and method of manufacturing the same | |
US20230146397A1 (en) | Semiconductor device | |
US20230352521A1 (en) | Semiconductor device | |
JP5714413B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
JP3846395B2 (en) | MOS type semiconductor device | |
JP2022018931A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL BA HR MK YU |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL BA HR MK RS |
|
17P | Request for examination filed |
Effective date: 20081126 |
|
17Q | First examination report despatched |
Effective date: 20090105 |
|
AKX | Designation fees paid |
Designated state(s): DE FR GB NL |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 29/40 20060101ALI20090624BHEP Ipc: H01L 29/78 20060101AFI20090624BHEP Ipc: H01L 29/06 20060101ALI20090624BHEP Ipc: H01L 29/08 20060101ALN20090624BHEP Ipc: H01L 29/10 20060101ALN20090624BHEP |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB NL |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REF | Corresponds to: |
Ref document number: 602006012106 Country of ref document: DE Date of ref document: 20100325 Kind code of ref document: P |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: T3 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20101104 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: NL Payment date: 20130912 Year of fee payment: 8 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20130827 Year of fee payment: 8 Ref country code: FR Payment date: 20130826 Year of fee payment: 8 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20130930 Year of fee payment: 8 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 602006012106 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 602006012106 Country of ref document: DE |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20140912 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 602006012106 Country of ref document: DE Effective date: 20150401 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20150529 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20150401 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20140912 Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20150401 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20140930 |