EP1714327A1 - Ensemble comprenant un dispositif electroluminescent sur un substrat - Google Patents

Ensemble comprenant un dispositif electroluminescent sur un substrat

Info

Publication number
EP1714327A1
EP1714327A1 EP04701336A EP04701336A EP1714327A1 EP 1714327 A1 EP1714327 A1 EP 1714327A1 EP 04701336 A EP04701336 A EP 04701336A EP 04701336 A EP04701336 A EP 04701336A EP 1714327 A1 EP1714327 A1 EP 1714327A1
Authority
EP
European Patent Office
Prior art keywords
light emitting
ring
substrate
emitting device
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04701336A
Other languages
German (de)
English (en)
Inventor
Walter Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asetronics AG
Original Assignee
Asetronics AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asetronics AG filed Critical Asetronics AG
Publication of EP1714327A1 publication Critical patent/EP1714327A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • H01L33/60Reflective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64Heat extraction or cooling elements
    • H01L33/642Heat extraction or cooling elements characterized by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64Heat extraction or cooling elements
    • H01L33/647Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body

Definitions

  • the present invention relates to an arrangement with at least one light emitting device, a light emitting diode (LED) or a chip comprising one ore more light emitting diodes (LEDs) , placed on a substrate according to claim 1.
  • LED light emitting diode
  • LEDs light emitting diodes
  • the present invention further relates to an arrangement with an array of light emitting devices placed on said substrate.
  • the present invention relates in particular to an arrangement with at least one light emitting device and means designed to dissipate the thermal energy generated by the light emitting device as well as means used to reflect the light emitted by the light emitting device.
  • arrays of LEDs may be employed in a variety of high flux (optical energy/unit time) applications such as street lighting, traffic signals, and liquid crystal display back-lighting.
  • high flux optical energy/unit time
  • the spacing between LEDs in the array is decreased (thus increasing the number of LEDs per unit area of the array) and/or the flux provided by the individual LEDs is increased.
  • either approach to increasing the flux per unit area of an LED array also increases the thermal energy that must be dissipated to avoid significant degradation of the performance of the LEDs.
  • LED arrays described in [1] are placed on an insulated metal substrate IMS comprising a dielectric layer disposed above a metal substrate that acts i.a. as a heat sink (see figure 1 below) .
  • a plurality of electrically conductive traces is disposed on the dielectric layer and a plurality of vias pass through the dielectric layer.
  • Each of the LEDs is disposed above a corresponding one of said vias and includes a first and a second electrical BESTATIGUNGSKOPIE contact electrically coupled to separate ones of the electrically conductive traces.
  • Each of the vias contains a thermally conductive material in thermal contact with the metal substrate and the corresponding LED.
  • the thermally conductive material may include, for example, a solder material.
  • the thermally conductive material in a via is in direct physical contact with the metal substrate and the corresponding LED. Such direct physical contact is sufficient but not necessary to establish thermal contact.
  • the thermally conductive material in a via provides a low thermal resistance path for heat to flow from an LED disposed above the via to the metal substrate, which then effectively conducts the heat away. Consequently, LEDs in arrays may be operated at higher currents and may be spaced closer together without raising their temperatures to levels that degrade their performance .
  • a reflective base may be realised by forming a concave recess on the substrate, e.g. on a printed circuit board. Then a metal reflective layer is applied to the recess, followed by die bonding or wire bonding the mounted LED and encapsulation.
  • solder points act as vias that, as described in [1], transport the thermal energy generated by the LED to its other end, where a heat-dissipating material, such as a metal substrate is preferably applied (see [2] , figure 5 and figure 2 below) .
  • the solution described in [1] does not comprise a reflective element that directs the light emitted by the LED towards the application area.
  • the efficiency of the LED array is reduced by a partial misguidance of the light beams. This is especially disadvantageous in applications where the light should be emitted in a narrow beam, as often required with traffic lights.
  • the process for manufacturing the reflecting element as described in [2] is however extremely laborious, requiring numerous process steps. Still further, this process may not be used with substrates, e.g. multi-layered substrates that do not allow drilling holes.
  • a second embodiment described in [2] (see figures 8 to 14) that requires the build up and forming of metal structures on the surface of the printed circuit board is cumbersome as well. The placement and bonding procedures in the grooves formed in the solder points (vias) or the metal structures are difficult to perform as well. The use of further bonding techniques is limited since electrically conductive traces are not available or can not easily be arranged within said dish-shaped grooves.
  • the resin encapsulations and lenses used to seal the LEDs and/or to direct the light beams can often not easily and precisely be placed with the arrangements described in [1] and [2] .
  • LED light emitting diode
  • LEDs light emitting diodes
  • the arrangement comprises a substrate with a plurality of electrically conductive traces and at least one light emitting device, a light emitting diode or a chip comprising one ore more light emitting diodes, preferably surface mounted on the substrate and connected with a first and a second electrical contact to said electrically conductive traces.
  • a ring is placed onto the substrate in such a way that it surrounds the light emitting device.
  • the ring comprises a lower surface, that is attached, preferably bonded to the substrate, and an upper surface, that is designed to reflect the light emitted by the light emitting device.
  • the light emitting device can therefore be placed, preferably surface mounted on the substrate and bonded to the electrically conductive traces with conventional techniques and machinery as used for any other device that is mounted on the substrate.
  • the light emitting device is contained in a ball grid array package and bonded to the electrically conductive traces by means of ball grid array technique (ball grid array techniques are described in [3] , BGA (Ball Grid Array) , National Semiconductor Corporation, Application Note 1126, issued August 2003) . Since the surface of the substrate is flat, the connections resulting from the bonding processes, i.e. processes used for connecting the electrodes of the light emitting device to the electrically conductive traces, are of standard high quality.
  • the rings which may be round, circular or rectangular, can be picked and placed, e.g. by means of a vacuum picker device, in the same manner as any surface mounted device so that the manufacturing of the inventive arrangements can be performed rapidly and at low cost.
  • the rings are formed accordingly, preferably provided with a flat area that allows coupling with the vacuum picker device.
  • the rings are made of a thermally and electrically conductive material that allows efficient transfer of thermal energy and that can be bonded to electrical contacts, e.g. to the metal substrate, an electrode of the light emitting device or to the electrically conductive traces.
  • an array of rings formed in one piece is placed onto the substrate so that each of the rings surrounds a light emitting device. All the interconnected rings, i.e. the ring array, can therefore be mounted in one process step. Further the ring array itself can easily be manufactured with an individual orientation of the reflection axes of the reflecting upper surfaces of the rings.
  • the light emitting device and the ring are attached to the substrate preferably by means of a thermally conducting adhesive or solder.
  • a thermally conducting adhesive or solder In order to achieve an optimal transfer of thermal energy the lower surface of the ring may directly be soldered to a metallic element of the substrate, possibly to one of the electrically conductive traces that lead to ground and that may be connected to the metallic heat sink. Efficient heat dissipation from the light emitting device to the heat sink results further from the bonding connections.
  • the reflecting upper surface of the ring is formed at least approximately as a parabolic reflector, a conical reflector or an angular, e.g. a pyramidal reflector. Furthermore the light emitting device is preferably placed in or close to the focus of the parabolic reflector or the vertex of the conical reflector.
  • the reflecting upper surface of the ring is preferably coated with a film of highly reflective material such as silver in order to obtain a good light reflection with low losses.
  • the metal coating may me plated or evaporated onto the upper surface of the ring.
  • the reflective upper surface of the ring may be formed in such a way that the axis of the reflector of the ring is in line or inclined to a line standing perpendicular to the substrate.
  • the axes auf the light beams emitted by the LEDs of an array may therefore individually be directed towards at least one distant target (regarding technological background see [4] , US 6,554,451 Bl, a method for illuminating an object by means of a plurality of LEDs) .
  • the inventive solution may be applied on different substrates that comprise heat-dissipating material such as printed circuit boards or insulated metal substrates (IMS) , for example as described in [1] and [2] .
  • IMS insulated metal substrates
  • the substrate is preferably an insulated metal substrate (IMS) with an electrically insulating, but thermally conducting dielectric layer or an insulated metal substrate (IMS) with a dielectric layer through which pass one or more thermally conducting vias, that are located at positions, where the light emitting devices or the rings are placed, in order to transfer thermal energy from the light emitting devices directly or via the rings to the heat sink.
  • IMS insulated metal substrate
  • IMS insulated metal substrate
  • the light emitting device and the ring are covered by an optically transmissive encapsulation preferably made by at least one layer of a resin, for example as described in [5], US 6,351,069 Bl .
  • an optically transmissive encapsulation preferably made by at least one layer of a resin, for example as described in [5], US 6,351,069 Bl .
  • the encapsulation may be formed with one or more layers that may have different functionalities.
  • the lowest layer, that covers the light emitting device, may have a high thermal conductivity while an upper layer may comprise supplementary fluorescent material that radiates secondary light, in order to adjust the spectrum of the emitted light.
  • the ring comprises an annular groove, preferably arranged concentrically above the reflective upper surface and designed; either to receive resin during the fabrication of the encapsulation, preferably to provide a borderline for the flow of resin and to hold the encapsulation in place; or to receive and hold a lens that collects and directs light emitted by the light emitting device.
  • the ring also facilitates the fabrication of the encapsulation.
  • Figure 1 shows an arrangement 1000 with an LED or LED chip mounted on a substrate as described in [1] ;
  • Figure 2 shows an arrangement 1001 with an LED or LED chip mounted on a substrate as described in [2] ;
  • Figure 3 shows a preferred embodiment of an inventive arrangement 1 with a light emitting device 2 that is placed on a substrate 15, asymmetrically BGA-bonded to conductive traces 101, 102 and that is surrounded by a ring 6 with a reflective upper surface 61;
  • Figure 4 shows a further embodiment of an inventive arrangement 1 with a light emitting device 2 that is BGA bonded to one conductive trace 102 and that is wire-bonded to the ring 6, which is soldered to the other conductive trace 101;
  • Figure 5 shows a further embodiment of an inventive arrangement 1 with a light emitting device 2 that is placed on a substrate 15 and that is thermally connected to a heat sink layer 12 of the substrate 15 by means of a via 13;
  • Figure 6 a further inventive arrangement with an encapsulation 3 that comprises a lens 31, which is placed onto the ring 6 and an encapsulant, which has been injected through a channel 150 provided in the substrate 15;
  • Figure 7 shows a sectional view of a ring 6 comprising a vertical reflection axis x
  • Figure 8 shows a sectional view of a ring 6 comprising an non- vertical reflection axis x' ;
  • Figure 9 shows a section of an inventive arrangement 1 with an array of light emitting devices 2 and rings 6 from the top;
  • Figure 10 shows an array of six light emitting devices 2 that are connected in parallel to conductive traces 101, 102 by means of asymmetrical BGA bonding;
  • Figure 11 shows a further circuit arrangement for the light emitting devices 2;
  • Figure 12 an inventive arrangement with an array 60 of interconnected rings 6a; ..., 6i.
  • Figure 1 shows the arrangement of [1] , figure 1 with an LED 2 or LED-chip mounted on an insulated metal substrate IMS 15 consisting of a metal substrate 12 that is covered by a dielectric layer 11 and a trace layer 10 comprising conventional electrically conductive traces that are connected by means of solder points 4 to the electrodes 21, 22 of the LED 2.
  • IMS 15 Located below the LED 2 is thermally conducting material 13 of a via, which passes through the trace layer 10 and the dielectric layer 11 to terminate on or in metal substrate 12.
  • LED 2 also includes a thermal contact 131 (e.g., a metal pad) that in some implementations may electrically be isolated from the electrodes 21, 22 of the LED 2. Such electrical isolation may be provided, for example, by an optional dielectric layer.
  • the arrangement also includes an encapsulation with a lens 3 that is disposed over the LED 2 to collect and direct light emitted by the LED 2.
  • a lens 3 that is disposed over the LED 2 to collect and direct light emitted by the LED 2.
  • such lenses may be conventionally cast or moulded in clear plastic or elastomer onto some or all of the LEDs 2 of a an LED-array.
  • silicone or similar clear material may be conventionally dispensed onto some or all of the LEDs 2 and then cured to form simple lenses.
  • hollow clear lenses may be conventionally heat staked, glued, or press fit over some or all of the LEDs 2 and then filled with silicone, for example, to encapsulate the LEDs 2.
  • LEDs that may be used for an LED array are described for example in [1] , which is incorporated herein in its entirety.
  • the arrangement described in [1] does not use a reflector.
  • the light, which is not collected by the lens 3, is not directed to the target, but lost as stray light.
  • Figure 2 shows the arrangement of [2] , figure 5 with an LED 2 or LED-chip mounted on a printed circuit board PCB 15' that is covered on the lower side with heat-dissipating material and on the upper side with a trace layer 10 comprising conventional electrically conductive traces that are bonded to the electrodes of the LED 2.
  • the LED 2 is disposed on a solder point 5 that has been filled into a hole, which was drilled into the PCB 15' and plated with a metal sleeve 7.
  • the LED 2 is located above thermally conducting material 13 of a via that passes through the trace layer 10 and the PCB 15' to terminate on or in a metal substrate 12.
  • the upper side of the solder point comprises a dish shaped form with a flat central portion 52, that is designed for mounting the LED 2, that is adjoined by a conical sidewall 51 designed to reflect the light emitted by the LED 2.
  • fabricating the solder point with the dish shaped form on one side requires numerous process steps. Further, the placement and contacting of the LED can not be performed on the same plane and with the same means as with other electrical elements placed on the PCB 15' that can be connected to the electrically conductive traces of the trace layer 10.
  • Figure 3 shows an inventive arrangement 1 with a light emitting device 2, an LED or a chip comprising one ore more LEDs, that is placed on an insulated metal substrate 15 comprising a metal substrate 12 that is covered by a dielectric layer 11 and a trace layer 10 incorporating electrically conductive traces 101, 102.
  • the electrodes of the light emitting device 2 are connected to the trace layer 10 by means of a ball grid array technique, for example as described in [3] .
  • Ball grid array (BGA) techniques provide several advantages over conventional bonding techniques, in particular higher packing densities and improved thermal and electrical performance, while being compatible with existing Surface Mount Technology (SMT) infrastructure.
  • SMT Surface Mount Technology
  • Light emitting devices 2 can therefore be designed as ball grid array packages and placed and connected with BGA-technology to the electrically conducting traces 10 provided on the surface of the substrate 15. However any other Surface Mount Technology (SMT) is also applicable.
  • SMT Surface Mount Technology
  • the ring 6 can easily be picked and placed before or preferably after the light emitting device 2 has been mounted.
  • the lower surface 62 of the ring 6 may be attached to the substrate 15 in different ways.
  • the ring 6 is attached, soldered or glued with a thermally conducting adhesive, to the trace layer 10 and/or to the dielectric layer 11.
  • the lower surface 62 of the ring 6 is electrically insulated from the first conductive trace 101 by means of a varnish layer 18.
  • the second conductive trace 102 is connected, e.g. soldered or glued to the lower surface 62 of the ring 6 and/or to the metal substrate 12. Thermal energy can therefore efficiently be transferred to the ring 6 and/or to the metal substrate 12 via the second conductive trace 102.
  • the light emitting device 2 comprises asymmetrical bonding areas for the electrodes 21, 22.
  • the first electrode 21 comprises a small area which is sufficient for bonding the electrode 21 to the first conducting trace 101.
  • the second electrode 21 comprises a large area which is designed for bonding the electrode 21 to a corresponding area of the second conducting trace 101 in order to establish an electrical connection and to provide a high thermal conductivity.
  • the second electrode 22 comprises therefore a ball grid array with a comparably high number of balls. After the placement of the light emitting device 2 a heating process is applied that melts and connects the balls to the conductive traces 101, 102.
  • Figure 4 shows a further embodiment of an inventive arrangement 1 with a multi-layered light emitting device 2 with the second electrode 22 BGA-bonded to one conductive trace 102 and with the first electrode 21 wire-bonded to the ring 6 (see wire 210) , which is connected by solder 110 to the other conductive trace 101.
  • the lower surface of the light emitting device 2 is completely covered and connected to the conductive trace 102 by means of the second electrode 22, thus providing an optimal transfer of thermal energy.
  • the light emitting device 2, the ring 6 and/or the trace layer 10 may also be thermally connected to the metal substrate 12 by means of vias.
  • Figure 5 shows an inventive arrangement 1 with a light emitting device 2 that is mounted on a substrate 15. Located below the light emitting device 2 is thermally conducting material of a via 13, which passes through the trace layer 10 and the dielectric layer 11 to terminate on or in the metal substrate 12.
  • the light emitting device 2 in this preferred embodiment includes a thermal contact 131 that in some implementations is electrically isolated from one or both of the electrodes 21, 22.
  • the ring 6, or a part 69 of it, is in direct contact with the metal substrate 12.
  • the ring 6 may have recesses 64 acting as passage ways (see figure 4) .
  • a section of the ring 6 may be cut off.
  • the upper surface 61 of the rings 6 shown in figures 3 to 5 is designed to reflect the light emitted by the light emitting device 2.
  • the ring 6 is preferably made of metal that may be covered with a film of highly reflective material such as silver, gold or ni-palladium in order to avoid diffuse reflectance .
  • the upper surface 61 of the ring 6 is formed at least approximately as a parabolic reflector, a conical reflector or an angular reflector, e.g. a pyramidal reflector in order to obtain good beam directivity.
  • the light emitting device 2 is preferably placed in or close to the focus of the parabolic reflector or the vertex of the conical reflector, so that all the stray light emitted by the light emitting device 2 is redirected by the reflecting upper surface 61.
  • the reflecting upper surface 61 of the ring 6, 6' designed in such a way, that the axis x; x' of the reflector is in line (see figure 7) or inclined (see figure 8) to a line standing perpendicular to the substrate 15 or to the plane of the lower surface 62, thus pointing into a desired direction.
  • the arrangement may comprise an array of light emitting devices 2, each placed in a central, round or angular gap 65 of the related ring 6; 6a, ..., 6i.
  • Figure 12 shows that the rings 6 of the array comprise a flat wing element 68 that, for mounting purposes, can be grasped by means of a vacuum picker device.
  • the wing element 68 can be wire-bonded to the corresponding electrode 21 of the light emitting device 2 (see figure 5) .
  • Other techniques for picking and placing the rings 6 are also applicable.
  • an adhesive tape 150 may be applied to the rings 6 that can be contacted by a picking tool.
  • the array of rings 6a, ..., 6i is formed as one piece or a ring mask that can be placed onto the substrate 15 in one process step.
  • the reflecting upper surfaces 61, 61' of the rings 6a, ..., 6i may comprise flat planes or a round, conical or parabolic form.
  • Figures 10 and 11 show electrical circuits with light emitting devices 2 connected to electrically conductive traces.
  • Figure 10 shows an array of six light emitting devices 2 that are connected in parallel to the conductive traces 101, 102 by means of the inventive asymmetrical BGA bonding.
  • the contact areas of the second electrodes 22 of the light emitting devices 2, which are approximately four times the size of the areas of the first electrode 21, are arranged adjacent to each other above a rectangular stripe of the second conductive trace 102, which is preferable connected to the electrical and/or to the thermal ground, e.g. to the metal substrate 12.
  • the thermal energy generated by each light emitting device 2 can therefore be transferred across a large electrode area while the comparably small size of the area of the first electrode 21 is absolutely sufficient for establishing an electrical contact.
  • the ratio of the areas of the electrodes 21, 22 may be selected in such a way that a sufficient electrical contact can be established with the first electrode 21 while the area of the second electrode is maximised.
  • the ratio that depends on the size of the light emitting device 2 and the applied bonding technology may therefore be up to 1:10 or far higher.
  • Figure 11 shows a further circuit arrangement with four light emitting devices 2 that are connected, pair by pair in series and parallel .
  • the light emitting device 2 and the ring 6 are preferably covered by an optically transmissive encapsulation 3 that may provide several functions.
  • the encapsulation 3 is designed to protect the light emitting device 2, to collect and direct the light emitted by the light emitting device 2, to adjust the wavelength spectrum and, as described below, to transfer thermal energy from the light emitting device 2 to the ring 2.
  • the encapsulation 3 may be formed with one or more layers that may have different functionalities. The lowest layer, that covers the light emitting device 2, may have a high thermal conductivity while an upper layer may comprise supplementary fluorescent material that radiates secondary light, in order to adjust the spectrum of the emitted light.
  • the ring 6 may also be covered by a lens 31 that collects and directs the light of the light emitting device 2.
  • the space enclosed within the ring 6 and the lens 31 may preferably be filled with an encapsulant 32 such as silicone .
  • the ring 6 preferably comprises holding means such as an annular groove 63 that is preferably arranged above the reflective upper surface 61, said groove 63 being designed either to be filled with resin during the fabrication process of the encapsulation 3 or to receive and hold the lens 31. Placement and precise alignment of the lens 31 is therefore facilitated.
  • Figure 6 shows an arrangement with a lens 31 that has been placed into the annular groove 63 of the ring 6.
  • the space below the lens 31 has been filled with an encapsulant 32 that has been injected through a channel 150 provided in the substrate 15.
  • one or more vent channels 151, 67 are provided in the substrate 15 and/or in the ring 6.
  • the invention can be applied with different substrate architectures, different kinds of LEDs, different LED-packages, in particular Ball Grid Array or Land Grid Array-chip-packages or derivates thereof, and different techniques to connect the LEDs and LED-packages to the electrically conductive traces 10. Further, various forms and materials are applicable for the encapsulation 3. Hence, besides Ball Grid Array technology further grid array technologies such as Land Grid Array technology is analogously applicable. Form, material and coating of the ring 2, as well as the materials, adhesives or solder, and techniques to attach the ring 2 to the substrate 15 or to the metal layer 12 can be selected according to the given requirements by a man skilled in the art. Still further the invention is not limited to

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un ensemble qui comprend un substrat (15) comportant une pluralité de tracés conducteurs (10) et au moins un dispositif électroluminescent (2), de type diode électroluminescente ou puce comprenant une ou plusieurs diodes électroluminescentes, ledit dispositif étant de préférence monté en surface sur le substrat (15) et relié au moyen d'une première et d'une deuxième électrode électrique (21, 22) auxdits tracés électroconducteurs (10). Un anneau (6), positionné sur le substrat (15) et entourant le dispositif électroluminescent (2), comprend une surface inférieure (62) qui est reliée au substrat (15), et une surface supérieure (61) qui est conçue pour réfléchir la lumière émise par le dispositif électroluminescent (2) dans une direction désirée. Outre les propriétés avantageuses de collecte et de redirection de lumière, l'anneau (6) permet de positionner de manière précise une enveloppe (3) ou une lentille (31) pouvant faire partie de l'enveloppe (3), et absorbe l'énergie thermique issue de ladite enveloppe (3) qui a été transférée depuis la partie supérieure et les parois latérales dudit dispositif électroluminescent (2).
EP04701336A 2004-01-12 2004-01-12 Ensemble comprenant un dispositif electroluminescent sur un substrat Withdrawn EP1714327A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CH2004/000005 WO2005067063A1 (fr) 2004-01-12 2004-01-12 Ensemble comprenant un dispositif electroluminescent sur un substrat

Publications (1)

Publication Number Publication Date
EP1714327A1 true EP1714327A1 (fr) 2006-10-25

Family

ID=34744490

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04701336A Withdrawn EP1714327A1 (fr) 2004-01-12 2004-01-12 Ensemble comprenant un dispositif electroluminescent sur un substrat

Country Status (2)

Country Link
EP (1) EP1714327A1 (fr)
WO (1) WO2005067063A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3792986A1 (fr) * 2019-08-13 2021-03-17 Coreled Systems, LLC Dispositifs optiques montés en surface

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1872401B1 (fr) 2005-04-05 2018-09-19 Philips Lighting Holding B.V. Boitier de dispositif electronique a evaporateur integre
DE102006015335B4 (de) 2006-04-03 2013-05-02 Ivoclar Vivadent Ag Halbleiter-Strahlungsquelle sowie Lichthärtgerät
DE102006015377B4 (de) * 2006-04-03 2018-06-14 Ivoclar Vivadent Ag Halbleiter-Strahlungsquelle sowie Lichthärtgerät
US7906794B2 (en) 2006-07-05 2011-03-15 Koninklijke Philips Electronics N.V. Light emitting device package with frame and optically transmissive element
CN101536179B (zh) 2006-10-31 2011-05-25 皇家飞利浦电子股份有限公司 照明设备封装
DE102007053849A1 (de) * 2007-09-28 2009-04-02 Osram Opto Semiconductors Gmbh Anordnung umfassend ein optoelektronisches Bauelement
WO2013175333A1 (fr) * 2012-05-23 2013-11-28 Koninklijke Philips N.V. Dispositif à semiconducteurs montable en surface
DE102012110774A1 (de) * 2012-11-09 2014-05-15 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6182486A (ja) * 1984-09-29 1986-04-26 Sharp Corp 固体発光表示装置
JPH08204239A (ja) * 1995-01-31 1996-08-09 Rohm Co Ltd 樹脂封止型発光装置
JP2000269551A (ja) * 1999-03-18 2000-09-29 Rohm Co Ltd チップ型発光装置
JP3696020B2 (ja) * 2000-01-20 2005-09-14 三洋電機株式会社 混成集積回路装置
US6345903B1 (en) * 2000-09-01 2002-02-12 Citizen Electronics Co., Ltd. Surface-mount type emitting diode and method of manufacturing same
JP2002319711A (ja) * 2001-04-20 2002-10-31 Citizen Electronics Co Ltd 表面実装型発光ダイオード及びその製造方法
KR100439402B1 (ko) * 2001-12-24 2004-07-09 삼성전기주식회사 발광다이오드 패키지

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2005067063A1 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3792986A1 (fr) * 2019-08-13 2021-03-17 Coreled Systems, LLC Dispositifs optiques montés en surface
US11252821B2 (en) 2019-08-13 2022-02-15 CoreLed Systems, LLC Optical surface-mount devices

Also Published As

Publication number Publication date
WO2005067063A1 (fr) 2005-07-21

Similar Documents

Publication Publication Date Title
JP5520243B2 (ja) 電力表面取り付けの発光ダイ・パッケージ
EP2139051B1 (fr) Boîtier de diode électroluminescente pour montage en surface
US7728341B2 (en) Illumination device for providing directionally guided light
US8541797B2 (en) Illuminator and method for producing such illuminator
US8044423B2 (en) Light emitting device package
KR100653645B1 (ko) 발광소자 패키지 및 발광소자 패키지 제조방법
US8399267B2 (en) Methods for packaging light emitting devices and related microelectronic devices
KR20060121261A (ko) 조명 조립체
US8487339B2 (en) Light-emitting diode chip package body and method for manufacturing same
US20110084612A1 (en) Hybrid chip-on-heatsink device and methods
EP2472616B1 (fr) Conditionnement de dispositif électroluminescent et son procédé de fabrication
WO2005067063A1 (fr) Ensemble comprenant un dispositif electroluminescent sur un substrat
US10784423B2 (en) Light emitting device
KR102503855B1 (ko) 매트릭스 배열 마이크로 칩 모듈 및 그 제조방법
KR20060112836A (ko) 전자부품 패키지
KR101768908B1 (ko) 메탈 인쇄회로기판 및 그 제조 방법, 엘이디 패키지 구조물 및 그 제조 방법
CN103208584A (zh) 具有倾斜结构的发光二极管封装
KR101995538B1 (ko) 발광 반도체를 상호 접속하기 위한 오버레이 회로 구조체
KR20190079598A (ko) 발광 반도체를 상호 접속하기 위한 오버레이 회로 구조체

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20060814

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20070411

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20120317