EP1636781A1 - Display device addressing method with alternating row selecting order and intermediate off pulses - Google Patents

Display device addressing method with alternating row selecting order and intermediate off pulses

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Publication number
EP1636781A1
EP1636781A1 EP04736246A EP04736246A EP1636781A1 EP 1636781 A1 EP1636781 A1 EP 1636781A1 EP 04736246 A EP04736246 A EP 04736246A EP 04736246 A EP04736246 A EP 04736246A EP 1636781 A1 EP1636781 A1 EP 1636781A1
Authority
EP
European Patent Office
Prior art keywords
row
electrodes
sub
voltage
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04736246A
Other languages
German (de)
French (fr)
Inventor
Roel Van Woudenberg
Sebastiaan De Bont
William P. M. M. Jans
Johannis L. Hoppenbrouwers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP04736246A priority Critical patent/EP1636781A1/en
Publication of EP1636781A1 publication Critical patent/EP1636781A1/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/3473—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on light coupled out of a light guide, e.g. due to scattering, by contracting the light guide with external means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/063—Waveforms for resetting the whole screen at once
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/2029—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames having non-binary weights

Definitions

  • the present invention relates to a method for addressing a display device having a set of row electrodes and a set of column electrodes for addressing a plurality of pixels defined by intersections of said electrodes, wherein, during a first period, an ON-select voltage is applied to one row electrode at a time such that pixels connected to this row electrode can be switched ON by a data signal applied to the column electrodes.
  • the invention also relates to a display driver for implementing such a method, and a display device comprising such a driver.
  • Fig. 1 The switching curves of such a pixel element being addressed by voltages applied on row and column electrodes is shown in Fig. 1, where the x- and y-axis represent the row and column voltages respectively.
  • the pixel For a combination of row and column voltages (Vrow,seioN, Vcoi.seiON), the pixel is switched ON 10, and for another combination of row and column voltages (N ro w,seioFF, V co i, S eioFF), the pixel is switched OFF 12.
  • addressing is performed in the following way.
  • the addressing sequence for a frame starts with all pixels in the OFF-state. Then, all but one row is put at the 5 unselect voltage (V r0 w,unsei) and remains in its current state (hence OFF) when the data voltages (V co ⁇ ,sei ⁇ N or V C oi,seioFF) are applied on the column voltage.
  • One row is put at the ON- select voltage (V row ,sei ⁇ N)- At this voltage, a pixel will switch ON and emit light when the column voltage is at V co ⁇ jSe i ⁇ N5 while it will remain in its current position (hence OFF) when the column voltage is V co ⁇ ,sei ⁇ FF.
  • the rows are addressed sequentially during a first scan, to allow switching all pixels ON, and then a second sequential scan is performed during which the selective row voltage is V row ,sei ⁇ FF, and all column voltages are put to V co ⁇ ,sei ⁇ FF, i-e. all pixels are finally switched to the OFF state.
  • the frame period is divided into several pairs of such ON- and OFF -scans, each such pair being referred to as a sub-field.
  • Grey scales can be accomplished by switching a pixel ON during appropriate sub- fields, which sub-fields preferably are weighted, for example in a binary fashion (binary weighted sub-fields, BWS).
  • BWS binary weighted sub-fields
  • the weight of a sub-field depends on the number of time slots of the frame it occupies.
  • the sub- fields are organized in an addressing scheme, which describes in what order the rows are being addressed with ON and OFF addressing actions.
  • An object of the present invention is to provide an addressing scheme which is improved compared with known addressing schemes.
  • a particular object is to provide an addressing scheme with improved switching. These and other objects are achieved by a method of the kind mentioned by way of introduction, further comprising during a second period, applying the O ⁇ -select voltage to one row electrode at a time in reverse order compared to said first period, and in a time slot between said first and second periods, applying to all columns electrodes an OFF voltage adapted to place all pixels in the set in the OFF state.
  • the "set" of the electrodes not necessarily includes all electrodes of the display. On the contrary, the electrodes of the display may advantageously be divided into several sets, in order to provide a more efficient addressing.
  • the invention is based on the understanding that it is easier to switch OFF a complete column of the display compared to switching OFF a particular pixel in that column.
  • a complete column may be switched OFF by applying to all column electrodes a robust voltage level so that all the pixels are placed in the OFF state regardless of the row voltage levels.
  • the robust OFF pulse the whole display is erased, and it is possible to provide an addressing scheme which is very robust.
  • One advantage with applying the robust OFF pulse is that the row voltage level previously used to switch pixels OFF no longer is necessary, which facilitates the operation of the display. It also means that only one row-column voltage combination is outside the bi-stable region, which enables lower voltage swings compared to Fig. 1, i.e.
  • the ON-scan is repeated in reverse order after the robust OFF-switch, which results in that all rows are able to be in the ON state for the same amount of time.
  • the repeated ON-scan can also enable flicker reduction.
  • the method according to the invention can be implemented in an addressing scheme of the type where a frame period is divided into a plurality of sub-fields, and the first and second periods can then together form a sub-field.
  • the method according to the invention provides more freedom in choosing sub-field weight and order of the sub-fields, and thus removes some of the restrictions present in previous addressing schemes.
  • the display device comprises several sets of row electrodes, whereby the above mentioned steps of applying the first and second voltage levels are preformed for each set in such a way that during the addressing frame, the sub-fields appear in a different order for each set.
  • each row electrode set displays information from a different sub-field.
  • the addressing steps i.e. the steps in which a row for example is switched ON
  • the sub-fields preferably have weights of an increasing order of 1, 2, 3, 4, 5, etcetera. This enables that the addressing time slots may be distributed optimally over the frame in order to increase the available addressing time.
  • Another advantage with this weighting compared to binary weighted sub-fields is that there are several ways to display one grey level (for example grey level 4 may be displayed as sub- field 4 or sub-field 1+3). By using many active sub-fields to display a grey scale (i.e.
  • the row electrodes are preferably addressed one at a time in a successive order, from one end of the row electrode set to the opposite end of the set.
  • the ON-scan may start by addressing the row electrode at the top of the display, continue with each consecutive, adjacent row electrode in a direction downwards, and finish by addressing the row electrode at the bottom of the display.
  • the addressing in each set may start by addressing of the row electrode at the top of the set, continue with each consecutive, adjacent row electrode in a direction downwards, and finish by addressing the row electrode at the bottom of the set.
  • the OFF voltage is applied to all columns electrodes in the set in a time slot during said first period and a time slot during said second period.
  • This additional robust OFF pulse during the first and second periods divides the ON-scan into sub-periods, enabling a reduction of the weight of the lowest sub-field. This in turn, allows reduction of the number of time slots, and hence an increased available row selection time. A longer row selection time makes the display easier to operate.
  • the first and second periods may each be divided into for example two or four sub-periods. When dividing each period into two sub-periods, the additional robust OFF pulse is consequently applied once during the first period, and once during the second period.
  • the additional robust OFF pulse may for example be applied in a time slot when half of the rows of the display has been placed in the ON enabling state, i.e. halfway through the ON- scan. After the additional robust OFF pulse, the ON-scan continue in order to place the remaining rows of the display in the ON state.
  • the additional robust OFF pulse may be applied only for the sub- fields with the lowest weights, i.e. sub-fields that are smaller than the number of rows of the display (L).
  • This addressing scheme is more time-efficient.
  • the method according to the invention can be advantageously implemented in a dynamic foil display.
  • Fig. 1 illustrates the switching curves of a pixel element having a bi-stable region.
  • Fig. 2 is a side view of a dynamic foil display.
  • Fig. 3 illustrates a conventional addressing scheme for a display having bistable pixel elements.
  • Fig. 4 illustrates the switching curves of a pixel element having a bi-stable region, and robust OFF.
  • Figs. 5a-5d show four addressing schemes according to one embodiment of the invention.
  • Figs. 6a-6c show three addressing schemes according to another embodiment of the invention comprising additional robust OFF pulses.
  • Figs. 7a-7b show two addressing schemes according to a further embodiment of the invention, wherein the set rows electrodes are divided into sub-sets of row electrodes.
  • such a display comprises a light guide 20 in the form of an edge lit glass plate and a non- lit back plate 22, with a scattering foil 24 clamped in between.
  • Light from a light source 26 is coupled into the light guide 20.
  • On both plates there are respective sets of parallel electrodes which are arranged perpendicularly with respect to each other.
  • the electrodes on the light guide are referred to as column electrodes 28, while the electrodes in the back plate are row electrodes 30.
  • the voltages applied to the electrodes are controlled by a row driver and a column driver.
  • Fig. 3 An example of an addressing scheme is illustrated in Fig. 3.
  • checked boxes 32 indicate time slots in which pixels in the row can be activated (turned ON), while the following white boxes 34 indicate time slots during which they will stay on if activated.
  • Black boxes 36 indicate time slots in which the pixels may be turned OFF (and always are turned OFF), while dotted boxes 38 indicate time slots during which the pixels stay OFF.
  • pixel elements are in the bi-stable region 14 in both the white periods 34 and the dotted periods 38.
  • the sequential ON- and OFF-scans are performed and completed one at a time, resulting in the striped pattern.
  • the time period 38 during which the pixel is idle, the dead time is at least equal to the number of lines minus one.
  • the length of the shortest sub-field (LSB) 40 has to include a number of time slots at least equal to the number of lines, in order to allow completion of the first ON scan before the first OFF scan starts. (It is noted that the length of the sub-field here is defined as the number of white boxes 34 plus 1, as a part of the ON- switching time slots normally contributes to the total light emitted.)
  • Fig. 4 shows the switching curves of a pixel element, and a robust OFF voltage according the present invention.
  • a pixel element may be switched ON by the column data voltages when the row electrode voltage is V row>se ⁇ oN, while the pixel element will remain in its current state (ON or OFF) when the row electrode voltage is V row ,unsei regardless of the column data voltages.
  • a column electrode voltage V CO I, OFF is applied.
  • all pixels in that column are robustly switched OFF, regardless of the row electrode voltages (V r0 w,seioN or N r0 w ; unsei). If the row voltages are always V r0 w,sei ⁇ or V r0 ,unsei, the V CO I,OFF level needs to be higher than the crossing of the OFF-switching curve 18 and the V row , se ioN-line.
  • the column voltage level at the mentioned crossing is indicated with dashed line 43.
  • the V CO I, O FF level is chosen so that it is between the foil voltage level (V f0 ⁇ ) and the level of the crossing of the ON-switching curve 16 and the OFF-switching curve 18.
  • the column voltage level at the ON-switching/OFF- switching curves crossing is indicated with dashed line 45.
  • the voltage V COI , OFF is preferably 10- 15V lower than the foil voltage (Vfoii). The voltage V CO I,OFF causes the electrostatic force between the columns and the foil of the display to disappear, and thus the pixels are switched OFF.
  • FIG. 4 there are only four row-column voltage level combinations compared to six combinations in Fig. 1. Also, only one combination (V r ⁇ w,sei ⁇ and V co ⁇ ,sei ⁇ N) 44 is outside the bi-stable region 14, which means that it is possible to use smaller differences between V r0 w,seioN and V r ow,unsei respectively V co ⁇ ,sei ⁇ N and V co ⁇ ,sei ⁇ FF, i.e. lower voltage swings are needed when addressing according to the invention.
  • Figs. 5a and 5b show the addressing scheme in Fig. 3, improved by implementing the method according to the invention.
  • addressing is made in the following way.
  • the addressing sequence for a frame starts with all pixels in the OFF-state.
  • the first row is placed in an ON state 32 by applying a row selection voltage V r ⁇ w,s ec ⁇ N5 i.e. a pixel in the row will emit light if the column voltage is ON (V Co i,seio N ) and not emit light if the column voltage is OFF (V co ⁇ ,sei ⁇ FF).
  • the other rows are initially set at the unselect voltage row,unsei, i.e.
  • FIG. 5a the first ON-scan 46 starts from the top row of the display, and the second, reversed ON-scan 50 starts from the bottom row of the display. After the reversed ON-scan 50 in Fig. 5a is completed, all rows may remain in this state for a predetermined time to allow light to be generated. The predetermined time depends on the weight, i.e. the number of time slots, of the sub- field.
  • the first (starting from the left) ON-scan and reversed ON-scan defines the first sub-field 52, while the second ON-scan and reversed ON-scan with the following light generating period 54 defines the second sub-field 56.
  • the pixels in the first row are able to be in the ON-state for eleven time slots (white boxes 34) during the first ON-scan, plus a part of each time slot where the actual ON-switching takes place (one checked box 32 in the first ON-scan and one in the reversed ON-scan).
  • the pixels in first row are able to emit light for approximately twelve time slots.
  • the pixels are able to emit light for ten time slots (white boxes 34) during the first ON-scan, and for one time slot (white box 34) during the following reversed ON-scan, plus again the contribution of about one time slot from the ON-switching (checked boxes 32), which equals a total of twelve time slots, i.e. same as for the first row, and so on.
  • the ON-scan from the top row of the display to the bottom row is immediately followed by a robust OFF pulse 48, while the ON-scan in reverse order, i.e. from the bottom row of the display to the top row, in the second sub-field is followed by a light generating period 54 before the next robust OFF pulse.
  • the active addressing sequence 46, 50 is the same for all sub- fields, with the only exception that the length of the light generating period 54, i.e. the number of time slots the light generating period lasts, is different depending on the weight of the sub-field.
  • the light generating period 54 may be divided into several parts.
  • the ON-scan 58 in the second sub-field is followed by a first light generating period 60
  • the reversed ON-scan 62 is followed by a second light generating period 64, whereby the fist and second light generating period 60, 64 has the same total number of time slots as the one light generating period 54 in the second sub-field in Fig. 5a.
  • the advantage with a divided light generating period scheme is that it is symmetric, which improves image quality.
  • each "regular" top-to-bottom ON-scan is followed by a reverse bottom-to-top ON-scan, which is followed by another “regular” ON-scan, and so on.
  • all the “regular” ON-scans may be first in the frame, followed by all corresponding reversed ON-scans, as shown in Fig. 5c.
  • the first ON-scan 63 is associated to the first reversed ON-scan 64, which together constitutes a sub-field, while the second ON-scan 66 and the second reversed ON-scan and light generating period 68 constitutes another sub- field, and so on.
  • an additional robust OFF pulse is applied during the ON-scan in addition to the robust OFF pulse after the completion of the ON-scan as discussed above.
  • the additional robust OFF pulse may be applied both during the first top-to-bottom ON-scan, and the second, reversed ON-scan.
  • the additional robust OFF pulse may for example be applied at a time when half of the rows have been placed in the ON state, i.e. in the middle of the ON-scan. After the additional robust OFF pulse, the ON-scan continues in order to place the remaining rows of the display in the ON state. It is preferred that the additional robust OFF pulses are only applied for sub- fields with the lowest weights, i.e.
  • the slot time increases from 0.158 ⁇ s to 0.306 ⁇ s without any significant decrease of efficiency, when using the repeated sub-field addressing scheme with additional robust OFF pulse compared to the standard repeated sub-field addressing scheme.
  • the larger maximum slot time i.e. the row selection or addressing time, makes the display easier to operate.
  • slot times may be further increased by giving additional robust
  • OFF pulses 70 for example three times during each ON-scan in the first sub-field, i.e. at time slots at every V ⁇ of the number of rows, and one time during each ON-scan in the second sub- field, i.e. at time slots at every Vz of the number of rows.
  • Fig. 6b wherein the lowest sub-field 72 have been reduced to three time slots.
  • the order of the sub-periods in Figs. 6a and 6b may be changed, for example resulting in the scheme in Fig. 6c.
  • the rows of the first half of the addressing scheme can be interleaved with the rows of the second half.
  • row one i.e. the first row from the top
  • row two with the sequence of row L/2+1
  • row three with that of row two
  • row four with that of row L/2+2, etc.
  • row L-l is addressed with the sequence drawn for row L/2, and row L with that drawn from row L.
  • the display may comprise several sets of row electrodes forming groups 76 ,77 ,78 , resulting in the addressing schemes shown in Figs. 7a and 7b.
  • the addressing in Fig. 7a starts with an ON-scan, wherein all rows in the group 77 which is to display the sub-field with largest weight are switched ON. Directly following this ON-scan, another ON-scan is performed by the group 76 displaying the second largest sub- field, and so on. After all groups of rows have performed an ON-scan each, there is a robust OFF pulse 80, whereby all rows are placed in the OFF state. After the robust OFF, each row is by groups switched ON in a reverse order compared to the first set of ON-scans. These reversed ON-scans are then again followed by a robust OFF pulse.
  • another group 76 displays the sub-field with largest weight
  • another group 78 displays the sub- field with the second largest weight, and so on.
  • the sub- fields are divided into a plurality of parts, which are displayed at different times by different groups.
  • the number of groups is equal to the number of sub-fields of the frame.
  • sub-fields with weights of increasing order, in this case 1,2,3,4,5,... etcetera. This is achieved by adding extra light emission time slots after the ON-scans, whereby the number of extra light emission time slots should equal the number of row electrodes per group. This is shown in Fig. 7b, wherein after each group of rows has performed an ON-scan, all rows remains in a light enabling state for a certain period of time 82 depending on the sub-field weights before the following robust OFF-pulse.
  • This weighting makes it possible to distribute the addressing time slots, i.e. the time slots where the row selection voltage V row ,secON is applied, optimally over the frame, which enables an increase in the available addressing time. This will be shown by the following calculations.
  • Table 1 shows a comparison of the grouped repeated sub-field addressing scheme, with Figures calculated using the above formulas, and the standard repeated sub- field scheme. Note that the number of sub-fields in the first case has been chosen to result in roughly the same number of grey scales as the binary sub-fields. In table 1, the values have been calculated for a display having 480 lines and at a 60 Hz frame rate.
  • the available addressing time is 0,74 ⁇ s for the grouped repeated subfield addressing scheme with sub-fields having increasing weights. This may be compared to the standard repeated sub-field addressing scheme with binary sub- fields where the corresponding available addressing time is 0.13 ⁇ s. Thus, the available addressing time increases with almost a factor 6 compared to the standard repeated sub-field addressing scheme.
  • the larger maximum slot time, i.e. the row selection or addressing time, makes the display easier to operate.
  • row electrodes and “column electrodes” are used in the description and claims generally to indicate a system of electrodes capable of addressing each pixel independently. This is normally accomplished by two orthogonal sets of parallel electrodes (hence the names), but may equally well be accomplished by two arbitrary sets of electrodes, as long as each pixel is connected to one electrode in each set.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

A method for addressing a display device comprising, during a first period, applying to one row electrode at a time an ON-select voltage (Vrow,selON) such that pixels connected to this row electrode can be switched ON by a data signal applied to the column electrodes, during a second period, applying the ON-select voltage (Vrow,seloN) to one row electrode at a time in reverse order compared to said first period, and in a time slot between said first and second periods, applying to all columns electrodes (28) an OFF voltage (Vcol,OFF) adapted to place all pixels in the OFF state. By applying the second voltage (Vcol,OFF) to all column electrodes (28) in the set, all pixels are switched OFF regardless of the row voltage levels, which makes it possible 10 to provide an addressing scheme which is very robust.

Description

DISPLAY DEVICE ADDRESSING METHOD WITH ALTERNATING ROW SELECTING ORDER AND INTERMEDIATE OFF PULSES
The present invention relates to a method for addressing a display device having a set of row electrodes and a set of column electrodes for addressing a plurality of pixels defined by intersections of said electrodes, wherein, during a first period, an ON-select voltage is applied to one row electrode at a time such that pixels connected to this row electrode can be switched ON by a data signal applied to the column electrodes.
The invention also relates to a display driver for implementing such a method, and a display device comprising such a driver.
0 The switching curves of such a pixel element being addressed by voltages applied on row and column electrodes is shown in Fig. 1, where the x- and y-axis represent the row and column voltages respectively. For a combination of row and column voltages (Vrow,seioN, Vcoi.seiON), the pixel is switched ON 10, and for another combination of row and column voltages (Nrow,seioFF, Vcoi,SeioFF), the pixel is switched OFF 12. However, for a suitable 5 row voltage level (Vr0w,unsei), the state for the pixel cannot be switched (neither ON nor OFF) by changing the column voltage level between Vcoi,SeioN and VCoi,seioFF, but maintains its present state. This bi-stable region 14, between the ON-curve 16 and the OFF-curve 18, creates a memory effect in the pixel element. This memory effect makes it possible to use a passive matrix addressing method to drive the display. 0 Thus, there is three different row voltages (Vrow,seiθN5 Nrow,seioFF and Vr0w,unsei) and two different column voltages (Vcoι,seiθΝ> Vcoι,seiθFF,), which means that there are six different row-column voltage combinations. The combinations are shown in Fig. 1.
Conventionally, addressing is performed in the following way. The addressing sequence for a frame starts with all pixels in the OFF-state. Then, all but one row is put at the 5 unselect voltage (Vr0w,unsei) and remains in its current state (hence OFF) when the data voltages (Vcoι,seiθN or VCoi,seioFF) are applied on the column voltage. One row is put at the ON- select voltage (Vrow,seiθN)- At this voltage, a pixel will switch ON and emit light when the column voltage is at VcoιjSeiθN5 while it will remain in its current position (hence OFF) when the column voltage is Vcoι,seiθFF. The rows are addressed sequentially during a first scan, to allow switching all pixels ON, and then a second sequential scan is performed during which the selective row voltage is Vrow,seiθFF, and all column voltages are put to Vcoι,seiθFF, i-e. all pixels are finally switched to the OFF state. The frame period is divided into several pairs of such ON- and OFF -scans, each such pair being referred to as a sub-field. Grey scales can be accomplished by switching a pixel ON during appropriate sub- fields, which sub-fields preferably are weighted, for example in a binary fashion (binary weighted sub-fields, BWS). The weight of a sub-field depends on the number of time slots of the frame it occupies. The sub- fields are organized in an addressing scheme, which describes in what order the rows are being addressed with ON and OFF addressing actions.
However, in some types of displays, there is a problem with spread in the ON- curve and OFF-curve referred to in Fig. 1. The spread in the switching curves is caused by physical differences in the display. The spread makes it difficult to place the ON-switching point, i.e. select the ON-switching voltages (Vrow,seioN> Vcoι,seiθN), and the OFF-switching point (Nrow,seioFF, Vcoi,seioFF) so that they for sure are outside the bi-stable region. If for example an OFF-switching point because of spread in the switching curves falls within the bi-stable region, the pixel will not be switched OFF properly.
An object of the present invention is to provide an addressing scheme which is improved compared with known addressing schemes.
A particular object is to provide an addressing scheme with improved switching. These and other objects are achieved by a method of the kind mentioned by way of introduction, further comprising during a second period, applying the OΝ-select voltage to one row electrode at a time in reverse order compared to said first period, and in a time slot between said first and second periods, applying to all columns electrodes an OFF voltage adapted to place all pixels in the set in the OFF state. It should be noted that the "set" of the electrodes not necessarily includes all electrodes of the display. On the contrary, the electrodes of the display may advantageously be divided into several sets, in order to provide a more efficient addressing.
The invention is based on the understanding that it is easier to switch OFF a complete column of the display compared to switching OFF a particular pixel in that column. A complete column may be switched OFF by applying to all column electrodes a robust voltage level so that all the pixels are placed in the OFF state regardless of the row voltage levels. By applying this OFF pulse the whole display is erased, and it is possible to provide an addressing scheme which is very robust. One advantage with applying the robust OFF pulse is that the row voltage level previously used to switch pixels OFF no longer is necessary, which facilitates the operation of the display. It also means that only one row-column voltage combination is outside the bi-stable region, which enables lower voltage swings compared to Fig. 1, i.e. lower voltage differences between the row voltages respectively the column voltages are needed in order to make sure that the ON-switching row-column voltage combination is outside the bi-stable region. Another advantage with the robust OFF pulse is that since it is applied to the whole column, the IC circuit that was previously used to switch pixels both ON and OFF now only is involved in the ON switching of the pixels.
As mentioned above, the ON-scan is repeated in reverse order after the robust OFF-switch, which results in that all rows are able to be in the ON state for the same amount of time. In addition, the repeated ON-scan can also enable flicker reduction.
The method according to the invention can be implemented in an addressing scheme of the type where a frame period is divided into a plurality of sub-fields, and the first and second periods can then together form a sub-field. The method according to the invention provides more freedom in choosing sub-field weight and order of the sub-fields, and thus removes some of the restrictions present in previous addressing schemes.
In one embodiment of the invention, the display device comprises several sets of row electrodes, whereby the above mentioned steps of applying the first and second voltage levels are preformed for each set in such a way that during the addressing frame, the sub-fields appear in a different order for each set. Thus, at a certain time during the addressing, each row electrode set displays information from a different sub-field.
One advantage with this addressing scheme is that the addressing steps, i.e. the steps in which a row for example is switched ON, may be distributed more efficiently over the frame, whereby the available row selection time is increased. In this addressing scheme, the sub-fields preferably have weights of an increasing order of 1, 2, 3, 4, 5, etcetera. This enables that the addressing time slots may be distributed optimally over the frame in order to increase the available addressing time. Another advantage with this weighting compared to binary weighted sub-fields is that there are several ways to display one grey level (for example grey level 4 may be displayed as sub- field 4 or sub-field 1+3). By using many active sub-fields to display a grey scale (i.e. using for example sub-fields 1+3+4 to display grey level 8 instead of using sub-field 8 only), motion artefacts may be reduced. On the other hand, regarding uniformity, it is most beneficial to use the least number of active sub-fields (i.e. using sub-field 8 only to display grey level 8 instead of using for example sub-fields 1+3+4 or 1+2+5).
The row electrodes are preferably addressed one at a time in a successive order, from one end of the row electrode set to the opposite end of the set. In the case with one set, the ON-scan may start by addressing the row electrode at the top of the display, continue with each consecutive, adjacent row electrode in a direction downwards, and finish by addressing the row electrode at the bottom of the display. In the case with several row electrode sets, the addressing in each set may start by addressing of the row electrode at the top of the set, continue with each consecutive, adjacent row electrode in a direction downwards, and finish by addressing the row electrode at the bottom of the set.
In another embodiment of the invention, the OFF voltage is applied to all columns electrodes in the set in a time slot during said first period and a time slot during said second period. This additional robust OFF pulse during the first and second periods divides the ON-scan into sub-periods, enabling a reduction of the weight of the lowest sub-field. This in turn, allows reduction of the number of time slots, and hence an increased available row selection time. A longer row selection time makes the display easier to operate. The first and second periods may each be divided into for example two or four sub-periods. When dividing each period into two sub-periods, the additional robust OFF pulse is consequently applied once during the first period, and once during the second period. The additional robust OFF pulse may for example be applied in a time slot when half of the rows of the display has been placed in the ON enabling state, i.e. halfway through the ON- scan. After the additional robust OFF pulse, the ON-scan continue in order to place the remaining rows of the display in the ON state.
Preferably, the additional robust OFF pulse may be applied only for the sub- fields with the lowest weights, i.e. sub-fields that are smaller than the number of rows of the display (L). This addressing scheme is more time-efficient. The method according to the invention can be advantageously implemented in a dynamic foil display. Currently preferred embodiments of the invention will now be further described in reference to the accompanying drawings wherein:
Fig. 1 illustrates the switching curves of a pixel element having a bi-stable region. Fig. 2 is a side view of a dynamic foil display.
Fig. 3 illustrates a conventional addressing scheme for a display having bistable pixel elements.
Fig. 4 illustrates the switching curves of a pixel element having a bi-stable region, and robust OFF. Figs. 5a-5d show four addressing schemes according to one embodiment of the invention.
Figs. 6a-6c show three addressing schemes according to another embodiment of the invention comprising additional robust OFF pulses.
Figs. 7a-7b show two addressing schemes according to a further embodiment of the invention, wherein the set rows electrodes are divided into sub-sets of row electrodes.
In the following, the method according to the invention will be described in relation to a dynamic foil display, described in e.g. WOOO/38163. With reference to Fig. 2, such a display comprises a light guide 20 in the form of an edge lit glass plate and a non- lit back plate 22, with a scattering foil 24 clamped in between. Light from a light source 26 is coupled into the light guide 20. On both plates there are respective sets of parallel electrodes which are arranged perpendicularly with respect to each other. The electrodes on the light guide are referred to as column electrodes 28, while the electrodes in the back plate are row electrodes 30. The voltages applied to the electrodes are controlled by a row driver and a column driver.
Conventionally, the dynamic foil display is addressed in the way which was described above, with reference to Fig. 1. An example of an addressing scheme is illustrated in Fig. 3. In this Figure (and in the following Figures 5a-5d and 6a-6c), checked boxes 32 indicate time slots in which pixels in the row can be activated (turned ON), while the following white boxes 34 indicate time slots during which they will stay on if activated. Black boxes 36 indicate time slots in which the pixels may be turned OFF (and always are turned OFF), while dotted boxes 38 indicate time slots during which the pixels stay OFF. With reference to Fig. 1, pixel elements are in the bi-stable region 14 in both the white periods 34 and the dotted periods 38.
In Fig. 3, the sequential ON- and OFF-scans are performed and completed one at a time, resulting in the striped pattern. After each pixel has been switched OFF during an OFF-scan the time period 38 during which the pixel is idle, the dead time, is at least equal to the number of lines minus one. Further, the length of the shortest sub-field (LSB) 40 has to include a number of time slots at least equal to the number of lines, in order to allow completion of the first ON scan before the first OFF scan starts. (It is noted that the length of the sub-field here is defined as the number of white boxes 34 plus 1, as a part of the ON- switching time slots normally contributes to the total light emitted.)
Fig. 4 shows the switching curves of a pixel element, and a robust OFF voltage according the present invention. As in Fig. 1, a pixel element may be switched ON by the column data voltages when the row electrode voltage is Vrow>seιoN, while the pixel element will remain in its current state (ON or OFF) when the row electrode voltage is Vrow,unsei regardless of the column data voltages.
In order to turn a pixel OFF, a column electrode voltage VCOI,OFF according to the invention is applied. When provided with this voltage, all pixels in that column are robustly switched OFF, regardless of the row electrode voltages (Vr0w,seioN or Nr0w;unsei). If the row voltages are always Vr0w,seiθΝ or Vr0 ,unsei, the VCOI,OFF level needs to be higher than the crossing of the OFF-switching curve 18 and the Vrow,seioN-line. The column voltage level at the mentioned crossing is indicated with dashed line 43. However, because of possible spread in the OFF-switching curve 18, it is preferred that the VCOI,OFF level is chosen so that it is between the foil voltage level (Vf0ϋ) and the level of the crossing of the ON-switching curve 16 and the OFF-switching curve 18. The column voltage level at the ON-switching/OFF- switching curves crossing is indicated with dashed line 45. In the described embodiment, the voltage VCOI,OFF is preferably 10- 15V lower than the foil voltage (Vfoii). The voltage VCOI,OFF causes the electrostatic force between the columns and the foil of the display to disappear, and thus the pixels are switched OFF.
As seen in Fig. 4, there are only four row-column voltage level combinations compared to six combinations in Fig. 1. Also, only one combination (Vrθw,seiθΝ and Vcoι,seiθN) 44 is outside the bi-stable region 14, which means that it is possible to use smaller differences between Vr0w,seioN and Vrow,unsei respectively Vcoι,seiθN and Vcoι,seiθFF, i.e. lower voltage swings are needed when addressing according to the invention. Figs. 5a and 5b show the addressing scheme in Fig. 3, improved by implementing the method according to the invention. In this "repeated" sub-field addressing scheme, addressing is made in the following way. The addressing sequence for a frame starts with all pixels in the OFF-state. Then, as in the conventional method described above, the first row is placed in an ON state 32 by applying a row selection voltage Vrθw,secθN5 i.e. a pixel in the row will emit light if the column voltage is ON (VCoi,seioN) and not emit light if the column voltage is OFF (Vcoι,seiθFF). The other rows are initially set at the unselect voltage row,unsei, i.e. they will remain in their current state (hence OFF) when data voltages, Vcoi,seioN or Vcoi.seiOFF, are applied to the column electrodes. After the first row has been switched ON, the following rows are then successively placed in the ON state one row at a time in a scanning phase 46.
After the ON-scan 46, all pixels of the display are in one time slot simultaneously erased, i.e. placed in the OFF state, by applying a robust OFF pulse (indicated with an arrow 48) according to the invention. Robust OFF means as mentioned earlier that the pixels are placed in the OFF state regardless of the row electrode voltages. This is achieved by setting all the column electrodes to VCOI,OFF.
Following the robust OFF pulse, another ON-scan 50 is carried out in reverse order compared to the first ON-scan. In Fig. 5a, the first ON-scan 46 starts from the top row of the display, and the second, reversed ON-scan 50 starts from the bottom row of the display. After the reversed ON-scan 50 in Fig. 5a is completed, all rows may remain in this state for a predetermined time to allow light to be generated. The predetermined time depends on the weight, i.e. the number of time slots, of the sub- field. In Fig. 5a, the first (starting from the left) ON-scan and reversed ON-scan defines the first sub-field 52, while the second ON-scan and reversed ON-scan with the following light generating period 54 defines the second sub-field 56.
By performing the reversed ON-scan, all rows have been able to be in the ON state for the same amount of time, i.e. the number of time slots that the pixels in each row are able to emit light are the same for each sub-field. For example in the first sub-field in Fig. 5a, the pixels in the first row are able to be in the ON-state for eleven time slots (white boxes 34) during the first ON-scan, plus a part of each time slot where the actual ON-switching takes place (one checked box 32 in the first ON-scan and one in the reversed ON-scan). In total, the pixels in first row are able to emit light for approximately twelve time slots. For the second row, the pixels are able to emit light for ten time slots (white boxes 34) during the first ON-scan, and for one time slot (white box 34) during the following reversed ON-scan, plus again the contribution of about one time slot from the ON-switching (checked boxes 32), which equals a total of twelve time slots, i.e. same as for the first row, and so on.
In Fig. 5a, the ON-scan from the top row of the display to the bottom row is immediately followed by a robust OFF pulse 48, while the ON-scan in reverse order, i.e. from the bottom row of the display to the top row, in the second sub-field is followed by a light generating period 54 before the next robust OFF pulse. By having the whole light generating period after the reversed ON-scan, the active addressing sequence 46, 50 is the same for all sub- fields, with the only exception that the length of the light generating period 54, i.e. the number of time slots the light generating period lasts, is different depending on the weight of the sub-field.
However, the light generating period 54 may be divided into several parts. With reference to Fig. 5b, the ON-scan 58 in the second sub-field is followed by a first light generating period 60, and the reversed ON-scan 62 is followed by a second light generating period 64, whereby the fist and second light generating period 60, 64 has the same total number of time slots as the one light generating period 54 in the second sub-field in Fig. 5a. The advantage with a divided light generating period scheme is that it is symmetric, which improves image quality.
Again referring to Fig. 5a, each "regular" top-to-bottom ON-scan is followed by a reverse bottom-to-top ON-scan, which is followed by another "regular" ON-scan, and so on. In an alternative addressing scheme, all the "regular" ON-scans may be first in the frame, followed by all corresponding reversed ON-scans, as shown in Fig. 5c. In this addressing scheme, the first ON-scan 63 is associated to the first reversed ON-scan 64, which together constitutes a sub-field, while the second ON-scan 66 and the second reversed ON-scan and light generating period 68 constitutes another sub- field, and so on. When starting with all "regular" ON-scans, it is preferred to use divided light generating periods as discussed above, resulting in the addressing scheme exemplified in Fig. 5d. This addressing scheme shows a symmetry of the first and the second half of the frame, and it enables flicker reduction.
In another embodiment of the invention, an additional robust OFF pulse is applied during the ON-scan in addition to the robust OFF pulse after the completion of the ON-scan as discussed above. The additional robust OFF pulse may be applied both during the first top-to-bottom ON-scan, and the second, reversed ON-scan. The additional robust OFF pulse may for example be applied at a time when half of the rows have been placed in the ON state, i.e. in the middle of the ON-scan. After the additional robust OFF pulse, the ON-scan continues in order to place the remaining rows of the display in the ON state. It is preferred that the additional robust OFF pulses are only applied for sub- fields with the lowest weights, i.e. when the sub-field is smaller than the number of lines of the display (L). This is the most time-efficient method. As shown in Fig. 6a, by applying additional robust OFF pulses indicated with the arrow 70 during the ON-scan, the weight of the lowest sub-field is reduced (from 12 time slots in Fig. 5a, to 6 time slots in Fig. 6a). This makes it possible to reduce the number of required time slots, and hence increase the time available for row selection or addressing compared to the standard repeated sub-field addressing scheme. This will be shown by the following calculations.
For the standard repeated sub- field addressing scheme with binary sub-fields with the lowest weight of L (Fig. 5a), the total number of required time slots Ntot(RS) = NSF*(2*L+2)+L*(2NSF-l-NSF), and the number of slots in which light is generated Nlight(RS) = L*(2NSF-1), wherein NSF is the number of sub-fields and L is the number of lines. For a VGA display with 480 lines and 8 binary sub- fields, the standard repeated sub- field addressing scheme has a total number of slots Ntot(RS) = 126256 of which a number of Nlight(RS) = 122400 is used to make light. At a 50 Hz frame rate, this results in a slot time of 20 ms / 126256 = 0.158 μs and an efficiency of 122400 / 126256 = 96.9 %.
For the repeated sub-field addressing scheme with additional robust OFF action with LSB=L/2 (Fig. 6a), the total number of required time slots Ntot(RS-half) = (2L+4) + (NSF-l)*(2*L+2)+L*(2(NSF"1)-l-(NSF-l)) = 2 + NSF*(2*L+2)+L*(2(NSF-1)-NSF), and the number of slots in which light is generated Nlight(RS-half) = L*(2NSF- 1)/2. For a VGA display with 480 lines and 8 binary sub-fields, the standard repeated sub-field addressing scheme has a total number of slots Ntot(RS) = 65298 of which a number of Nlight(RS) = 61200 is used to make light. At a 50 Hz frame rate, this results in a slot time of 20 ms / 65298 = 0.306 μs and an efficiency of 93.7 %. In the above examples, the slot time increases from 0.158 μs to 0.306 μs without any significant decrease of efficiency, when using the repeated sub-field addressing scheme with additional robust OFF pulse compared to the standard repeated sub-field addressing scheme. The larger maximum slot time, i.e. the row selection or addressing time, makes the display easier to operate. Alternatively, slot times may be further increased by giving additional robust
OFF pulses 70 for example three times during each ON-scan in the first sub-field, i.e. at time slots at every VΛ of the number of rows, and one time during each ON-scan in the second sub- field, i.e. at time slots at every Vz of the number of rows. This is shown in Fig. 6b, wherein the lowest sub-field 72 have been reduced to three time slots. Naturally, the order of the sub-periods in Figs. 6a and 6b may be changed, for example resulting in the scheme in Fig. 6c.
Also, the order in which the rows are addressed in an addressing scheme according to the invention may be changed. For example, the rows of the first half of the addressing scheme can be interleaved with the rows of the second half. Starting from an addressing scheme as illustrated in Fig. 5a with L rows, this would mean that row one (i.e. the first row from the top) is addressed with the sequence of the first row; row two with the sequence of row L/2+1; row three with that of row two; row four with that of row L/2+2, etc. Finally, row L-l is addressed with the sequence drawn for row L/2, and row L with that drawn from row L.
In a further embodiment of the invention, the display may comprise several sets of row electrodes forming groups 76 ,77 ,78 , resulting in the addressing schemes shown in Figs. 7a and 7b.
The addressing in Fig. 7a starts with an ON-scan, wherein all rows in the group 77 which is to display the sub-field with largest weight are switched ON. Directly following this ON-scan, another ON-scan is performed by the group 76 displaying the second largest sub- field, and so on. After all groups of rows have performed an ON-scan each, there is a robust OFF pulse 80, whereby all rows are placed in the OFF state. After the robust OFF, each row is by groups switched ON in a reverse order compared to the first set of ON-scans. These reversed ON-scans are then again followed by a robust OFF pulse.
For the next set of ON-scans and corresponding reversed ON-scans, another group 76 displays the sub-field with largest weight, and another group 78 displays the sub- field with the second largest weight, and so on. Thus, when running this grouped repeated sub- field addressing scheme, the sub- fields are divided into a plurality of parts, which are displayed at different times by different groups. The number of groups is equal to the number of sub-fields of the frame.
When using grouped row electrodes, it is preferred to use sub-fields with weights of increasing order, in this case 1,2,3,4,5,... etcetera. This is achieved by adding extra light emission time slots after the ON-scans, whereby the number of extra light emission time slots should equal the number of row electrodes per group. This is shown in Fig. 7b, wherein after each group of rows has performed an ON-scan, all rows remains in a light enabling state for a certain period of time 82 depending on the sub-field weights before the following robust OFF-pulse. This weighting makes it possible to distribute the addressing time slots, i.e. the time slots where the row selection voltage Vrow,secON is applied, optimally over the frame, which enables an increase in the available addressing time. This will be shown by the following calculations.
The total number of required time slots, i.e. addressing steps, for this addressing scheme is Ntot(grouped) = NSF*(L+NSF+l+L+NSF+roundup(L/NSF)+l) = NSF*(2L+2NSF+2+roundup(L/NSF)), and the number of slots in which light is generated Nlight(grouped)=(NSF2+NSF)*(roundup(L/NSF)+l). Also, the number of grey levels (G) which is to be displayed equals G = (NSF2+NSF)/2.
Table 1 shows a comparison of the grouped repeated sub-field addressing scheme, with Figures calculated using the above formulas, and the standard repeated sub- field scheme. Note that the number of sub-fields in the first case has been chosen to result in roughly the same number of grey scales as the binary sub-fields. In table 1, the values have been calculated for a display having 480 lines and at a 60 Hz frame rate.
Table 1.
As seen from the results in table 1, for 8 bits (in this case 22 sub-fields which equals 254 grey scales), the available addressing time is 0,74 μs for the grouped repeated subfield addressing scheme with sub-fields having increasing weights. This may be compared to the standard repeated sub-field addressing scheme with binary sub- fields where the corresponding available addressing time is 0.13 μs. Thus, the available addressing time increases with almost a factor 6 compared to the standard repeated sub-field addressing scheme. The larger maximum slot time, i.e. the row selection or addressing time, makes the display easier to operate.
The invention is not limited to the embodiments described above. Those skilled in the art will recognize that variations and modifications can be made without departing from the scope of the invention as claimed in the accompanying claims.
For example, it should be noted that the terms "row electrodes" and "column electrodes" are used in the description and claims generally to indicate a system of electrodes capable of addressing each pixel independently. This is normally accomplished by two orthogonal sets of parallel electrodes (hence the names), but may equally well be accomplished by two arbitrary sets of electrodes, as long as each pixel is connected to one electrode in each set.

Claims

CLAIMS:
1. A method for addressing a display device having a set of row electrodes (30) and a set of column electrodes (28) for addressing a plurality of pixels defined by intersections of said electrodes, comprising: during a first period, applying to one row electrode at a time an ON-select voltage (Vrow,seioN) such that pixels connected to this row electrode can be switched ON by a data signal applied to the column electrodes, characterized in during a second period, applying said ON-select voltage (Vr0w,seioN) to one row electrode at a time in reverse order compared to said first period, and in a time slot between said first and second periods, applying to all columns electrodes (28) in the set an OFF voltage (VCOI,OFF) adapted to place said pixels in the OFF state.
2. A method according to claim 1, implemented in an addressing scheme of the type where a frame period is divided into a plurality of sub-fields (52, 56), wherein said first and second periods together form a sub- field.
3. A method according to claim 2, wherein said display device comprises several sets of row electrodes (76, 77, 78), and wherein the steps of applying said first and second voltage levels are performed for each set in such a way that said plurality of sub-fields appear in a different order for each set.
4. A method according to claim 3, wherein said sub-fields are weighted in increasing order of 1, 2, 3, ..., n.
5. A method according to any one of the claims 1-4, wherein during said first and second periods, said ON-select voltage (Vrow,seioN) is applied to one row electrode at a time in a successive order, form one end of the set to the opposite end of the set.
6. A method according to any one of claims 1-5, further comprising: in a time slot during said first period and a time slot during said second period, applying to all columns electrodes (28) in the set said OFF voltage (VCOI,OFF).
7. A method according to any one of the preceding claims, wherein said display device comprises a light guide (20) and a flexible element (24), and wherein said row and column electrodes (30, 28) are arranged to bring selected portions of the flexible element (24) into contact with the light guide (20) in order to extract light from the light guide 20.
8. A display driver intended for use in a display device having a set of row electrodes (8) and a set of column electrodes (9) for addressing a plurality of pixels defined by intersections of said electrodes, said driver comprising: means for applying, during a first period, to one row electrode at a time an ON-select voltage (Vro ,seioN) such that pixels connected to this row electrode can be switched ON by a data signal applied to the column electrodes, means for applying, during a second period, said ON-select voltage (Vro ,seioN) to one row electrode at a time in reverse order compared to said first period, and means for applying, in a time slot between said first and second periods, to all columns electrodes (28) in the set an OFF voltage (VCOI,OFF) adapted to place said pixels in the OFF state.
9. A display device driver according to claim 8, wherein said means for applying said ON-select voltage (VroWjSeioN) is arranged to apply the voltage to one row electrode at a time in a successive order, from one end of the set to the opposite end of the set.
10. A display driver according to claim 8 or 9, further comprising means for applying, in a time slot during said first period and a time slot during said second period, to all columns electrodes (28) in the set said OFF voltage (VCOI,OFF).
11. A display device comprising a display driver according to one of claims 8-10.
12. A display device according to claim 11, further comprising a light guide (20) and a flexible element (24), and wherein said row and column electrodes (30, 28) are arranged to bring selected portions of the flexible element (24) into contact with the light guide (20) in order to extract light from the light guide (20).
EP04736246A 2003-06-10 2004-06-07 Display device addressing method with alternating row selecting order and intermediate off pulses Withdrawn EP1636781A1 (en)

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