EP1617311B1 - IC with modulated regulator with low voltage drop - Google Patents

IC with modulated regulator with low voltage drop Download PDF

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Publication number
EP1617311B1
EP1617311B1 EP05291508A EP05291508A EP1617311B1 EP 1617311 B1 EP1617311 B1 EP 1617311B1 EP 05291508 A EP05291508 A EP 05291508A EP 05291508 A EP05291508 A EP 05291508A EP 1617311 B1 EP1617311 B1 EP 1617311B1
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Prior art keywords
auxiliary
power
output
main
transistor
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German (de)
French (fr)
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EP1617311A1 (en
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Alexandre Pons
Fabienne Grigis
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the invention relates to low voltage drop regulators ("LDO”) and more particularly to the realization of the power stage of such a regulator.
  • LDO low voltage drop regulators
  • a voltage regulator uses a reference current source and a supply voltage (battery) to provide a regulated output voltage i.e. independent of variations in the supply voltage.
  • the low-voltage drop regulators can be connected to a decoupling capacitor arranged parallel to a load, to which the regulator provides a charging current, via a power transistor, looped back on an operational amplifier.
  • the maximum value of the charging current depends on the dimensions of the power transistor. For the sake of optimization, it is necessary to adapt these dimensions to the load current.
  • the power transistor having a high parasitic capacitance the output stage of the operational amplifier must be adapted to the power transistor, and therefore to the maximum load current.
  • a modification of the value of the maximum charging current involves the change of the power transistor and the adaptation of the heart of the regulator comprising the operational amplifier. This technique represents a strong time constraint in the design of the integrated circuit.
  • the invention aims to provide a solution to this problem.
  • An object of the invention is to modulate the load current delivered by the low voltage drop regulator without modifying the topology of the integrated circuit.
  • Another object of the invention is to use a topologically programmable power stage (programmable by "layout”) as a function of a load current, and a core comprising an operational amplifier, identical whatever the programmed load current .
  • Another object of the invention is to obtain constant performance regardless of the programmed load current.
  • the output stage of the regulator will no longer consist of a single large power MOS transistor but a fixed power portion and one or more power modules assembled, the number of modules depending on the desired maximum output current.
  • the invention thus proposes an integrated circuit comprising a low-voltage drop regulator, said regulator comprising an operational amplifier and a power stage looped back onto the operational amplifier, and capable of delivering an output current into a load.
  • the output stage of the amplifier comprises a main output and n auxiliary outputs adapted to respectively supply a main control voltage and n auxiliary control voltages.
  • the power stage comprises a main power transistor, controlled on its gate by the main control voltage, and p topologically identical power modules with p less than or equal to n, respectively comprising p auxiliary power transistors respectively controlled on their grid by p auxiliary control voltages.
  • the number p is chosen according to a desired maximum output current.
  • the invention uses a programmable power stage at the level of the topology of the integrated circuit, by the use of several power modules, each power module comprising an auxiliary power transistor. These power modules are activated according to the desired value of the charging current delivered by the voltage regulator with low voltage drop.
  • This integrated circuit has the advantage of being able to modulate the value of the load current delivered by the regulator from a single fixed power portion.
  • the output stage comprises a main output transistor and n identical output auxiliary transistors.
  • a main internal impedance is connected between the supply voltage and the main output transistor, and n identical auxiliary internal impedances, belonging to the power stage, are respectively connected between the supply voltage and the n transistors. Auxiliary output.
  • the topology of the integrated circuit comprises a first part incorporating the operational amplifier and its output stage with the exception of the n identical auxiliary internal impedances, and a second part formed of a first invariant sub-part comprising the transistor of main power, and a second modular sub-part comprising p topologically identical power modules, each power module also topologically incorporating the auxiliary internal impedance intended to be connected to the output auxiliary transistor adapted to deliver the control voltage to the auxiliary power transistor contained in this power module.
  • auxiliary internal impedances makes it possible to fix the impedance on the gates of the power transistors, which are mutually unconnected, that is to say non-interconnected. In this way, characteristics of the regulator, such as the polarization range, and its performance no longer depend on the number p of power modules.
  • the dimensions of the main transistor of the output stage are smaller than the dimensions of the n auxiliary output transistors may be smaller or the same, and the dimensions of the main power transistor are smaller than the dimensions of the p power transistors. auxiliary.
  • FIG. 1 shows an integrated circuit CI according to the invention.
  • the LDO reference represents a low voltage drop regulator. It comprises an operational amplifier AMP receiving a reference voltage V REF on the positive input. AMP amplifier is powered by a supply voltage Vdd_LDO, and consumes current Iq.
  • the LDO regulator also includes a power stage EtP connected to the output of the operational amplifier AMP.
  • the power stage EtP is powered by the supply voltage Vdd_LDO, and delivers an output voltage Vout.
  • the output of the power stage EtP is looped back to the negative input of the operational amplifier AMP and connected to a load R L.
  • the load R L receives a charge current Io, equal to the current consumed by the power stage EtP.
  • the output of the power stage EtP is also connected to a decoupling capacitor C L , connected in parallel with the load R L '
  • the capacitor C L generally has a fairly large capacitance, for example 4.7 ⁇ F. Its function is to stabilize the regulator with low LDO voltage drop.
  • the operational amplifier AMP of the LDO regulator here comprises an input stage EtE and an output stage EtS.
  • the input stage EtE is conventionally produced by a differential pair polarized by a current source I and connected to a current mirror.
  • the differential pair comprises two transistors, M1 and M2 connected by their source, for example PMOS transistors.
  • the current source I is also connected to the common source of the differential pair.
  • the current mirror is formed by two transistors M3 and M4 connected by their gate, for example NMOS transistors.
  • the common gate of the current mirror is looped back to the source of the transistor M3.
  • the sources of Transistors M3 and M4 are respectively connected to the drains of transistors M1 and M2 of the differential pair.
  • the gate of the transistor M1 corresponds to the positive input of the amplifier AMP and thus receives the reference voltage Vref.
  • the gate of the transistor M2 corresponds to the negative input of the amplifier AMP and receives a voltage Vout proportional to the output voltage Vout of the power stage EtP.
  • the voltage at Vout is obtained proportional to the output voltage of the power stage EtP, for example by means of a divider bridge (not shown), known to those skilled in the art.
  • the drain of the transistor M2 (output of the input stage EtP) is connected to the output stage EtS of the amplifier AMP.
  • the output stage EtS of the amplifier AMP comprises a main output transistor MosPrinc, connected between the supply voltage Vdd_LDO and the ground.
  • the output stage further comprises n auxiliary output transistors Mos1,..., Mosn connected in parallel with the main output transistor MosPrinc between the supply voltage Vdd_LDO and the ground of the integrated circuit CI.
  • the gates of the main output transistor MosPrinc and the auxiliary output transistors Mos1,..., Mosn are connected together on the output of the input stage EtE.
  • a main internal impedance Zprinc is connected between the supply voltage Vdd_LDO and the drain of the main output transistor MosPrinc.
  • n + 1 outputs of the operational amplifier AMP The drains of the main MosPrinc and auxiliary output transistors Mos1,..., Mosn constitute n + 1 outputs of the operational amplifier AMP. These n + 1 outputs are in this example all connected to the power stage EtP, and respectively deliver a main control voltage V GPRINC and n auxiliary control voltages V G1 , ..., V Gn .
  • the power stage EtP comprises a main power transistor PMosPrinc connected between the supply voltage Vdd_LDO and the gate of the transistor M2 of the input stage EtE of the operational amplifier AMP.
  • the PMosPrinc main power transistor delivers an Iprinc current.
  • the power stage EtP further comprises p auxiliary power transistors PMos1, ..., PMosn.
  • the identical auxiliary power transistors PMos1, ... PMosn each deliver a current of the same value Iunit1, ..., Initn.
  • the gates of the main power transistor PMosPrinc and the p power transistors PMos1,..., PMosp are connected to the n + 1 outputs of the output stage EtS.
  • the number of auxiliary power transistors p can be at most equal to n.
  • the number p is determined as a function of the maximum value of the desired charging current Io. In this example, p is equal to n.
  • auxiliary internal impedances Zinternel ..., Zinternen
  • the value of the main internal impedance Zprinc is greater than the value of the internal internal impedances Zinterne1, ..., Zinternen.
  • the source voltage of the main output transistor MosPrinc of the output stage EtS is greater than the respective source voltages of the auxiliary output transistors Mos1, ..., Mosn.
  • the source voltage of the main MosPrinc output transistor is ten times greater than the voltages of the respective drains of the auxiliary output transistors Mos1, ..., Mosn.
  • the auxiliary power transistors PMos1, ..., PMosn are connected between the supply voltage Vdd_LDO and the gate of the transistor M2 of the input stage EtE of the AMP operational amplifier.
  • the power transistors are preferably PMOS transistors.
  • the dimensions of the main power transistor PMosPrinc are smaller than the dimensions of the auxiliary power transistors PMos1, ..., PMosn.
  • the dimensions are determined according to the values of currents Iprinc, Iunit1, ..., Iunitn that it is desired to deliver.
  • a PMosPrinc main power transistor delivering a current between 0 and 1mA.
  • the auxiliary power transistors PMos1, ..., PMosn then have dimensions that enable them to deliver a current Iunit1, ..., Iunitn, being between 0 and 19 mA (the current in the auxiliary power transistors PMosi starting at 0 mA).
  • the gate of the PMosPrinc main power transistor is controlled by the main control voltage V GPRINC .
  • auxiliary power transistors PMos1, ..., PMosn are respectively controlled by the n auxiliary control voltages V G1 , ..., V Gn .
  • the transistors Mos1,..., Mosn of the output stage EtS are always conductive, and the control voltages, V GPRINC , V G1 ,..., V Gn, make it possible to make the PMosPrinc main power transistors conductive or not. and auxiliary PMos1, ..., PMosn.
  • the auxiliary power transistors PMos1, ..., PMosn become conductive and each deliver a same current which will increase as a function of the request until wait for the maximum value. In this way, the output current of the LDO regulator can be modulated.
  • each auxiliary power transistor PMos1, ..., PMosn is respectively fixed by the internal impedances Zinternel, ..., Zinternen. In this way, and in combination with the fact that the gates of the power transistors are not interconnected, the number n of auxiliary power transistors is made independent of the performance of the LDO regulator.
  • the pole Fc is identical for each of the grids and independent of n. So we have both the conservation of poles and polarization, whatever n. More precisely, the polarization range is: ⁇ 0 ; ( iunit ⁇ + vt ) / Zinterne ⁇ , and is independent of n.
  • the rejection ratio of the regulator is independent of n, as is the phase margin of the regulator, which makes it possible to obtain an acceptable stability whatever the value of n.
  • the topology of the integrated circuit CI comprises two distinct parts.
  • a first portion INT comprising means for generating the reference voltage Vref as well as the operational amplifier AMP, with the exception of the internal auxiliary impedances Zinternel, ..., Zinternen.
  • a second part EXT comprises two subparts.
  • a first invariant sub-part Pinv comprises means for generating the supply voltage Vdd_LDO, a terminal delivering the output voltage Vout of the power stage EtP of the LDO regulator, as well as the supply voltage for the rail rails. Vdd power supply.
  • the invariant sub-part Pinv further comprises the main power transistor PMosPrinc, which is conductive even when the charging current Io is low.
  • the second part EXT also has a modular subpart Pmod.
  • This sub-part Pmod comprises n identical and distinct power modules, module 1, module 2, module 3, ..., module n.
  • These n power modules comprise the auxiliary power transistors of the power stage EtP of the LDO regulator, as well as the n associated auxiliary internal impedances, Zinternel, ..., Zinternen.
  • power modules module 1, module 2, module 3, ..., module n are connected together by a programming cell CP, contained in the modular sub-part Pmod including the necessary connections (not shown).
  • the use of a modular sub-part makes it possible to vary the charge current value I o delivered by the LDO regulator without modifying the topology of the integrated circuit CI.
  • the integrated circuit CI has a single core regardless of the load current Io delivered, and the module stage is programmable via the n modules. As a result, time is saved in the design and design of the integrated circuit.
  • auxiliary internal impedances in the power modules reduces the silicon area used. This also makes it possible to reduce the consumption of the circuit since the drains of the transistors Mos1,..., Mosn are in the air when the corresponding auxiliary PMOS is not used. Indeed, the outputs of the AMP operational amplifier not connected (in the case where p ⁇ n), are not associated with an auxiliary internal impedance, since these are included in the power modules.

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Description

L'invention concerne les régulateurs à faible chute de tension (« LDO » : « LowDropOut voltage regulator » en langue anglaise) et plus particulièrement la réalisation de l'étage de puissance d'un tel régulateur.The invention relates to low voltage drop regulators ("LDO") and more particularly to the realization of the power stage of such a regulator.

Un régulateur de tension utilise une source de courant de référence et une tension d'alimentation (batterie) pour délivrer une tension de sortie régulée c'est-à-dire indépendante des variations de la tension d'alimentation.A voltage regulator uses a reference current source and a supply voltage (battery) to provide a regulated output voltage i.e. independent of variations in the supply voltage.

Pour des raisons de stabilité, les régulateurs à faible chute de tension peuvent être connectés à un condensateur de découplage disposé parallèlement à une charge, à laquelle le régulateur fournit un courant de charge, par l'intermédiaire d'un transistor de puissance, rebouclé sur un amplificateur opérationnel. La valeur maximale du courant de charge dépend des dimensions du transistor de puissance. Par souci d'optimisation, il est nécessaire d'adapter ces dimensions au courant de charge. En outre, le transistor de puissance ayant une forte capacité parasite, l'étage de sortie de l'amplificateur opérationnel doit être adapté au transistor de puissance, et donc au courant maximal de charge. Ainsi, une modification de la valeur du courant maximal de charge implique le changement du transistor de puissance et l'adaptation du coeur du régulateur comprenant l'amplificateur opérationnel. Cette technique représente une forte contrainte de temps au niveau de la conception du circuit intégré.For reasons of stability, the low-voltage drop regulators can be connected to a decoupling capacitor arranged parallel to a load, to which the regulator provides a charging current, via a power transistor, looped back on an operational amplifier. The maximum value of the charging current depends on the dimensions of the power transistor. For the sake of optimization, it is necessary to adapt these dimensions to the load current. In addition, the power transistor having a high parasitic capacitance, the output stage of the operational amplifier must be adapted to the power transistor, and therefore to the maximum load current. Thus, a modification of the value of the maximum charging current involves the change of the power transistor and the adaptation of the heart of the regulator comprising the operational amplifier. This technique represents a strong time constraint in the design of the integrated circuit.

L'invention vise à apporter une solution à ce problème.The invention aims to provide a solution to this problem.

Un but de l'invention est de moduler le courant de charge délivré par le régulateur à faible chute de tension sans modifier la topologie du circuit intégré.An object of the invention is to modulate the load current delivered by the low voltage drop regulator without modifying the topology of the integrated circuit.

Un autre but de l'invention est d'utiliser un étage de puissance topologiquement programmable (programmable par « layout ») en fonction d'un courant de charge, et un coeur comprenant un amplificateur opérationnel, identique quel que soit le courant de charge programmé.Another object of the invention is to use a topologically programmable power stage (programmable by "layout") as a function of a load current, and a core comprising an operational amplifier, identical whatever the programmed load current .

Un autre but de l'invention est d'obtenir des performances constantes quel que soit le courant de charge programmé.Another object of the invention is to obtain constant performance regardless of the programmed load current.

À cet effet, selon l'invention, l'étage de sortie du régulateur va être constitué non plus d'un seul gros transistor MOS de puissance mais d'une partie de puissance fixe et d'un ou plusieurs modules de puissance assemblés, le nombre de modules étant fonction du courant de sortie maximum souhaité.For this purpose, according to the invention, the output stage of the regulator will no longer consist of a single large power MOS transistor but a fixed power portion and one or more power modules assembled, the number of modules depending on the desired maximum output current.

L'invention propose ainsi un circuit intégré comprenant un régulateur à faible chute de tension, ledit régulateur comprenant un amplificateur opérationnel et un étage de puissance rebouclé sur l'amplificateur opérationnel, et apte à délivrer un courant de sortie dans une charge. Selon une caractéristique générale de l'invention, l'étage de sortie de l'amplificateur comporte une sortie principale et n sorties auxiliaires aptes à délivrer respectivement une tension de commande principale et n tensions de commande auxiliaires. Par ailleurs, l'étage de puissance comporte un transistor de puissance principal, commandé sur sa grille par la tension de commande principale, et p modules de puissance topologiquement identiques avec p inférieur ou égal à n, comportant respectivement p transistors de puissance auxiliaires respectivement commandé sur leur grille par p tensions de commande auxiliaires. Le nombre p est choisi en fonction d'un courant de sortie maximum désiré.The invention thus proposes an integrated circuit comprising a low-voltage drop regulator, said regulator comprising an operational amplifier and a power stage looped back onto the operational amplifier, and capable of delivering an output current into a load. According to a general characteristic of the invention, the output stage of the amplifier comprises a main output and n auxiliary outputs adapted to respectively supply a main control voltage and n auxiliary control voltages. Furthermore, the power stage comprises a main power transistor, controlled on its gate by the main control voltage, and p topologically identical power modules with p less than or equal to n, respectively comprising p auxiliary power transistors respectively controlled on their grid by p auxiliary control voltages. The number p is chosen according to a desired maximum output current.

En d'autres termes, l'invention utilise un étage de puissance programmable au niveau de la topologie du circuit intégré, par l'utilisation de plusieurs modules de puissance, chaque module de puissance comprenant un transistor de puissance auxiliaire. Ces modules de puissance sont activés en fonction de la valeur souhaitée du courant de charge délivré par le régulateur de tension à faible chute de tension.In other words, the invention uses a programmable power stage at the level of the topology of the integrated circuit, by the use of several power modules, each power module comprising an auxiliary power transistor. These power modules are activated according to the desired value of the charging current delivered by the voltage regulator with low voltage drop.

Ce circuit intégré a pour avantage de pouvoir moduler la valeur du courant de charge délivré par le régulateur à partir d'une seule partie de puissance fixe.This integrated circuit has the advantage of being able to modulate the value of the load current delivered by the regulator from a single fixed power portion.

Selon un mode de réalisation, l'étage de sortie comporte un transistor principal de sortie et n transistors auxiliaires de sortie identiques. En outre, une impédance interne principale est connectée entre la tension d'alimentation et le transistor principal de sortie, et n impédances internes auxiliaires identiques, appartenant à l'étage de puissance, sont respectivement connectées entre la tension d'alimentation et les n transistors auxiliaires de sortie. Par ailleurs, la topologie du circuit intégré comporte une première partie incorporant l'amplificateur opérationnel et son étage de sortie à l'exception des n impédances internes auxiliaires identiques, et une deuxième partie formée d'une première sous-partie invariante comprenant le transistor de puissance principal, et d'une seconde sous-partie modulable comprenant p modules de puissance topologiquement identiques, chaque module de puissance incorporant également topologiquement l'impédance interne auxiliaire destinée à être connectée au transistor auxiliaire de sortie apte à délivrer la tension de commande sur le transistor de puissance auxiliaire contenu dans ce module de puissance.According to one embodiment, the output stage comprises a main output transistor and n identical output auxiliary transistors. In addition, a main internal impedance is connected between the supply voltage and the main output transistor, and n identical auxiliary internal impedances, belonging to the power stage, are respectively connected between the supply voltage and the n transistors. Auxiliary output. Moreover, the topology of the integrated circuit comprises a first part incorporating the operational amplifier and its output stage with the exception of the n identical auxiliary internal impedances, and a second part formed of a first invariant sub-part comprising the transistor of main power, and a second modular sub-part comprising p topologically identical power modules, each power module also topologically incorporating the auxiliary internal impedance intended to be connected to the output auxiliary transistor adapted to deliver the control voltage to the auxiliary power transistor contained in this power module.

L'ajout d'impédances internes auxiliaires permet de fixer l'impédance sur les grilles des transistors de puissance, qui sont mutuellement non connectées, c'est-à-dire dire non interconnectées. De cette façon des caractéristiques du régulateur, telles que la gamme de polarisation, et ses performances ne dépendent plus du nombre p de modules de puissance.The addition of auxiliary internal impedances makes it possible to fix the impedance on the gates of the power transistors, which are mutually unconnected, that is to say non-interconnected. In this way, characteristics of the regulator, such as the polarization range, and its performance no longer depend on the number p of power modules.

Selon un mode de réalisation, les dimensions du transistor principal de l'étage de sortie sont inférieures aux dimensions des n transistors auxiliaires de sortie peuvent être inférieures ou identiques, et les dimensions du transistor principal de puissance sont inférieures aux dimensions des p transistors de puissance auxiliaires.According to one embodiment, the dimensions of the main transistor of the output stage are smaller than the dimensions of the n auxiliary output transistors may be smaller or the same, and the dimensions of the main power transistor are smaller than the dimensions of the p power transistors. auxiliary.

D'autres avantages et caractéristiques de l'invention apparaîtront à l'examen de la description détaillée d'un mode de réalisation de l'invention nullement limitatif, et des dessins annexés sur lesquels :

  • la figure 1 représente schématiquement un mode de réalisation d'un circuit intégré selon l'invention,
  • la figure 2 représente schématiquement mais plus en détail certaines parties de la figure 1, selon l'invention,
  • la figure 3 représente schématiquement un exemple d'un circuit intégré selon l'invention.
Other advantages and features of the invention will appear on examining the detailed description of an embodiment of the invention which is in no way limiting, and the appended drawings in which:
  • FIG. 1 diagrammatically represents an embodiment of an integrated circuit according to the invention,
  • FIG. 2 schematically represents, but in more detail, certain parts of FIG. 1, according to the invention,
  • FIG. 3 schematically represents an example of an integrated circuit according to the invention.

Sur la figure 1, on a représenté un circuit intégré CI selon l'invention.FIG. 1 shows an integrated circuit CI according to the invention.

La référence LDO représente un régulateur à faible chute de tension. Il comprend un amplificateur opérationnel AMP recevant une tension de référence VREF sur l'entrée positive. L'amplificateur AMP est alimenté par une tension d'alimentation Vdd_LDO, et consomme un courant Iq.The LDO reference represents a low voltage drop regulator. It comprises an operational amplifier AMP receiving a reference voltage V REF on the positive input. AMP amplifier is powered by a supply voltage Vdd_LDO, and consumes current Iq.

Le régulateur LDO comporte également un étage de puissance EtP, connecté à la sortie de l'amplificateur opérationnel AMP. L'étage de puissance EtP est alimenté par la tension d'alimentation Vdd_LDO, et délivre une tension de sortie Vout. La sortie de l'étage de puissance EtP est rebouclée sur l'entrée négative de l'amplificateur opérationnel AMP et connectée sur une charge RL.The LDO regulator also includes a power stage EtP connected to the output of the operational amplifier AMP. The power stage EtP is powered by the supply voltage Vdd_LDO, and delivers an output voltage Vout. The output of the power stage EtP is looped back to the negative input of the operational amplifier AMP and connected to a load R L.

La charge RL reçoit un courant de charge Io, égal au courant consommé par l'étage de puissance EtP.The load R L receives a charge current Io, equal to the current consumed by the power stage EtP.

La sortie de l'étage de puissance EtP est également reliée à un condensateur de découplage CL, connecté parallèlement à la charge RL' Le condensateur CL a généralement une capacité assez importante, par exemple 4,7 µF. Sa fonction est de stabiliser le régulateur à faible chute de tension LDO.The output of the power stage EtP is also connected to a decoupling capacitor C L , connected in parallel with the load R L ' The capacitor C L generally has a fairly large capacitance, for example 4.7 μF. Its function is to stabilize the regulator with low LDO voltage drop.

On se réfère à présent à la figure 2, qui représente plus précisément le régulateur LDO.Referring now to Figure 2, which more specifically represents the LDO regulator.

L'amplificateur opérationnel AMP du régulateur LDO comprend ici un étage d'entrée EtE et un étage de sortie EtS.The operational amplifier AMP of the LDO regulator here comprises an input stage EtE and an output stage EtS.

L'étage d'entrée EtE est réalisé de façon classique par une paire différentielle polarisée par une source de courant I et connectée sur un miroir de courant. La paire différentielle comprend deux transistors, M1 et M2 reliés par leur source, par exemple des transistors PMOS. La source de courant I est également connectée sur la source commune de la paire différentielle. Le miroir de courant est formé par deux transistors M3 et M4 reliés par leur grille, par exemple des transistors NMOS. La grille commune du miroir de courant est rebouclée sur la source du transistor M3. En outre, les sources des transistors M3 et M4 sont respectivement connectées sur les drains des transistors M1 et M2 de la paire différentielle.The input stage EtE is conventionally produced by a differential pair polarized by a current source I and connected to a current mirror. The differential pair comprises two transistors, M1 and M2 connected by their source, for example PMOS transistors. The current source I is also connected to the common source of the differential pair. The current mirror is formed by two transistors M3 and M4 connected by their gate, for example NMOS transistors. The common gate of the current mirror is looped back to the source of the transistor M3. In addition, the sources of Transistors M3 and M4 are respectively connected to the drains of transistors M1 and M2 of the differential pair.

La grille du transistor M1 correspond à l'entrée positive de l'amplificateur AMP et reçoit donc la tension de référence Vref. La grille du transistor M2 correspond à l'entrée négative de l'amplificateur AMP et reçoit une tension a Vout proportionnelle à la tension de sortie Vout de l'étage de puissance EtP. On obtient la tension a Vout proportionnelle à la tension de sortie de l'étage de puissance EtP, par exemple par l'intermédiaire d'un pont diviseur (non représenté), connu de l'homme de métier.The gate of the transistor M1 corresponds to the positive input of the amplifier AMP and thus receives the reference voltage Vref. The gate of the transistor M2 corresponds to the negative input of the amplifier AMP and receives a voltage Vout proportional to the output voltage Vout of the power stage EtP. The voltage at Vout is obtained proportional to the output voltage of the power stage EtP, for example by means of a divider bridge (not shown), known to those skilled in the art.

Le drain du transistor M2 (sortie de l'étage d'entrée EtP) est connectée sur l'étage de sortie EtS de l'amplificateur AMP.The drain of the transistor M2 (output of the input stage EtP) is connected to the output stage EtS of the amplifier AMP.

L'étage de sortie EtS de l'amplificateur AMP comprend un transistor principal de sortie MosPrinc, connecté entre la tension d'alimentation Vdd_LDO et la masse.The output stage EtS of the amplifier AMP comprises a main output transistor MosPrinc, connected between the supply voltage Vdd_LDO and the ground.

L'étage de sortie comprend en outre n transistors auxiliaires de sortie Mos1, ..., Mosn connectés parallèlement au transistor principal de sortie MosPrinc entre la tension d'alimentation Vdd_LDO et la masse du circuit intégré CI. Les grilles du transistor principal de sortie MosPrinc et des transistors auxiliaires de sortie Mos1, ..., Mosn sont connectées ensemble sur la sortie de l'étage d'entrée EtE.The output stage further comprises n auxiliary output transistors Mos1,..., Mosn connected in parallel with the main output transistor MosPrinc between the supply voltage Vdd_LDO and the ground of the integrated circuit CI. The gates of the main output transistor MosPrinc and the auxiliary output transistors Mos1,..., Mosn are connected together on the output of the input stage EtE.

En outre, une impédance interne principale Zprinc est connectée entre la tension d'alimentation Vdd_LDO et le drain du transistor principal de sortie MosPrinc.In addition, a main internal impedance Zprinc is connected between the supply voltage Vdd_LDO and the drain of the main output transistor MosPrinc.

Les drains des transistors de sortie principal MosPrinc et auxiliaires Mos1, ..., Mosn constituent n+1 sorties de l'amplificateur opérationnel AMP. Ces n+1 sorties sont dans cet exemple toutes connectées à l'étage de puissance EtP, et délivrent respectivement une tension de commande principale VGPRINC et n tensions de commande auxiliaires VG1, ..., VGn.The drains of the main MosPrinc and auxiliary output transistors Mos1,..., Mosn constitute n + 1 outputs of the operational amplifier AMP. These n + 1 outputs are in this example all connected to the power stage EtP, and respectively deliver a main control voltage V GPRINC and n auxiliary control voltages V G1 , ..., V Gn .

L'étage de puissance EtP comprend un transistor de puissance principal PMosPrinc connecté entre la tension d'alimentation Vdd_LDO et la grille du transistor M2 de l'étage d'entrée EtE de l'amplificateur opérationnel AMP. Le transistor de puissance principal PMosPrinc délivre un courant Iprinc.The power stage EtP comprises a main power transistor PMosPrinc connected between the supply voltage Vdd_LDO and the gate of the transistor M2 of the input stage EtE of the operational amplifier AMP. The PMosPrinc main power transistor delivers an Iprinc current.

L'étage de puissance EtP comprend en outre p transistors de puissance auxiliaires PMos1, ..., PMosn. Les transistors de puissance auxiliaires identiques PMos1, ...PMosn délivre chacun un courant de même valeur Iunit1, ..., Initn. Les grilles du transistor de puissance principal PMosPrinc et des p transistors de puissance PMos1, ..., PMosp sont connectées aux n+1 sortie de l'étage de sortie EtS. Le nombre de transistors de puissance auxiliaires p peut être au plus égal à n. Le nombre p est déterminé en fonction de la valeur maximale du courant de charge Io désiré. Dans cet exemple, p est égal à n.The power stage EtP further comprises p auxiliary power transistors PMos1, ..., PMosn. The identical auxiliary power transistors PMos1, ... PMosn each deliver a current of the same value Iunit1, ..., Initn. The gates of the main power transistor PMosPrinc and the p power transistors PMos1,..., PMosp are connected to the n + 1 outputs of the output stage EtS. The number of auxiliary power transistors p can be at most equal to n. The number p is determined as a function of the maximum value of the desired charging current Io. In this example, p is equal to n.

De plus, n impédances internes auxiliaires identiques Zinternel, ..., Zinternen, sont connectées entre la tension d'alimentation Vdd_LDO et les grilles des transistors de puissance auxiliaires de sortie PMos1, ..., PMosn. La valeur de l'impédance interne principale Zprinc est supérieure à la valeur des impédances internes auxiliaires Zinterne1, ..., Zinternen. Ainsi la tension de source du transistor principal de sortie MosPrinc de l'étage de sortie EtS est supérieure aux tensions de sources respectives des transistors auxiliaires de sortie Mos1, ..., Mosn. Par exemple, pour une impédance interne principale Zprinc trois fois supérieures à la valeur d'une impédance interne auxiliaire, la tension de la source du transistor principal de sortie MosPrinc est dix fois supérieure aux tensions des drains respectifs des transistors auxiliaires de sortie Mos1, ..., Mosn.Moreover, n identical auxiliary internal impedances Zinternel, ..., Zinternen, are connected between the supply voltage Vdd_LDO and the gates of the auxiliary auxiliary power transistors PMos1, ..., PMosn. The value of the main internal impedance Zprinc is greater than the value of the internal internal impedances Zinterne1, ..., Zinternen. Thus the source voltage of the main output transistor MosPrinc of the output stage EtS is greater than the respective source voltages of the auxiliary output transistors Mos1, ..., Mosn. For example, for a main internal impedance Zprinc three times greater than the value of an auxiliary internal impedance, the source voltage of the main MosPrinc output transistor is ten times greater than the voltages of the respective drains of the auxiliary output transistors Mos1, ..., Mosn.

De la même façon que pour le transistor de puissance principal PMosPrinc, les transistors de puissance auxiliaires PMos1, ..., PMosn sont connectés entre la tension d'alimentation Vdd_LDO et la grille du transistor M2 de l'étage d'entrée EtE de l'amplificateur opérationnel AMP.In the same way as for the main power transistor PMosPrinc, the auxiliary power transistors PMos1, ..., PMosn are connected between the supply voltage Vdd_LDO and the gate of the transistor M2 of the input stage EtE of the AMP operational amplifier.

Les transistors de puissance sont de préférence des transistors PMOS. En outre, les dimensions du transistor de puissance principal PMosPrinc sont inférieures aux dimensions des transistors de puissance auxiliaires PMos1, ..., PMosn. Les dimensions sont déterminées en fonction des valeurs des courants Iprinc, Iunit1, ..., Iunitn que l'on souhaite délivrer.The power transistors are preferably PMOS transistors. In addition, the dimensions of the main power transistor PMosPrinc are smaller than the dimensions of the auxiliary power transistors PMos1, ..., PMosn. The dimensions are determined according to the values of currents Iprinc, Iunit1, ..., Iunitn that it is desired to deliver.

Par exemple, on choisit un transistor de puissance principal PMosPrinc délivrant un courant compris entre 0 et 1mA. Les transistors de puissance auxiliaires PMos1, ..., PMosn ont alors des dimensions qui leur permettent de délivrer chacun un courant Iunit1, ..., Iunitn, étant compris entre 0 et 19 mA (le courant dans les transistors de puissance auxiliaires PMosi démarrant à 0 mA).For example, one chooses a PMosPrinc main power transistor delivering a current between 0 and 1mA. The auxiliary power transistors PMos1, ..., PMosn then have dimensions that enable them to deliver a current Iunit1, ..., Iunitn, being between 0 and 19 mA (the current in the auxiliary power transistors PMosi starting at 0 mA).

La grille du transistor de puissance principal PMosPrinc est commandée par la tension de commande principale VGPRINC.The gate of the PMosPrinc main power transistor is controlled by the main control voltage V GPRINC .

Les grilles des transistors de puissance auxiliaires PMos1, ..., PMosn sont respectivement commandés par les n tensions de commande auxiliaires VG1, ..., VGn.The gates of the auxiliary power transistors PMos1, ..., PMosn are respectively controlled by the n auxiliary control voltages V G1 , ..., V Gn .

Les transistors Mos1, ..., Mosn de l'étage de sortie EtS sont toujours conducteurs, et les tensions de commande, VGPRINC, VG1, ..., VGn permettent de rendre conducteurs ou non les transistors de puissance principal PMosPrinc et auxiliaires PMos1, ..., PMosn. Ainsi, dans le cas de faibles courants, seul le transistor de puissance principal PMosPrinc conduit étant donné ses dimensions. Puis, selon la valeur de la tension différentielle sur l'étage d'entrée EtE de l'amplificateur opérationnel AMP, les transistors de puissance auxiliaires PMos1, ..., PMosn deviennent conducteurs et délivrent chacun un même courant qui va augmenter en fonction de la demande jusqu'à attendre la valeur maximale. On peut de cette manière moduler le courant de sortie du régulateur LDO.The transistors Mos1,..., Mosn of the output stage EtS are always conductive, and the control voltages, V GPRINC , V G1 ,..., V Gn, make it possible to make the PMosPrinc main power transistors conductive or not. and auxiliary PMos1, ..., PMosn. Thus, in the case of weak currents, only the power transistor PMosPrinc main leads given its dimensions. Then, according to the value of the differential voltage on the input stage EtE of the operational amplifier AMP, the auxiliary power transistors PMos1, ..., PMosn become conductive and each deliver a same current which will increase as a function of the request until wait for the maximum value. In this way, the output current of the LDO regulator can be modulated.

L'impédance de grille de chaque transistor de puissance auxiliaire PMos1, ..., PMosn est fixée respectivement par les impédances internes Zinternel, ..., Zinternen. De cette façon, et en combinaison avec le fait que les grilles des transistors de puissance ne sont pas interconnectées, on rend indépendant du nombre n de transistors de puissance auxiliaires, les performances du régulateur LDO.The gate impedance of each auxiliary power transistor PMos1, ..., PMosn is respectively fixed by the internal impedances Zinternel, ..., Zinternen. In this way, and in combination with the fact that the gates of the power transistors are not interconnected, the number n of auxiliary power transistors is made independent of the performance of the LDO regulator.

Plus précisément, lorsque l'on connecte une impédance interne sur chaque transistor auxiliaire de sortie, le pôle Le pôle de fréquence de coupure Fc, qui est le premier pôle secondaire du régulateur LDO, vu sur chacune des grilles des transistors de puissance auxiliaires est : Fc = 1 2 * π * Zinternet * C gPMOSi ,

Figure imgb0001
CgPMOSi représentant la capacité parasite pour chaque transistor de puissance auxiliaire.More precisely, when an internal impedance is connected to each output auxiliary transistor, the pole The cut-off frequency pole Fc, which is the first secondary pole of the LDO regulator, seen on each of the gates of the auxiliary power transistor is: Fc = 1 2 * π * Zinternet * VS gPMOSi ,
Figure imgb0001
 C gPMOSi representing the stray capacitance for each auxiliary power transistor.

Le pôle Fc est identique pour chacune des grilles et indépendant de n. On a donc à la fois la conservation des pôles et de la polarisation, quel que soit n. Plus précisément, la gamme de polarisation vaut : ⌊ 0 ; ( Iunit β + Vt ) / Zinterne ⌋ ,

Figure imgb0002
et est indépendant de n.The pole Fc is identical for each of the grids and independent of n. So we have both the conservation of poles and polarization, whatever n. More precisely, the polarization range is: ⌊ 0 ; ( iunit β + vt ) / Zinterne ⌋ ,
Figure imgb0002
 and is independent of n.

Ainsi, selon l'invention, le taux de réjection du régulateur est indépendant de n, de même que la marge de phase du régulateur, ce qui permet d'obtenir une stabilité acceptable quelle que soit la valeur de n.Thus, according to the invention, the rejection ratio of the regulator is independent of n, as is the phase margin of the regulator, which makes it possible to obtain an acceptable stability whatever the value of n.

On se réfère à présent à la figure 3, qui représente l'implémentation du circuit intégré CI, décrit précédemment.Referring now to Figure 3, which shows the implementation of the integrated circuit CI, described above.

La topologie du circuit intégré CI comprend deux parties distinctes. Une première partie INT comprenant des moyens de génération de la tension de référence Vref ainsi que l'amplificateur opérationnel AMP, à l'exception des impédances internes auxiliaires Zinternel, ..., Zinternen.The topology of the integrated circuit CI comprises two distinct parts. A first portion INT comprising means for generating the reference voltage Vref as well as the operational amplifier AMP, with the exception of the internal auxiliary impedances Zinternel, ..., Zinternen.

Une seconde partie EXT comprend deux sous-parties. Une première sous-partie invariante Pinv, comprend des moyens de génération de la tension d'alimentation Vdd_LDO, une borne délivrant la tension de sortie Vout de l'étage de puissance EtP du régulateur LDO, ainsi que la tension d'alimentation des rails d'alimentation Vdd. La sous-partie invariante Pinv comprend en outre le transistor de puissance principal PMosPrinc, qui est conducteur même lorsque le courant de charge Io est faible.A second part EXT comprises two subparts. A first invariant sub-part Pinv comprises means for generating the supply voltage Vdd_LDO, a terminal delivering the output voltage Vout of the power stage EtP of the LDO regulator, as well as the supply voltage for the rail rails. Vdd power supply. The invariant sub-part Pinv further comprises the main power transistor PMosPrinc, which is conductive even when the charging current Io is low.

La seconde partie EXT comporte également une sous-partie modulable Pmod. Cette sous-partie Pmod comprend n modules de puissance identiques et distincts, module 1, module 2, module 3,..., module n. Ces n modules de puissance comprennent les transistors de puissance auxiliaires de l'étage de puissance EtP du régulateur LDO, ainsi que les n impédances internes auxiliaires associées, Zinternel, ..., Zinternen.The second part EXT also has a modular subpart Pmod. This sub-part Pmod comprises n identical and distinct power modules, module 1, module 2, module 3, ..., module n. These n power modules comprise the auxiliary power transistors of the power stage EtP of the LDO regulator, as well as the n associated auxiliary internal impedances, Zinternel, ..., Zinternen.

Les n modules de puissance module 1, module 2, module 3,..., module n, sont connectés entre eux par une cellule de programmation CP, contenue dans la sous-partie modulable Pmod comprenant les connexions nécessaires (non représentées).The n power modules module 1, module 2, module 3, ..., module n, are connected together by a programming cell CP, contained in the modular sub-part Pmod including the necessary connections (not shown).

L'utilisation d'une sous-partie modulable permet de faire varier la valeur de courant de charge Io délivré par le régulateur LDO sans modifier la topologie du circuit intégré CI. En effet, le circuit intégré CI possède un coeur unique quel que soit le courant de charge Io délivré, et l'étage de module est programmable par l'intermédiaire des n modules. On réalise par conséquent un gain de temps sur le dessin et la conception du circuit intégré.The use of a modular sub-part makes it possible to vary the charge current value I o delivered by the LDO regulator without modifying the topology of the integrated circuit CI. Indeed, the integrated circuit CI has a single core regardless of the load current Io delivered, and the module stage is programmable via the n modules. As a result, time is saved in the design and design of the integrated circuit.

En outre, le fait d'inclure les impédances internes auxiliaires dans les modules de puissance permet de réduire la surface de silicium utilisée. Cela permet aussi de réduire la consommation du circuit puisque les drains des transistors Mos1, ..., Mosn sont en l'air lorsque le PMOS auxiliaire correspondant n'est pas utilisé. En effet, les sorties de l'amplificateur opérationnel AMP non connectées (dans le cas où p<n), ne sont pas associées à une impédance interne auxiliaire, puisque celles-ci sont comprises dans les modules de puissance.In addition, including the auxiliary internal impedances in the power modules reduces the silicon area used. This also makes it possible to reduce the consumption of the circuit since the drains of the transistors Mos1,..., Mosn are in the air when the corresponding auxiliary PMOS is not used. Indeed, the outputs of the AMP operational amplifier not connected (in the case where p <n), are not associated with an auxiliary internal impedance, since these are included in the power modules.

Claims (3)

  1. Integrated circuit comprising a low dropout voltage (LDO) regulator, the said regulator (LDO) comprising an operational amplifier (AMP) and a power stage (EtP) which is fed back to the operational amplifier (AMP) and can deliver an output current (Io) into a load (RL), characterized in that:
    - the output stage (EtS) of the amplifier (AMP) has a main output and n auxiliary outputs, which can respectively deliver a main control voltage (VGPRINC) and n auxiliary control voltages (VG1, ... , VGn),
    - in that the power stage (EtP) has a main power transistor (PmosPrinc), controlled at its gate by the main control voltage (VGPRINC), and p power modules (module 1, ..., module n) of identical layout with p less than or equal to n, respectively having p auxiliary power transistors (PMos1, ..., PMosn) each controlled at their gate by p auxiliary control voltages (VG1, ..., VGn) ,
    - and in that the number p is selected as a function of an intended maximum output current.
  2. Integrated circuit according to Claim 1, characterized in that the output stage has a main output transistor (MosPrinc) and n identical auxiliary output transistors (Mos1, ..., Mosn), in that a main internal impedance (MosPrinc) is connected between the supply voltage (Vdd_LDO) and the main output transistor (MosPrinc), in that n identical auxiliary internal impedances (Zinterne1, ..., Zinternen) belonging to the power stage are respectively connected between the supply voltage (Vdd_LDO) and the n auxiliary output transistors (Mos1, ..., Mosn), and in that the layout of the integrated circuit (CI) has a first part (INT) incorporating the operational amplifier (AMP) and its output stage (EtS), apart from the n identical auxiliary internal impedances (Zinterne1, ..., Zinternen), and a second part (EXT) formed by an invariant first sub-part (Pinv) comprising the main power transistor (PMosPrinc) and a modulable second sub-part (Pmod) comprising p power modules (module 1, module 2, module 3, ..., module n) of identical layout, the layout of each power module also incorporating the auxiliary internal impedance intended to be connected to the auxiliary output transistor which can deliver the control voltage to the auxiliary power transistor contained in this power module.
  3. Integrated circuit according to Claim 2, characterized in that the dimensions of the main power transistor (PMosPrinc) are less than the dimensions of the p auxiliary power transistors (PMos1, ..., PMosn).
EP05291508A 2004-07-15 2005-07-13 IC with modulated regulator with low voltage drop Expired - Fee Related EP1617311B1 (en)

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US7417416B2 (en) * 2005-10-27 2008-08-26 International Business Machines Corporation Regulator with load tracking bias
TWI365365B (en) * 2008-01-30 2012-06-01 Realtek Semiconductor Corp Linear regulator and voltage regulation method
US7710144B2 (en) * 2008-07-01 2010-05-04 International Business Machines Corporation Controlling for variable impedance and voltage in a memory system
US8089813B2 (en) * 2008-07-18 2012-01-03 International Business Machines Corporation Controllable voltage reference driver for a memory system
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US4926109A (en) * 1989-06-21 1990-05-15 National Semiconductor Corporation Low dropout voltage regulator with low common current
EP1061428B1 (en) * 1999-06-16 2005-08-31 STMicroelectronics S.r.l. BiCMOS/CMOS low drop voltage regulator
US6246221B1 (en) * 2000-09-20 2001-06-12 Texas Instruments Incorporated PMOS low drop-out voltage regulator using non-inverting variable gain stage
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US6765374B1 (en) * 2003-07-10 2004-07-20 System General Corp. Low drop-out regulator and an pole-zero cancellation method for the same

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