EP1527479A1 - Procede pour realiser un cadre electriquement conducteur et procede pour realiser un composant semi-conducteur qui peut etre monte en surface, et strie de cadre conducteur - Google Patents

Procede pour realiser un cadre electriquement conducteur et procede pour realiser un composant semi-conducteur qui peut etre monte en surface, et strie de cadre conducteur

Info

Publication number
EP1527479A1
EP1527479A1 EP03783921A EP03783921A EP1527479A1 EP 1527479 A1 EP1527479 A1 EP 1527479A1 EP 03783921 A EP03783921 A EP 03783921A EP 03783921 A EP03783921 A EP 03783921A EP 1527479 A1 EP1527479 A1 EP 1527479A1
Authority
EP
European Patent Office
Prior art keywords
layer
window
conductor layer
hardened
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03783921A
Other languages
German (de)
English (en)
Inventor
Gertrud KRÄUTER
Jörg Erich SORG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10306557A external-priority patent/DE10306557A1/de
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP1527479A1 publication Critical patent/EP1527479A1/fr
Withdrawn legal-status Critical Current

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Classifications

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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Definitions

  • the invention relates to a method for producing an electrical lead frame, in particular for a surface-mountable semiconductor component having a semiconductor chip, at least two external electrical connections which are connected in an electrically conductive manner to at least two electrical contacts of the semiconductor chip, and a chip encapsulation. It also relates to a leadframe strip and a method for producing a surface-mountable semiconductor component.
  • Luminescent diode housings with a footprint of size 0402 (this corresponds to 0.5 mm x 1.0 mm) and a component height of 400 ⁇ m - 600 ⁇ m are now available. See data sheet from FAIRCHILD SEMICONDUCTOR® for type QTLP690C-X. The corresponding component concept is described in US Pat. No. 4,843,280.
  • the present invention is based on the object of providing a concept for a surface-mountable semiconductor component, in particular for surface-mountable miniature luminescent diode and / or photodiode components, which permits a further reduction in the size, in particular the overall height.
  • a laminate with an electrically insulating carrier layer and an electrically conductive connecting conductor layer was first produced.
  • This laminate preferably consists of these two layers alone. For example, they can be connected to one another by means of an adhesive layer and can also be completely unstructured.
  • at least one contacting window is produced in the carrier layer in each component section of the laminate toward the connecting conductor layer, and at least one first and one second electrical connection path is formed in the connecting conductor layer, at least one of which can be electrically connected through the contacting window.
  • This electrical lead frame is preferably suitable for Light-emitting diode components with an extremely low overall height of the component housing in relation to the height of the light-emitting diode chip.
  • This lead frame preferably enables very good heat dissipation from the light-emitting diode chip if it is mounted directly on a connecting track in a contacting window of the carrier layer by means of a heat-conducting connecting means such as conductive adhesive or metallic solder.
  • the support layer is preferably structured before the connection conductor layer is structured. This sequence can also be reversed.
  • the carrier layer is preferably a plastic layer that can be structured by means of masking and etching techniques, in particular a plastic film, particularly preferably a polyimide film.
  • the connection conductor layer is likewise preferably an electrically conductive film that can be structured using masking and etching techniques, particularly preferably a metal film.
  • the thicknesses of the carrier layer and the connecting conductor layer are preferably less than 80 ⁇ m and are in particular between 30 ⁇ m and 60 ⁇ m inclusive.
  • a first contacting window for example a chip mounting window, for the first connection path and a second contacting window, for example a wire connection window, for the second connection path are formed in the carrier layer.
  • the carrier layer initially consists at least in the structure to be turing areas preferably made of a detachable plastic layer. Except for the surfaces of the contacting windows and any other areas that are subsequently to be removed, this is preferably made insoluble by hardening or hardening. This means that it is then resistant to the solvent for the plastic layer in these areas.
  • the contacting windows and any other areas to be exposed are subsequently etched free.
  • a mask layer in particular a photoresist layer, is first applied to it. This is applied in a structured or structured manner such that the areas of the contacting windows and other areas to be subsequently removed are covered by the mask layer. Subsequently, the plastic layer is hardened in the uncovered areas that are to remain on the connection conductor layer, before the photoresist layer and the underlying plastic layer are then removed from the connection conductor layer at least in the areas of the contacting windows. The not hardened
  • Plastic layer is preferably removed from the connecting conductor layer by loosening.
  • a photomask is first placed over or on top of it, which shadows the areas of the contacting windows.
  • the plastic layer is then hardened or hardened in unshaded areas which are to remain on the connecting conductor layer.
  • the plastic layer is preferably by means of
  • UV radiation curable Material containing polyimide monomer is preferably suitable for this.
  • a plastic layer curable by means of heat radiation can be used.
  • the photomask layer is subsequently lifted off and the plastic layer in the areas of the contacting windows is removed from the connecting conductor layer. This is preferably done again by means of wet chemical dissolution.
  • the use of a plasma ashing method is conceivable.
  • connection conductor layer is also preferably structured by means of a mask and a wet chemical etching process. Structuring methods of this type, for example for metal layers, are known from printed circuit board technology and are in principle suitable in the present case. They are therefore not explained in more detail here.
  • the structuring methods described can advantageously be integrated in a simple manner into existing manufacturing processes for semiconductor components and can even at least partially use existing techniques that are often used in the production of semiconductor components.
  • a multiplicity of contacting windows and a multiplicity are made into a laminate strip, which preferably consists of a metal foil as the connecting conductor layer and a polyimide foil as the carrier layer, by means of a method as described above produced by these contacting electrical connection tracks.
  • the contacting windows extend to the connecting tracks.
  • a group of contacting windows and associated connecting tracks is located in a component section within a field of a plurality of component sections arranged next to one another on the laminate strip.
  • the connecting conductor layer is at least partially removed along dividing lines between two adjacent component regions. This measure advantageously facilitates the severing of the laminate strip along the dividing lines, which is done, for example, by sawing or punching.
  • the method according to the invention is particularly suitable for producing surface-mountable semiconductor components, each with at least one semiconductor chip, at least two external electrical connection conductors which are connected to at least two electrical contacts of the semiconductor chip, and with a plastic housing which envelops the semiconductor chip.
  • an electrically insulating carrier layer is first applied to an electrically conductive connecting conductor layer. Subsequently, at least one chip window and at least one wire connection window are formed in the carrier layer and at least two external electrical connection conductors are formed in the connection conductor layer. The semiconductor chip is later mounted in the chip window and at least one electrical contact of the semiconductor chip is made by means of a bonding wire
  • Wire connection window electrically connected through a connecting conductor.
  • the composite of structured connection conductor layer, structured carrier layer, semiconductor chip and bond wire is then placed in an injection mold in which the semiconductor chip including bond wire is then encapsulated with a covering material which is subsequently at least partially cured or cured.
  • fields with a large number of component areas are produced in a laminate strip with a connection conductor layer and a carrier layer, in which fields each component area has at least one chip window, at least one wire connection window and at least two external electrical connection conductors , A large number of semiconductor chips are mounted in the large number of chip windows.
  • the electrical contacts of the semiconductor chips are then connected to the external electrical connection conductors by means of bonding wires through the wire connection windows.
  • the fields are subsequently placed individually or in groups one after the other in an injection mold which, for each field, has a single cavity which spans all the component regions of the field and there essentially only forms cavities on the side of the semiconductor chips. Enveloping material is then injected into the cavity and is at least partially hardened there. The field is subsequently removed from the injection mold and separated into separate semiconductor components by severing the sheathing material, the carrier layer and, if necessary, the connecting conductor layer.
  • an electrically insulating carrier layer is likewise first applied to an electrically conductive connecting conductor layer. Subsequently, at least one chip window is formed in the carrier layer and at least two external electrical connection conductors are formed in the connection conductor layer, which partially overlap with the chip window.
  • This structure is suitable, for example, for semiconductor chips in which at least two electrical contacts are arranged on the same side. Such a chip is placed in the chip window with the contacts on the external electrical see connecting conductor mounted and electrically connected.
  • This composite of structured connection conductor layer, structured carrier layer and semiconductor chip is subsequently placed in an injection mold, in which the semiconductor chip is then encapsulated with a coating material which is subsequently at least partially cured or cured.
  • fields with a large number of component areas are produced in a laminate strip with a connection conductor layer and a carrier layer, in which fields each component area has at least one chip window and at least two external electrical connection leads.
  • At least one semiconductor chip is installed in the chip window as described above.
  • the fields are encased and separated in the same way as described above.
  • the method according to the invention is particularly suitable for the production of light-emitting diode components in which light-emitting diode chips are mounted on the lead frame.
  • connection conductor layer preferably made of a structured metal foil
  • carrier layer preferably a structured plastic film, in particular made of polyimide material
  • the contacting windows enable a particularly simple monitoring of the adjustment of the chip assembly and wire bond system.
  • An impermissibly large misalignment of the chip assembly system and / or wire assembly system can be quickly recognized because the semiconductor chips or connecting wires do not adhere to the film after they have been mounted when they touch the edge of the contacting window. This is all the more important the smaller the design, because firstly, the reliability of the components is impaired by a misalignment of the chip assembly, the smaller the volume of the chip encapsulation, and secondly, the amount of rejects in the event of a misalignment that is not immediately recognized is due to the high packing density of the components and the associated large amount of components per unit length on a lead frame tape very high.
  • FIG. 1 shows a schematic sectional illustration of a first exemplary embodiment of a semiconductor component produced by the method according to the invention
  • FIG. 2 shows a schematic sectional illustration of a second exemplary embodiment for a semiconductor component produced by the method according to the invention
  • FIGS. 3a to 3f show a schematic illustration of a first exemplary embodiment for a method sequence according to the invention
  • Figures 4a to 4e is a schematic representation of a second embodiment for a method sequence according to the invention.
  • Figures 5a and 5b are a schematic plan view from below and a schematic plan view from above of a lead frame according to the invention.
  • FIGS. 6a and 6b show a partial schematic representation of a plan view from above of a leadframe strip with coated semiconductor chips, and a partial schematic representation of a top view of the leadframe strip from below;
  • FIG. 7 shows a partial schematic representation of a sectional view of an injection mold with an inserted lead frame strip
  • Figure 8 is a fragmentary schematic representation of a sectional view of a lead frame strip with enveloped
  • a method for producing a leadframe 10 for a surface-mountable semiconductor component according to FIG. 1 or FIG. 2, which in the exemplary embodiment is a light-emitting semiconductor component generally has the following steps: a) producing a layer composite from an electrically insulating carrier layer 101 and an electrically conductive connecting conductor layer 102 (suitable materials for this are for example copper and copper-based alloys) - the carrier layer is preferably a plastic film consisting of polyimide or a material containing polyimide (FIGS.
  • Step c) can alternatively take place before step b).
  • the thickness of the connection carrier layer 101 is between 30 ⁇ m and 60 ⁇ m inclusive. The same applies to the thickness of the connection conductor layer 102.
  • the carrier layer 101 is not yet cured before structuring, at least in the areas to be structured, and can be removed by means of a suitable solvent, and is hardened before the loosening except for the surfaces of the contacting windows 7 and 8 and, if appropriate, other areas to be removed subsequently.
  • the uncured areas of the carrier layer are subsequently removed.
  • a photoresist layer 103 is first applied to it (FIG. 3b), which is structured using known methods in such a way that the regions 70 and 80 of the contacting windows 7, 8 from the Photoresist layer 103 are covered ( Figure 3c).
  • the plastic layer is hardened in the uncovered areas, preferably by means of UV radiation 105 (FIG. 3c).
  • the photoresist layer 103 and the plastic layer underneath are then removed from the connection conductor layer 102.
  • Suitable solvents for this are, for example, IPA (isopropanol) and acetone.
  • a photomask 104 is first arranged above or on top of it, which shadows the areas 70, 80 of the contacting windows 7, 8 (FIG. 4b).
  • the plastic layer is then hardened or cured in the areas which are to remain on the connecting conductor layer 102, preferably by means of UV radiation 105 (FIG. 4b).
  • the photomask layer 104 is removed and then in the regions 70, 80 of the contacting windows 7, 8 the plastic layer is etched from the connecting conductor layer 102 by means of a suitable solvent 106 (FIG. 4c).
  • At least one contacting window 7 and at least two connecting conductors 2, 3 are formed in each component region by means of one of the methods described above.
  • connection conductor layer preferably has recesses 111 and 112, in which the connection conductor layer is removed (FIGS. 5a and 6b).
  • the semiconductor chip 1 is mounted in the chip window 7; c) at least one electrical contact 5 of the semiconductor chip 1 by means of a bonding wire 50 through the wire connection window
  • fields 201 are produced in a laminate strip from connection conductor layer 102 and carrier layer 101, each with a multiplicity of component regions 202, each with at least one chip window 7, at least one wire connection window 8 and at least two connection conductors 2, 3 (cf. FIGS. 6a and 6b).
  • each field is inserted into an injection mold 500 (FIG. 7), in which an entire field 201 is provided for each a single cavity 501 that spans all the component regions 202 of the field 201 and there is essentially only cavity-forming on the side of the semiconductor chips 1.
  • the field 201 is removed from the injection mold 500 and separated into semiconductor components separated from one another by severing the encapsulation material 60 and the connection carrier layer 101.
  • An exemplary method for producing a surface-mountable light-emitting component according to FIG. 2 with at least one light-emitting diode or laser diode chip 1, at least two connecting conductors 2, 3, which are connected to at least two electrical contacts 4, 5 of the semiconductor chip 1, and with a chip housing 11, which has a connection carrier 9 and a chip cladding 6, differs from the method just described only in that each component region has only one chip window and no wire connection window and that the chip 1 in the chip window 7 is turned over with its light-generating epitaxial layer to the connection conductors 2 and 3 facing this is mounted.
  • Both electrical contacts 4 and 5 are located on the same side of the chip 1.
  • the contact 4 is on the connection conductor 2 and the contact 5 on the connection conductor 3.
  • the carrier layer can preferably be hardened or cured by means of UV radiation. Alternatively, it can be hardened or hardened by means of heat radiation. It preferably consists of polyimide monomer.
  • the method according to the invention is particularly preferably suitable for the production of electromagnetic radiation with tating and / or receiving components with one or more electromagnetic radiation emitting and / or receiving semiconductor chips. It is particularly suitable for producing luminescent diode components with a housing footprint of size 0402 (corresponding to 0.5 mm x 1.0 mm) or smaller and a component height of less than 400 ⁇ m, in particular less than 350 ⁇ m.
  • a chip envelope made of an electromagnetic radiation is transparent, at
  • Light emitters used in particular transparent or translucent material.
  • a preferred encapsulant is unfilled clear plastic material. Such materials are known and are therefore not explained in more detail here.
  • the chip casing can be mixed with a phosphor which absorbs at least part of the electromagnetic radiation emitted by the luminescence diode chip and emits electromagnetic radiation of a different wavelength and color than the absorbed radiation.
  • the above-described injection of wrapping material into the cavity is preferably carried out from the side and in particular via a film gate.
  • the field is removed from the injection mold and separated into individual semiconductor components by cutting the chip encapsulation material and the lead frame between the component regions.
  • the chip cladding is preferably provided with a greater thickness in a central area above the semiconductor chip and possibly one or more bonding wires to the semiconductor chip, perpendicular to the lead frame, than in an edge area surrounding the central area.
  • the cavity 501 has a plurality of recesses 502, each of which spans one or more semiconductor chips 1.
  • the volume of encapsulation material is reduced by reducing the thickness of the encapsulation material in areas where this is permissible compared to the thickness in the area of semiconductor chips 1 and possibly one or more bonding wires 50 to the semiconductor chip 1.
  • This can counteract a curvature of the component field during the manufacturing process due to different thermal expansions of the lead frame laminate and the chip encapsulation.
  • a separate recess 502 is preferably provided above each semiconductor chip in the field, such that the wrapping material has a multiplicity of elevations 51 arranged next to one another after the spraying process, in particular has a structure similar to a chocolate bar (cf. FIG. 8).
  • the field is advantageously separated by cutting through the covering material and the lead frame in the trenches 52 between the elevations 51.
  • an adhesion promoter is applied to the carrier layer 101 before inserting the field into the injection mold 500, which improves the adhesion of the wrapping material to the lead frame.
  • a PI topcoat is preferably used for this.
  • the lead frame can be laminated with its back onto an auxiliary film 400 before insertion into the injection mold.
  • This auxiliary film protects, on the one hand, the connection conductors 2, 3 against mechanical damage (eg scratching) and, on the other hand, against an undesired covering of the connection conductors with wrapping material, that is to say against a so-called flash on the back of the lead frame strip.
  • the auxiliary film expediently has a similar or a greater coefficient of thermal expansion to that of the wrapping material, in such a way that it counteracts as far as possible warping of the field due to a greater shrinkage of the wrapping material compared to the lead frame during its curing and / or cooling after the extrusion coating of the field.
  • the laminate strip can have bores, openings and / or slots outside the fields to reduce mechanical stresses due to different thermal expansions and / or material shrinkages.
  • a cambered injection mold can be used, in which the field is curved convexly from the side on which the material with the greater coefficient of thermal expansion is later to be seen during the injection of the encapsulant into the cavity.
  • the field is separated with the wrapping side applied to a film and subsequently, if necessary, the auxiliary film removed from the back of the lead frame.
  • this film is preferably transparent to electromagnetic radiation and the measurement is carried out through the film.
  • the field is preferably separated by means of saws, laser cutting and / or water jet cutting.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

La présente invention concerne un procédé pour réaliser un cadre électriquement conducteur (10), destiné notamment à un composant à diode luminescente, comprenant au moins un premier (2) et un second (3) conducteur électrique de connexion. Le procédé comprend les étapes suivantes: a) réalisation d'une couche composite comprenant une couche support (101) électriquement isolante et une couche de connexion électrique (102) électriquement conductrice; b) structuration de la couche support (101) de sorte que dans celle-ci est formée au moins une fenêtre de contact (7) dirigée vers la couche de connexion électrique (102); c) structuration de la couche de connexion électrique (102) afin de produire le premier (2) et le second (3) conducteur électrique de connexion dont au moins l'un peut être raccordé électriquement en passant à travers la fenêtre de contact (7). La présente invention a également pour objet une strie de cadre conducteur comprenant une couche conductrice de connexion et une couche support de connexion, sur laquelle est formé un champ avec une pluralité de zones de composants, la couche conductrice de connexion étant séparée au moins partiellement par des lignes de séparation qui séparent deux zones de composants voisines.
EP03783921A 2002-08-05 2003-07-25 Procede pour realiser un cadre electriquement conducteur et procede pour realiser un composant semi-conducteur qui peut etre monte en surface, et strie de cadre conducteur Withdrawn EP1527479A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US40127302P 2002-08-05 2002-08-05
US401273P 2002-08-05
DE10306557 2003-02-17
DE10306557A DE10306557A1 (de) 2002-08-05 2003-02-17 Verfahren zum Herstellen eines elektrischen Leiterrahmens, Verfahren zum Herstellen eines oberflächenmontierbaren Halbleiterbauelements und Leiterrahmenstreifen
PCT/DE2003/002522 WO2004015769A1 (fr) 2002-08-05 2003-07-25 Procede pour realiser un cadre electriquement conducteur et procede pour realiser un composant semi-conducteur qui peut etre monte en surface, et strie de cadre conducteur

Publications (1)

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EP1527479A1 true EP1527479A1 (fr) 2005-05-04

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EP03783921A Withdrawn EP1527479A1 (fr) 2002-08-05 2003-07-25 Procede pour realiser un cadre electriquement conducteur et procede pour realiser un composant semi-conducteur qui peut etre monte en surface, et strie de cadre conducteur

Country Status (5)

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EP (1) EP1527479A1 (fr)
JP (1) JP4653484B2 (fr)
CN (1) CN100533723C (fr)
TW (1) TWI221027B (fr)
WO (1) WO2004015769A1 (fr)

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JP5217800B2 (ja) 2008-09-03 2013-06-19 日亜化学工業株式会社 発光装置、樹脂パッケージ、樹脂成形体並びにこれらの製造方法
DE102008053489A1 (de) * 2008-10-28 2010-04-29 Osram Opto Semiconductors Gmbh Trägerkörper für ein Halbleiterbauelement, Halbleiterbauelement und Verfahren zur Herstellung eines Trägerkörpers
US7993981B2 (en) * 2009-06-11 2011-08-09 Lsi Corporation Electronic device package and method of manufacture
JP5302117B2 (ja) * 2009-06-22 2013-10-02 スタンレー電気株式会社 発光装置の製造方法、発光装置および発光装置搭載用基板
EP2418700B1 (fr) * 2010-08-09 2017-11-01 LG Innotek Co., Ltd. Dispositif électroluminescent
KR101114719B1 (ko) * 2010-08-09 2012-02-29 엘지이노텍 주식회사 발광 소자 및 이를 구비한 조명 시스템
KR101114197B1 (ko) * 2010-08-09 2012-02-22 엘지이노텍 주식회사 발광 소자 및 이를 구비한 조명 시스템
JP5995579B2 (ja) * 2012-07-24 2016-09-21 シチズンホールディングス株式会社 半導体発光装置及びその製造方法
CN104576631B (zh) * 2014-12-05 2020-03-17 复旦大学 光电检测集成芯片
JP6056934B2 (ja) * 2015-10-09 2017-01-11 日亜化学工業株式会社 発光装置、樹脂パッケージ、樹脂成形体並びにこれらの製造方法
JP6164355B2 (ja) * 2016-12-07 2017-07-19 日亜化学工業株式会社 発光装置、樹脂パッケージ、樹脂成形体並びにこれらの製造方法
DE102017105235B4 (de) * 2017-03-13 2022-06-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Bauelement mit Verstärkungsschicht und Verfahren zur Herstellung eines Bauelements
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TW200402862A (en) 2004-02-16
JP2005535135A (ja) 2005-11-17
WO2004015769A1 (fr) 2004-02-19
JP4653484B2 (ja) 2011-03-16
TWI221027B (en) 2004-09-11
CN100533723C (zh) 2009-08-26
CN1675766A (zh) 2005-09-28

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