EP1356384A1 - Topologie d'interconnexions pour systeme informatique reparti extensible - Google Patents

Topologie d'interconnexions pour systeme informatique reparti extensible

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Publication number
EP1356384A1
EP1356384A1 EP00991412A EP00991412A EP1356384A1 EP 1356384 A1 EP1356384 A1 EP 1356384A1 EP 00991412 A EP00991412 A EP 00991412A EP 00991412 A EP00991412 A EP 00991412A EP 1356384 A1 EP1356384 A1 EP 1356384A1
Authority
EP
European Patent Office
Prior art keywords
dimensional
computer network
inter
intra
nodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00991412A
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German (de)
English (en)
Inventor
Nir c/o EXANET CO. PELEG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Exanet Inc
Original Assignee
Exanet Inc
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Filing date
Publication date
Application filed by Exanet Inc filed Critical Exanet Inc
Publication of EP1356384A1 publication Critical patent/EP1356384A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/12—Discovery or management of network topologies

Definitions

  • This invention is related to an interconnection topology for a scalable distributed computer system.
  • the invention relates the a mesh network using intra-dimensional and inter-dimensional switches to realize a scalable distributed computer system that can be rapidly enlarged while minimizing hardware impact.
  • the parallel processors must be interconnected such that the performance of the parallel processors is as close as possible to the number of processors times the performance of a single processor.
  • computations suitable for a single processor must be partitioned into a large number of computations that can be performed independently on distinct processors. Results obtained from each individual processor must be compiled to provide the identical computation that is achievable with a single processor.
  • This computational sharing requires a significant amount of communication between the parallel processors. Typically, the time required for this inter-processor communication dominates the computational time and, as such, represents a significant roadblock improved parallel processor performance.
  • the crossbar switch provides the most effective inter processor communication.
  • the crossbar switch provides a non-blocking network that interconnects inputs and outputs for all of the processors. Any one to one communication task is implemented with minimal blocking and with pipelining, so that one word can be provided to every processor on each communication cycle, using the crossbar switch.
  • the crossbar switch becomes impractical because of the large number of wires and crosspoints that are required to implement this apparatus.
  • hypercube An alternative network commonly used for inter-processor communication is the hypercube.
  • a hypercube contains far fewer crosspoints than the crossbar switch.
  • the computation of the crosspoint switch settings for both the crossbar switch and the hypercube network is very time consuming since there are many communication tasks and computational tasks that must be implemented.
  • Extensive work has been done in the prior art to address the issues of blocking and contention in hypercube networks and the use of routers that are based solely on source and destination addresses are common.
  • any network and routing procedure that permits blocking can not be optimal and significantly degrades the computing performance of the multiprocessor.
  • SIMD single instruction multiple data stream
  • SIMD machines are well suited for application such as numerical solution of differential equations where the identical numerical computation is carried out on each distinct grid point.
  • MIMD multiple instruction multiple data stream
  • connection topology of the processing elements that is, the way in which the communication channels link the processors.
  • Various communication topologies have been extensively studied. Typically, most communication topologies consist of regular grids in one or more dimensions (i.e., the grid's vertices represent processing elements and the edges represent communication channels). These studies have concluded that the computational problem at hand dictates the optimal processor connectivity. Hence, one option is to build a special purpose processor for each problem to be solved. A more practical alternative is to use complex processor connectivity incorporating a large number of useful sub-topologies.
  • hypercube architecture An example of the second alternative is hypercube architecture.
  • the processor connectivity is that of an n-dimensional Boolean hypercube.
  • a hypercube of dimension n has 2" processors each connected to n neighbors.
  • This connection topology allows the embedding of regular meshes of lower dimension than the hypercube using a subset of the hypercube connections.
  • Gray coding Such mappings are easily carried out using a technique known as Gray coding.
  • a hypercube of dimension 1 is illustrated in conceptual form.
  • a hypercube of dimension 1 is comprises two processors positioned at network node location 1,2 linked together through a communications link 3.
  • a hypercube of dimension 2 is illustrated in conceptual form. Each processor positioned at a network node location 4-7 of the hypercube is connected to two other processor located at other network node locations in the network through communications links 8a- 8d.
  • a hypercube of dimension 3 is illustrated in conceptual form.
  • the network of eight processors is configured in a cube, and each processor positioned at a network node location is connected to three of the other processor in the cube (reference characters are omitted for the sake of clarity) through communication links.
  • FIG. ID a hypercube of dimension 4 is illustrated in conceptual form.
  • a dimension 4 hypercube has sixteen processors. Each of the processors in this hypercube is connected to four of the processors in the hypercube through (reference characters are omitted for the sake of clarity) communication links.
  • the hypercube illustrated in FIG. ID is one possible interconnect topology for a dimension 4 hypercube.
  • Interconnect topologies are often the cause for lack of scalability in distributed systems. It is desirable to have a topology that does not generate "hot spots.” This is possible by spreading interconnect loads evenly throughout the system. It is also desirable to maintain a quality of service that is independent of system size. Quality of service can be quantified by measuring the following system properties on a per-client basis:
  • a first aspect of the invention provides a fully populated computer network comprising a plurality of computer nodes (n) arranged in a mesh having a dimension (m).
  • the computer network further comprises a plurality of inter-dimensional switches of width d, wherein width d represents the number of ports available on each inter-dimensional switch. Each occupied node is attached to one inter-dimensional switch.
  • the computer network further comprises a plurality of intra-dimensional switches of width w, wherein width w represents the number of ports available on each intra- dimensional switch.
  • Each inter-dimensional switch is connected to one or more (d in the fully populated case) intra-dimensional switch.
  • the number of nodes in the computer network is equal to w d .
  • a second aspect of the invention provides a fully populated computer network comprising a plurality of computer nodes (n) arranged in a mesh having a dimension (m).
  • the computer network further comprises a plurality of inter-dimensional switches of width d + 1, wherein width d + 1 represents the number of ports available on each inter-dimensional switch. Each occupied node is attached to a port of one inter-dimensional switch.
  • the computer network further comprises a plurality of intra-dimensional switches of width w, wherein width w represents the number of ports available on each intra-dimensional switch.
  • Each inter-dimensional switch is connected to one or more (d in the fully populated case) intra-dimensional switch.
  • the number of nodes in the computer network is equal to w d .
  • a third aspect of the invention provides a partially populated computer network comprising a plurality of computer nodes a plurality of nodes arranged in a mesh of dimension m, wherein m represents the maximum number of nodes connected to any one node of the plurality of nodes, and n represents the number of occupied nodes.
  • the computer network further comprises a plurality of inter-dimensional switches of width d, wherein width d represents the number of ports available on each inter-dimensional switch. Each occupied node is attached to one inter-dimensional switch.
  • the computer network further comprises a plurality of intra-dimensional switches, of width w, wherein width w represents the number of ports available on each intra-dimensional switch. Each intra-dimensional switch is connected to a port on at least one inter-dimensional switch. The number of occupied nodes n is less than w d .
  • a fourth aspect of the invention provides a partially populated computer network comprising a plurality of nodes arranged in a mesh of dimension m, wherein m represents the maximum number of nodes connected to any one node of the plurality of nodes, and n represents the number of occupied nodes.
  • the computer network further comprises a plurality of inter- dimensional switches of width d + 1, wherein width d + 1 represents the number of ports available on each inter-dimensional switch. Each occupied node is attached to a port of one inter-dimensional switch.
  • the computer network further comprises a plurality of intra-dimensional switches of width w, wherein width w represents the number of ports available on each intra- dimensional switch. Each intra-dimensional switch is connected to a port on at least one inter-dimensional switch.
  • a fifth aspect of the invention provides a computer network comprising a plurality of nodes arranged in a mesh of dimension m, wherein m represents the maximum number of nodes connected to any one node of the plurality of nodes, and n represents the number of occupied nodes.
  • the computer network further comprises a plurality of inter-dimensional switches of width d, wherein width d represents the number of ports available on each inter-dimensional switch and wherein each inter-dimensional switch has at least two occupied nodes attached thereto.
  • the computer network further comprises a plurality of intra-dimensional switches of width w, wherein width w represents the number of ports available on each intra-dimensional switch. Each intra-dimensional switch is connected to a port on at least one inter- dimensional switch.
  • the computer network may be partially or fully populated, such that the number of occupied nodes n is less than or equal to w d .
  • a sixth aspect of the invention provides a computer network comprising a plurality of nodes arranged in a mesh of dimension m, wherein m represents the number of nodes connected to any one node of the plurality of nodes, and n represents the number of occupied nodes.
  • the computer network further comprises a plurality of inter-dimensional switches of width d
  • a seventh aspect of the invention provides a computer network node that comprises at least one processor and an inter-dimensional network switch of width d, wherein width d represents the number of ports available on the inter-dimensional network switch connected to the at least one processor.
  • the inter-dimensional switch transmits and receives data from at least one other computer network node, and the at least one other computer network node comprises a plurality of computer network nodes arranged in a mesh of dimension m, wherein m represents the number of computer network nodes connected to any one node of the plurality of nodes.
  • the other computer network nodes are interconnected by plurality of intra-dimensional switches each with a width w.
  • the computer network may be partially or fully populated, such that the number of computer network nodes is less than or equal to w d .
  • An eighth aspect of the invention provides a computer network node that comprises at least one processor and an inter-dimensional network switch of width d + 1, wherein width d + 1 represents the number of ports available on the inter-dimensional network switch connected to at least one processor.
  • the inter-dimensional switch transmits and receives data from at least one other computer network node, and at least one other computer network node comprises a plurality of computer network nodes arranged in a mesh of dimension m, connected to any one node of the plurality of nodes.
  • the other computer network nodes are interconnected by plurality of intra-dimensional switches each with a width .
  • the computer network may be partially or fully populated, such that the number of computer network nodes is less than or equal to w d .
  • FIG. 1 A illustrates a one-dimensional hypercube
  • FIG. IB illustrates a two-dimensional hypercube
  • FIG. 1C illustrates a three-dimensional hypercube
  • FIG. ID illustrates a four-dimensional hypercube
  • FIG. 2 illustrates a fully-populated network using an interconnect topology according to an aspect of the present invention
  • FIGS. 3A-3C illustrate two dimensional perspective of the fully- populated network depicted in FIG. 2;
  • FIGS. 4A-4C illustrate another two dimensional perspective of the fully-populated network depicted in FIG. 2;
  • FIG. 5 illustrates a processor according to an aspect of the present invention with the network switch incorporated internally
  • FIG. 6 illustrates a processor according to an aspect of the present invention with an external network switch
  • FIG. 7 illustrates a processor comprised of several independent processors networked through a single external network switch
  • FIG. 8 illustrates a processor comprised of several independent processors networked through a single inter-dimensional switch
  • FIG. 9 illustrates a partially populated network according to an aspect of the invention.
  • FIGS. 10A-10C illustrates a plurality of independent processors connected to a minimum number of network switches
  • FIGS. 11 A-D illustrates sharing a minimum number of network switches to realize an interconnection topology according to an aspect of the invention.
  • computer system encompasses the widest possible meaning and includes, but is not limited to, standalone processors, networked processors, mainframe processors, and processors in a client/server relationship.
  • computer system is to be understood to include at least a memory and a processor.
  • the memory will store, at one time or another, at least portions of executable program code, and the processor will execute one or more of the instructions included in that executable program code.
  • embedded computer system includes, but is not limited to, an embedded central processor and memory bearing object code instructions.
  • embedded computer systems include, but are not limited to, personal digital assistants, cellular phones and digital cameras.
  • any device or appliance that uses a central processor, no matter how primitive, to control its functions can be labeled has having an embedded computer system.
  • the embedded central processor will execute one or more of the object code instructions that are stored on the memory.
  • the embedded computer system can include cache memory, input output devices and other peripherals.
  • predetermined operations the term "computer system software” and the term “executable code” mean substantially the same thing for the purposes of this description. It is not necessary to the practice of this invention that the memory and the processor be physically located in the same place. That is to say, it is foreseen that the processor and the memory might be in different physical pieces of equipment or even in geographically distinct locations.
  • the terms "media,” “medium” or “computer-readable media” include, but is not limited to, a diskette, a tape, a compact disc, an integrated circuit, a cartridge, a remote transmission via a communications circuit, or any other similar medium useable by computers.
  • the supplier might provide a diskette or might transmit the instructions for performing predetermined operations in some form via satellite transmission, via a direct telephone link, or via the Internet.
  • program product is hereafter used to refer to a computer-readable medium, as defined above, which bears instructions for performing predetermined operations in any form.
  • network switch includes, but is not limited to, hubs, routers, ATM switches, multiplexers, communications hubs, bridge routers, repeater hubs, ATM routers, ISDN switches, workgroup switches, Ethernet switches, ATM/fast Ethernet switches and CDDITFDDI concentrators, Fiber Channel switches and hubs, InfiniBand Switches and
  • FIG. 2 a fully populated computer network is illustrated according to an aspect of the present invention. Please note that the concepts of the present invention do not require the each dimension of the network to be fully populated. As shown in FIG. 8, a partially populated network can function as well using the concepts of the present invention.
  • network node location refers to a point in the network topology where a processor or a plurality of processors operating in a master/slave configuration would be connected to the network.
  • the network topology is comprised of a plurality of network switches and a plurality of independent processors.
  • the network topology is comprised of a plurality of network switches and a plurality of independent processors.
  • there are twenty-seven independent network node locations (111, 112, 113, 121, 122, 123, 131, 132, 133, 211, 212, 213, 221, 222, 223, 231, 232, 233, 311, 312, 313, 321, 322, 323, 331, 332, 333).
  • Each network node location in the network is connected to three other network node locations.
  • width refers to the number of available ports on either an inter-dimensional switch or an intra-dimensional switch.
  • each processor located at a network node location is connected to three intra-dimensional switches.
  • the inter-dimensional switch connected to the processor effects the connection to the intra-dimensional switch. For example, consider the processors located at network node location 111, network node location 121 and network node location 131. These processors are connected to an intra-dimensional switch
  • the processor at network node location 111 is also connected to processors located at network node location 211 and at network node location 311 through another intra-dimensional switch 414. Finally, the processor located at network node location 111 is connected to the processor at network node location 112 and the processor at network node location 113 through intra-dimensional switch 511. The processors at other network node locations in the network topology illustrated in FIG. 2 are similarly interconnected.
  • FIG. 3A a portion of the fully populated dimension 3 network of FIG. 2 is illustrated.
  • FIG. 3A depicts a 3 x 3 "dimensional section" of the fully populated dimension 3 network.
  • network node locations are shown arranged in two directions.
  • the processors located at network node location 111, network node location 121 and network node location 131 are interconnected through intra-dimensional switch 411.
  • the processors at network node location 211, network node location 221 and network node location 231 are interconnected through intra-dimensional switch 412.
  • the processors located at network node location 311, network node location 321 and network node location 331 are interconnected through intra-dimensional switch 413. In this manner, one of the three required network node location connections for a fully populated dimension 3 network according to the present invention is accomplished.
  • the processor located at each network node location would be connected to five other processors located at other network node locations in the dimension 5 network.
  • the dimension of the network topology is directly related to the maximum number of connections to each network node location.
  • the processors located at network node location 111, network node location 211 and network node location 311 are interconnected through intra-dimensional switch 414.
  • the processors located at network node location 121, network node location 221 and network node location 321 are interconnected through intra-dimensional switch 415.
  • the processors at network node location 131, network node location 231 and network node location 331 are interconnected through intra-dimensional switch 416. In this manner, the second of the three required network node location connections for a fully populated dimension 3 network according to the present invention is accomplished.
  • the same interconnection concepts apply to the dimensional slices illustrated in FIGS.
  • FIG. 4A a portion of the fully populated dimension 3 network of FIG. 2 is illustrated.
  • FIG. 4A depicts a 3 x 3 "cross dimensional section" of the fully populated dimension 3 network from a different perspective than FIG. 3A.
  • network node locations are shown arranged in two directions.
  • the next group of processors located at network node location 121, network node location 122 and network node location 123 are interconnected by intra- dimensional switch 512.
  • the last group of processors located at the network node location 131, network node location 132 and network node location 133 are interconnected by intra-dimensional switch 513.
  • the interconnection concepts apply equally to the cross dimensional sections illustrated in FIGS. 4B and 4C, and therefore the description thereof is omitted.
  • the width d refers to the number of available ports on an inter-dimensional switch.
  • the width w refers to the number of ports available on an intra-dimensional switch.
  • the widths of the intra- dimensional switches and the width of the inter-dimensional switch can be used to determine the number of nodes in a given network topology. In a fully populated network topology, the total number of nodes n is given by Equation 1:
  • Equation 2 The number of intra-dimensional switches p necessary to implement a fully populated network is given by Equation 2 or Equation 3:
  • an embodiment of the present invention uses inter-dimensional switches that are connected to the processor at the network node location through one of the ports that is available for connection to intra- dimensional switches.
  • an inter-dimensional switch may have twelve ports, but one of those ports is dedicated to the connection to the processor.
  • the inter-dimensional switch only has eleven ports available for connection to intra-dimensional switches.
  • the notation "d + 1" refers to an inter-dimensional switch that is used in this manner.
  • the processor 10 incorporates an inter-dimensional switch 11.
  • the processor 10 can execute any one of several different operating systems.
  • the processor 10 comprises storage devices with storage mediums for data caching (i.e., semiconductor memory) and data storage (not shown).
  • the storage devices are hard disk devices. Current hard disk devices, having storage capacities ranging in the gigabyte range, are well suited to the present invention.
  • the storage device may also comprise a RAID device to allow for greater system availability. Other types of storage devices, such as optical drives, tape storage and semiconductor memory can be used as well.
  • the inter-dimensional switch 11 incorporated in the processor 10 uses the InfiniBand protocol for data transmission and communication, but other bus protocols can be used as well.
  • the inter- dimensional switch 11 has a plurality of ports such that the processor 10 can be connected to other network switches, and thereby be connected to other processor nodes according to the present invention.
  • the ports of the inter- dimensional switch 11 are connected to other network switches via communication links 15-17, thereby connecting the processor 10 to other processors according to the present invention.
  • the processor 12 is connected to a port on the external network switch 13 via communications link 14.
  • the processor 12 can execute any one of several different operating systems.
  • the processor 12 comprises storage devices with storage mediums for data caching (i.e., semiconductor memory) and data storage (not shown).
  • the storage devices are hard disk devices. Current hard disk devices, having storage capacities ranging in the gigabyte range, are well suited to the present invention.
  • the storage device may also comprise a RAID device to allow for greater system availability. Other types of storage devices, such as optical drives, tape storage and semiconductor memory can be used as well.
  • the external network switch 13 uses the InfiniBand protocol for data transmission and communication to other network switches as well as to the processor 12, but other bus protocols can be used as well.
  • the ports of the external network switch 13 are connected to other network switches via communication links 15-17, thereby connecting the processor 12 to other processors according to the present invention.
  • the processor node is connected to a port on the external network switch 13 via bus 22.
  • the connection can also be link based as well.
  • the processor 18 comprises multiple processors 19-21, and the processors 19-21 execute any one of several different operating systems.
  • the multiple processors are interconnected via bus 22.
  • the processor 18 comprises storage devices with storage mediums for data caching (i.e., semiconductor memory) and data storage (not shown).
  • the storage devices are hard disk devices. Current hard disk devices, having storage capacities ranging in the gigabyte range, are well suited to the present invention.
  • the storage device may also comprise a RAID device to allow for greater system availability. Other types of storage devices, such as optical drives, tape storage and semiconductor memory can be used as well.
  • the processor 18 is comprised of multiple processors, to the outside world, it appears as one processor. Typically, one of the processors would be a master (19) and the remaining processors (20-21) would be slaves. Other types of multiple processor configurations would be acceptable substitutes as well.
  • the external network switch 13 uses the InfiniBand protocol for data transmission and communication to other network switches as well as to the processor 18, but other bus protocols can be used as well. The ports of the external network switch 13 are connected to other network switches via communication links 15-17, thereby connecting the processor 18 to other processors according to the present invention.
  • the processor 18 comprises multiple processors 19-21, and the processors 19-21 execute any one of several different operating systems, and one of the processors 23 incorporates an inter-dimensional switch 11.
  • the multiple processors are interconnected via bus 22.
  • the processor 18 comprises storage devices with storage mediums for data caching (i.e., semiconductor memory) and data storage (not shown).
  • the storage devices are hard disk devices. Current hard disk devices, having storage capacities ranging in the gigabyte range, are well suited to the present invention.
  • the storage device may also comprise a RAID device to allow for greater system availability. Other types of storage devices, such as optical drives, tape storage and semiconductor memory can be used as well.
  • the processor 18 is comprised of multiple processors, to the outside world, it appears as one processor. Typically, one of the processors would be a master (22) and the remaining processors (20-21) would be slaves. Other types of multiple processor configurations would acceptable substitutes as well.
  • the inter-dimensional switch 13 uses the InfiniBand protocol for data transmission and communication to other network switches as well as to the processor 18, but other bus protocols can be used as well.
  • the ports of the inter-dimensional switch 13 are connected to other network switches via communication links 15-17, thereby connecting the processor 18 to other processors according to the present invention.
  • FIG. 9 is similar to FIG. 2 in that a dimension 3 network topology is shown. Unlike the network topology illustrated in FIG. 2, all the available network node locations are not used.
  • the interconnect topology of FIG. 9 still realizes all the advantages of the present invention, and is a more typical implementation of the invention for widespread networks.
  • the processors located at network node location 131, network node location 122, network node location 113, network node location 212, network node location 321 and network node location 333 are missing. Therefore, since these processors are not included in the network topology, the corresponding connections to the various intra-dimensional and intra- dimensional switches do not have to be realized.
  • a partially populated network topology is illustrative of the scalability of the network topology according to the invention.
  • a partially populated network can be constructed at a given instance in time, and if user demand requires increasing the processing power of the network, additional processors can occupy the unused network node locations without having to redesign the network topology.
  • a processor will comprise an inter-dimensional network switch in order to interconnect with the other processors located at other network node locations. And as previously described, if an external inter- dimensional network switch is used, the processor connects to a port on the inter-dimensional network switch, and the other ports are used for interconnecting to the other processors. This is the d + 1 configuration. If the network topology requires a large number of network switches, the cost can become great. However, the present invention provides for a single inter- dimensional switch that can provide networking services to multiple processors, thereby providing considerable savings in equipment costs.
  • inter- dimensional network switch 38 provides interconnection services for processor 30 located at network node location 111, processor 31 located at network node location 121, processor 32 located at network node location 131 and processor 33 located at network node location 211.
  • the inter-dimensional network switch 38 has sixteen ports, and the inter- dimensional network switch 38 is divided into four sections of four ports each. For example, in the first section connected to processor 30, one port handles the connection between the network switch 38 and the processor 30. The remaining three ports are connected to intra-dimensional switch 411 (SW411), intra-dimensional switch 414 (SW414) and intra-dimensional switch 511 (SW511)(please see FIG.
  • FIG. 2 For the network interconnect topology).
  • the processor 31 at network node location 121 utilizes a second section of inter-dimensional network switch 38, and the necessary connections are realized as shown in FIG. 2.
  • FIGS. 10B-10C illustrate the other processors 32-38 are connected to the inter-dimensional network switches 39-41 in similar fashion.
  • FIGS. 11A-11D the concept of having a single network switch provide the interconnection support of several network switches is further illustrated as applied to the intra-dimensional switches.
  • FIGS. IIA and 11B all the intra-dimensional switches required to realize the partial network shown in FIG. 3A are shown.
  • the intra-dimensional network switches 45, 46 are twelve port switches that have been divided into four sections.
  • the first section SW411 acts as an intra- dimensional switch for the processors located at network node locations 111, 121 and 131.
  • the second section SW412 acts as an intra-dimensional switch for the processors located at network node locations 211, 221, and 231.
  • the third section SW413 acts as an intra-dimensional switch for the processors located at network node locations 311, 321, and 331.
  • the fourth section SW414 acts as an intra-dimensional switch for the processors located at network node locations 111, 211, and 311.
  • a second intra-dimensional network switch 46 realizes the intra-dimensional switches the remaining intra- dimensional switches (SW415 and SW416) for the partial network shown in FIG. 3A.
  • two intra-dimensional network switches replace six separate intra-dimensional network switches using the port allocation of the present invention.
  • an intra-dimensional network switch 48 provides interconnection services for the partial network illustrated in FIG. 4C.
  • the intra-dimensional network switch 48 is divided into three sections.
  • the first section (SW531) provides interconnects the processors at network node locations 311, 312 and 313.
  • the first section (SW532) interconnects the processors at network node locations 321, 322 and 323.
  • the third section (SW533) interconnects the processors at network node locations 331, 332 and 333.

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Abstract

L'invention concerne une topologie de réseau informatique présentant une configuration à d dimensions, dans laquelle chaque noeud (211) de traitement est relié à la topologie de réseau informatique par un commutateur interdimensionnel. Chaque commutateur interdimensionnel est connecté à plusieurs commutateurs (414) intradimensionnels en fonction du nombre de dimensions de la topologie du réseau informatique. Chaque commutateur (414) intradimensionnel peut être connecté par un certain nombre de ports à une série de commutateurs interdimensionnels.
EP00991412A 2000-12-21 2000-12-21 Topologie d'interconnexions pour systeme informatique reparti extensible Withdrawn EP1356384A1 (fr)

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PCT/US2000/034258 WO2002052425A1 (fr) 2000-12-21 2000-12-21 Topologie d'interconnexions pour systeme informatique reparti extensible

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CA1293819C (fr) * 1986-08-29 1991-12-31 Thinking Machines Corporation Ordinateur a tres grande echelle
US5008882A (en) * 1987-08-17 1991-04-16 California Institute Of Technology Method and apparatus for eliminating unsuccessful tries in a search tree
US5471580A (en) * 1991-10-01 1995-11-28 Hitachi, Ltd. Hierarchical network having lower and upper layer networks where gate nodes are selectively chosen in the lower and upper layer networks to form a recursive layer

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