EP1352420A1 - Insulating structures of buried layers with buried trenches and method for making same - Google Patents

Insulating structures of buried layers with buried trenches and method for making same

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Publication number
EP1352420A1
EP1352420A1 EP02710091A EP02710091A EP1352420A1 EP 1352420 A1 EP1352420 A1 EP 1352420A1 EP 02710091 A EP02710091 A EP 02710091A EP 02710091 A EP02710091 A EP 02710091A EP 1352420 A1 EP1352420 A1 EP 1352420A1
Authority
EP
European Patent Office
Prior art keywords
buried
zones
conductivity
trench
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02710091A
Other languages
German (de)
French (fr)
Inventor
Olivier Menut
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP1352420A1 publication Critical patent/EP1352420A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Definitions

  • the present invention relates to the manufacture of integrated circuits.
  • the present invention is more particularly suitable for the production of devices of the MOS or complementary MOS type or the manufacture, in the same semiconductor substrate, of bipolar type transistors and of transistors of complementary MOS type (BiCMOS).
  • BiCMOS complementary MOS type
  • the first step is to produce buried layers in the semiconductor substrate, generally made of silicon, which will later play a specific role depending on the component produced.
  • the buried layers may in particular be collectors for bipolar transistors, or even bottom receptacles for MOS transistors.
  • These buried layers are characterized by their P or N type doping in order to satisfy the specificities of the components that one wishes to produce (bipolar NPN or PNP transistor, NMOS or PMOS transistor).
  • CMOS complementary metal-oxide-semiconductor
  • BiCMOS bipolar transistors
  • the buried layers within the same substrate, cannot be doped independently of each other.
  • the doping levels of the buried layers define in particular parasitic phenomena such as the breakdown voltages between layers of type P and N, as well as the drilling voltages between layers of the same type of conductivity.
  • the breakdown voltage between two layers of reverse conductivities is lower the higher the doping gradient between these layers. This is generally the case when the buried layers are heavily doped. Furthermore, the risk of drilling between buried layers of the same type, is all the greater as the distance separating the two layers is reduced. The separation zone of reverse conductivity, not strongly doped and becoming increasingly narrow, can no longer play its role of insulator between the two buried layers of the same nature. The miniaturization of integrated circuits necessarily leads to an increase in this risk.
  • the invention essentially consists in the formation of buried trenches isolating laterally from each other, the buried layers of identical or different conductivities.
  • buried trenches isolating laterally from each other, the buried layers of identical or different conductivities.
  • These trenches are positioned so as to separate the buried layers of different or identical conductivity from each other. These trenches prevent the diffusion of dopants from one buried layer to the other, also reducing the risk of lowering the breakdown voltage.
  • the intrinsic correct functioning of the components is ensured due to independent doping of the buried layers of the device.
  • the invention thus provides an integrated circuit, comprising a semiconductor substrate, for example made of silicon, comprising at least one buried, vertical, dielectrically insulating trench and having a height at least five times its width, said trench laterally separating two regions, and an epitaxial semiconductor layer, for example made of monocrystalline silicon, covering the cut trench.
  • the trenches make it possible to avoid the diffusion of dopants through them, or else provide galvanic isolation.
  • the trench must be narrow enough to allow the development of a homogeneous epitaxial layer over the entire surface of the semiconductor wafer.
  • the width of these trenches is less than 1 ⁇ m, and more preferably less than
  • the trenches can be more or less deep depending on the need for the semiconductor device produced within the substrate.
  • a trench can have a width equal to 0.2 microns, a height greater than 5 microns, and be buried at a depth of at least 0.8 microns.
  • the invention advantageously applies when there are at least three adjacent buried layers N, P and N or
  • the substrate comprises at least two buried trenches and at least three adjacent buried zones of alternating conductivity, each of these buried zones being separated laterally from that which is adjacent thereto by a trench.
  • the substrate can comprise substantially above the three buried zones of alternating conductivity, three epitaxial zones having respectively the same types of conductivity as the three buried zones, and the circuit can comprise two MOS transistors of the same kind produced in the two epitaxial zones having the same type of conductivity.
  • the circuit may comprise two MOS transistors of different nature, respectively produced in the two epitaxial zones having two different types of conductivity.
  • It may also further comprise a bipolar transistor produced in the third epitaxial zone.
  • a subject of the invention is also a method of manufacturing an integrated circuit, comprising producing in the semiconductor substrate the circuit of at least one buried, vertical, dielectrically insulating trench having a height at least five times greater than its width, said trench laterally separating two regions, and an epitaxial semiconductor layer covering said trench.
  • the two regions can have conductivities of different types obtained by implantation of dopants.
  • a) said trench is made in the substrate, b) on either side of the trench, by implantation, the two regions having the same type of conductivity or else two different types of conductivity, c) annealing is carried out, d) said epitaxial layer is grown by epitaxy on the structure obtained in step c).
  • the trench is preferably made before the implantation of dopants in the areas of the substrate intended to subsequently form the buried layers. Indeed, after this instant of the process, the heat balance is lower but there is less risk of diffusion of dopants from one layer to the other. However, it is possible to envisage engraving the trenches after implantation in specific cases which certain devices may require.
  • This implantation step is usually followed by annealing to diffuse the dopants in particular over a thickness preferably less than the depth of the trenches.
  • a first layer of monocrystalline silicon is then grown by epitaxy over the entire surface of the substrate.
  • the very small size of the trenches allows a growth of quasi-homogeneous monocrystalline silicon over the entire surface of the substrate.
  • zones of the same conductivity as those of the underlying buried layers can be formed and an annealing is advantageously carried out such that the dopant of this epitaxial zone is in continuity with that of the buried zone .
  • the trenches are filled with a dielectric material, preferably silicon oxide.
  • a dielectric material preferably silicon oxide.
  • Nitrided compounds could also be used, or else “insulating + conductive” compounds, such as, for example, silicon dioxide + polysilicon.
  • the method of the invention can advantageously be implemented for the production of contiguous MOS and / or bipolar transistors, in particular in BiCMOS and CMOS technologies.
  • the integrated circuit produced in accordance with the embodiments illustrated in FIGS. 1a to 1b comprises components requiring the contiguity of three buried layers, including a central unit of a first type of conductivity and two lateral panels of a second type of conductivity. It is understood that the invention is not limited to this scenario and includes in particular also the contiguity of two buried layers of different conductivity, or the contiguity of more than three buried layers.
  • the location of the different implantation zones of N or P type dopants, which will later constitute the buried layers, is determined beforehand and in a conventional manner on a semiconductor substrate 1, generally made of silicon.
  • trenches 2 are then etched at the location of the junctions between these different zones. These trenches 2 can be deep or shallow. Their size depends essentially on the subsequent implantation and the thickness of the buried layers, of the anneals, and therefore more generally of the component which it is desired to produce.
  • the width of the trenches 2 is an important parameter. Indeed, the trenches 2 must be wide enough so that on the one hand they can be produced technically and filled uniformly with a dielectric material, and on the other hand they can play their role of insulation between two layers of conductivity different. In addition, the trenches 2 must be sufficiently narrow to allow the growth over the entire surface of the wafer of a homogeneous epitaxial layer of monocrystalline silicon.
  • the width of the trenches 2 according to the method of the invention is preferably less than 1 ⁇ m and more preferably less than 0,3 ⁇ m. More particularly, according to a preferred implementation of the invention, the trenches 2 have a width of the order of 0.2 ⁇ m.
  • the trenches 2 are then filled with a dielectric material 3.
  • a dielectric material 3 Preferably, silicon oxide will be used as the insulation material in the trenches.
  • zones of different conductivity are then produced on either side of the trenches.
  • an area 5 of a first type of conductivity has been produced between the two trenches 2.
  • two zones 4 of a second type of conductivity have been produced. Doping of these areas is done in a conventional manner by ion implantation with appropriate dopants (for example).
  • the central zone is of conductivity P and the lateral zones, of conductivity N.
  • Zones 4 and 5 will constitute the buried layers of the semiconductor components produced. These buried layers could, for example, be collectors of bipolar transistors or even bottom receptacles for MOS transistors.
  • thermal annealing is generally carried out so that the implantation zones 4 and 5 extend in particular over the entire desired thickness and preferably over a thickness less than the depth of the trenches 2.
  • the insulating trenches are made before the implantation of the buried layers in order to avoid any diffusion of dopants from one zone to the other, in particular during the annealing step.
  • the zones of different conductivity are separated from each other by insulating trenches, as illustrated in FIG. 1b.
  • the lateral diffusions of zones 4 and 5 are limited.
  • the dopants in these different zones do not compensate for each other.
  • the heavily doped parts are no longer in contact with each other, as they were previously without the trenches.
  • a dielectric wall separates the buried heavily doped layers, which causes an increase in breakdown voltages and therefore better resistance of the semiconductor components produced.
  • the choice of the doping level now only depends on the nature of the components that one wishes to produce and respects their intrinsic functioning.
  • a first layer 6 of monocrystalline silicon is then grown by epitaxy on the whole wafer.
  • This layer 6 develops on the surface of the substrate 1 and of the trenches 2 by vertical and lateral epitaxial growth.
  • implantations are then carried out in this first epitaxial layer 6 and substantially above each of the zones produced in the previous step to form zones of the same conductivity.
  • layer 8 is of the first type of conductivity and layers 7 are of the second type of conductivity, in accordance with layers 5 and 4 respectively.
  • a thermal annealing is carried out so that the layers 7 and 8 extend in particular over the entire thickness of the epitaxial layer 6.
  • the dopings were carried out so that the central region 8 was doped P and the lateral regions 7 were doped N.
  • the doping of the epitaxial layer depends on the conductivity of the buried layers or of the semiconductor device to be produced. Reverse conductivity compared to the illustrated case also falls within the scope of the invention.
  • the semiconductor components are then produced in the epitaxial zones of different conductivity, according to the usual methods. By way of example, in no way limiting, one can envisage several types of semiconductor devices to be produced from the device illustrated in FIG. 1 d.
  • two PMOS transistors can be produced in the N 7 epitaxial zones.
  • the buried layers 4 doped
  • N then constitute the bottom taps of the boxes of these transistors.
  • the central zone P constitutes a separation zone of reverse conductivity.
  • a PMOS transistor in the same way on an epitaxial zone 7.
  • NPN bipolar transistor In which case the buried layers N 4 will respectively constitute the bottom socket of the MOS transistor and the collector of the bipolar transistor.
  • the P-doped central zone, consisting of layers 5 and 8, can then be used as a basis for producing an NMOS transistor.
  • junction 20 junction 20, and by deep dielectric isolation 3.
  • the method of the invention is particularly suitable for the production of MOS, CMOS or even technology transistors.
  • the semiconductor devices produced according to the method of the invention exhibit better breakdown resistance and there is immediate piercing of the buried layers considerably reduced, or even non-existent.
  • the invention also applies to power devices by allowing deep dielectric isolation.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

The invention concerns an integrated circuit semiconductor substrate comprising at least a dielectrically vertical buried trench and having a height at least five times more than its width, and an epitaxial semiconductor layer (6) covering said trench laterally separating two regions (4, 5). The invention is applicable to MOS, CMOS and BICMOS technologies. The invention also concerns a method for making said substrate.

Description

STRUCTURE D ISOLATION DE COUCHES ENTERREES PAR TRANCHEES ENTERREES , ET PROCEDE DE FABRICATIONINSULATING STRUCTURE OF BURIED LAYERS BY BURIED TRENCHES, AND MANUFACTURING METHOD
La présente invention concerne la fabrication de circuits intégrés. La présente invention est plus particulièrement appropriée pour la réalisation de dispositifs de type MOS ou MOS complémentaire ou la fabrication dans un même substrat semi conducteur de transistors de type bipolaire et de transistors de type MOS complémentaire (BiCMOS). Lors de la fabrication de composants de type bipolaire ou de type MOS , on procède tout d'abord par la réalisation dans le substrat semi conducteur, généralement en silicium, de couches enterrées qui ultérieurement joueront un rôle spécifique selon le composant réalisé. Ainsi les couches enterrées peuvent être notamment des collecteurs pour transistors bipolaires, ou encore des prises de fond de caisson pour les transistors MOS . Ces couches enterrées sont caractérisées par leur dopage de type P ou N afin de satisfaire les spécificités des composants que l'on souhaite réaliser (transistor bipolaire NPN ou PNP, transistor NMOS ou PMOS). Au sein d'un même dispositif semi conducteur, on peut rencontrer deux transistors MOS adjacents de conductivité différente (CMOS), deux transistors MOS voisins de même conductivité séparée par une zone de conductivité inverse, ainsi que des transistors MOS et des transistors bipolaires (BiCMOS).The present invention relates to the manufacture of integrated circuits. The present invention is more particularly suitable for the production of devices of the MOS or complementary MOS type or the manufacture, in the same semiconductor substrate, of bipolar type transistors and of transistors of complementary MOS type (BiCMOS). When manufacturing bipolar or MOS type components, the first step is to produce buried layers in the semiconductor substrate, generally made of silicon, which will later play a specific role depending on the component produced. Thus the buried layers may in particular be collectors for bipolar transistors, or even bottom receptacles for MOS transistors. These buried layers are characterized by their P or N type doping in order to satisfy the specificities of the components that one wishes to produce (bipolar NPN or PNP transistor, NMOS or PMOS transistor). Within the same semiconductor device, two adjacent MOS transistors of different conductivity (CMOS) can be encountered, two neighboring MOS transistors of the same conductivity separated by a zone of reverse conductivity, as well as MOS transistors and bipolar transistors (BiCMOS ).
Bien qu' étant des éléments constitutifs de composants distincts , les couches enterrées, au sein d'un même substrat, ne peuvent pas être dopées de manière indépendante les unes des autres. En effet, les niveaux de dopage des couches enterrées définissent notamment des phénomènes parasites comme les tensions de claquage entre couches de type P et N, ainsi que les tensions de perçage entre couches de même type de conductivité.Although being constituent elements of distinct components, the buried layers, within the same substrate, cannot be doped independently of each other. In fact, the doping levels of the buried layers define in particular parasitic phenomena such as the breakdown voltages between layers of type P and N, as well as the drilling voltages between layers of the same type of conductivity.
Ainsi, par exemple, la tension de claquage entre deux couches de conductivités inverses est d'autant plus faible que le gradient de dopage entre ces couches est plus fort. Ceci est généralement le cas lorsque les couches enterrées sont fortement dopées. Par ailleurs, le risque de perçage entre couches enterrées de même type, est d'autant plus grand que la distance séparant les deux couches est réduite. La zone de séparation de conductivité inverse, non fortement dopée et devenant de plus en plus étroite, ne peut plus jouer son rôle d'isolant entre les deux couches enterrées de même nature. La miniaturisation des circuits intégrés entraîne nécessairement une augmentation de ce risque.Thus, for example, the breakdown voltage between two layers of reverse conductivities is lower the higher the doping gradient between these layers. This is generally the case when the buried layers are heavily doped. Furthermore, the risk of drilling between buried layers of the same type, is all the greater as the distance separating the two layers is reduced. The separation zone of reverse conductivity, not strongly doped and becoming increasingly narrow, can no longer play its role of insulator between the two buried layers of the same nature. The miniaturization of integrated circuits necessarily leads to an increase in this risk.
On pourrait envisager, pour remédier au problème du perçage, de diminuer le niveau de dopage des couches de même nature et d'augmenter celui des couches de conductivité inverse qui les séparent. Ceci aurait notamment pour conséquence de limiter la diffusion des dopants des couches fortement dopées vers les couches faiblement dopées isolantes. Or, la modification des niveaux de dopage des couches enterrées modifierait également le fonctionnement intrinsèque des dispositifs que l'on souhaite. En outre, si l'on augmente le dopage des couches de séparation, on risque également d'abaisser les tensions de claquage.One could envisage, to remedy the problem of drilling, to decrease the level of doping of the layers of the same nature and to increase that of the layers of reverse conductivity which separate them. This would in particular have the consequence of limiting the diffusion of dopants from the heavily doped layers towards the weakly doped insulating layers. However, the modification of the doping levels of the buried layers would also modify the intrinsic functioning of the devices that are desired. In addition, if the doping of the separation layers is increased, there is also a risk of lowering the breakdown voltages.
Avec la réduction des dimensions des composants et circuits intégrés, il sera de plus en plus complexe d'obtenir un compromis satisfaisant entre le fonctionnement intrinsèque des dispositifs et leur isolation.With the reduction of the dimensions of the components and integrated circuits, it will be increasingly complex to obtain a satisfactory compromise between the intrinsic functioning of the devices and their insulation.
Il existe donc un besoin de surmonter ces phénomènes parasitaires générés par la proximité des composants, et notamment la contiguïté des couches enterrées. Plus particulièrement, il apparaît nécessaire de proposer des solutions pour minimiser, voire éviter, le risque de perçage des couches enterrées, ainsi que l'abaissement des tensions de claquage tout en préservant le bon fonctionnement intrinsèque des composants réalisés. La demanderesse propose une solution qui permet de remédier à ces problèmes.There is therefore a need to overcome these parasitic phenomena generated by the proximity of the components, and in particular the contiguity of the buried layers. More particularly, it appears necessary to propose solutions to minimize, or even avoid, the risk of piercing the buried layers, as well as the lowering of the breakdown voltages while preserving the proper intrinsic functioning of the components produced. The applicant proposes a solution which makes it possible to remedy these problems.
L'invention consiste essentiellement en la formation de tranchées enterrées isolant latéralement les unes des autres, les couches enterrées de conductivités identiques ou différentes. On constate notamment que l'on peut éviter le perçage immédiat des couches enterrées par l'ajout dans le substrat semi conducteur de telles tranchées entre les couches. Ces tranchées sont positionnées de manière à séparer les unes des autres les couches enterrées de conductivité différente ou identique. Ces tranchées font obstacle à la diffusion des dopants d'une couche enterrée vers l'autre, réduisant également le risque d'abaissement de la tension de claquage.The invention essentially consists in the formation of buried trenches isolating laterally from each other, the buried layers of identical or different conductivities. We notes in particular that it is possible to avoid the immediate drilling of the buried layers by the addition in the semiconductor substrate of such trenches between the layers. These trenches are positioned so as to separate the buried layers of different or identical conductivity from each other. These trenches prevent the diffusion of dopants from one buried layer to the other, also reducing the risk of lowering the breakdown voltage.
Le bon fonctionnement intrinsèque des composants est assuré du fait d'un dopage indépendant des couches enterrées du dispositif. L' invention propose ainsi un circuit intégré, comprenant un substrat semiconducteur, par exemple en silicium, comportant au moins une tranchée enterrée, verticale, diélectriquement isolante et ayant une hauteur au moins cinq fois supérieure à sa largeur, ladite tranchée séparant latéralement deux régions, et une couche semiconductrice épitaxiale, par exemple en silicium monocristallin, recouvrant ladi te tranchée.The intrinsic correct functioning of the components is ensured due to independent doping of the buried layers of the device. The invention thus provides an integrated circuit, comprising a semiconductor substrate, for example made of silicon, comprising at least one buried, vertical, dielectrically insulating trench and having a height at least five times its width, said trench laterally separating two regions, and an epitaxial semiconductor layer, for example made of monocrystalline silicon, covering the cut trench.
Les tranchées permettent d' éviter la diffusion de dopants à travers elles, ou bien assurent une isolation galvanique.The trenches make it possible to avoid the diffusion of dopants through them, or else provide galvanic isolation.
La tranchée doit être suffisamment étroite pour permettre le développement d'une couche épitaxiée homogène sur la totalité de la surface de la plaquette semiconductrice. De préférence, la largeur de ces tranchées est inférieure à lμm, et encore de préférence inférieure àThe trench must be narrow enough to allow the development of a homogeneous epitaxial layer over the entire surface of the semiconductor wafer. Preferably, the width of these trenches is less than 1 μm, and more preferably less than
0,3μm, et plus particulièrement de l'ordre de 0,2μm.0.3 μm, and more particularly of the order of 0.2 μm.
Les tranchées peuvent être plus ou moins profondes selon la nécessité du dispositif semiconducteur réalisé au sein du substrat.The trenches can be more or less deep depending on the need for the semiconductor device produced within the substrate.
A titre indicatif, une tranchée peut avoir une largeur égale à 0,2 microns, une hauteur supérieure à 5 microns, et être enterrée à une profondeur d' au moins 0,8 microns.As an indication, a trench can have a width equal to 0.2 microns, a height greater than 5 microns, and be buried at a depth of at least 0.8 microns.
L'invention s' applique avantageusement lorsque l'on est en présence d'au moins trois couches enterrées adjacentes N, P et N ouThe invention advantageously applies when there are at least three adjacent buried layers N, P and N or
P, N et P, notamment lorsque l'on souhaite réaliser deux transistors MOS de même nature dont les couches enterrées sont séparées par une zone de conductivité inverse ou encore dans le cas d'une technologie BiCMOS . En effet, dans ce cas de figure, le risque de perçage immédiat des couches enterrées peut être important. La réalisation de tranchées étroites pour isoler latéralement les couches enterrées les unes des autres, permet de fortement réduire, voire d'éliminer ce risque. Ainsi, selon un mode de réalisation, le substrat comporte au moins deux tranchées enterrées et au moins trois zones enterrées adj acentes de conductivité alternée, chacune de ces zones enterrée étant séparée latéralement de celle qui lui est adj acente par une tranchée. Le substrat peut comporter sensiblement au-dessus des trois zones enterrées de conductivité alternée, trois zones épitaxiales ayant respectivement les mêmes types de conductivité que les trois zones enterrées, et le circuit peut comporter deux transistors MOS de même nature réalisés dans les deux zones épitaxiales ayant le même type de conductivité.P, N and P, in particular when it is desired to produce two MOS transistors of the same nature, the buried layers of which are separated by a zone of reverse conductivity or even in the case of a BiCMOS technology. In this case, the risk of piercing immediate buried layers can be important. The realization of narrow trenches to laterally isolate the buried layers from each other, greatly reduces or even eliminates this risk. Thus, according to one embodiment, the substrate comprises at least two buried trenches and at least three adjacent buried zones of alternating conductivity, each of these buried zones being separated laterally from that which is adjacent thereto by a trench. The substrate can comprise substantially above the three buried zones of alternating conductivity, three epitaxial zones having respectively the same types of conductivity as the three buried zones, and the circuit can comprise two MOS transistors of the same kind produced in the two epitaxial zones having the same type of conductivity.
En variante, le circuit peut comporter deux transistors MOS de nature différente, respectivement réalisés dans les deux zones épitaxiales ayant deux types de conductivité différents.As a variant, the circuit may comprise two MOS transistors of different nature, respectively produced in the two epitaxial zones having two different types of conductivity.
Il peut également comporter en outre un transistor bipolaire réalisé dans la troisième zone épitaxiale.It may also further comprise a bipolar transistor produced in the third epitaxial zone.
L'invention a également pour objet, un procédé de fabrication d'un circuit intégré, comprenant la réalisation dans le substrat semiconducteur du circuit d' au moins une tranchée enterrée, verticale, diélectriquement isolante et ayant une hauteur au moins cinq fois supérieure à sa largeur, ladite tranchée séparant latéralement deux régions, et d' une couche semiconductrice épitaxiale recouvrant ladite tranchée.A subject of the invention is also a method of manufacturing an integrated circuit, comprising producing in the semiconductor substrate the circuit of at least one buried, vertical, dielectrically insulating trench having a height at least five times greater than its width, said trench laterally separating two regions, and an epitaxial semiconductor layer covering said trench.
Les deux régions peuvent avoir des conductivités de type différent obtenues par implantation de dopants. Selon un mode de mise en œuvre, a) on réalise ladite tranchée dans le substrat, b) on forme de part et d' autre de la tranchée, par implantation, les deux régions ayant le même type de conductivité ou bien deux types différents de conductivité, c) on procède à un recuit, d) on fait croître par épitaxie ladite couche épitaxiale sur la structure obtenue à l'étape c) .The two regions can have conductivities of different types obtained by implantation of dopants. According to one mode of implementation, a) said trench is made in the substrate, b) on either side of the trench, by implantation, the two regions having the same type of conductivity or else two different types of conductivity, c) annealing is carried out, d) said epitaxial layer is grown by epitaxy on the structure obtained in step c).
La réalisation de la tranchée se fait préférentiellement avant l'implantation de dopants dans les zones du substrat destinées à former ultérieurement les couches enterrées. En effet, après cet instant du procédé, le bilan thermique est plus faible mais il y a moins de risque de diffusion de dopants d'une couche vers l'autre. Mais on peut envisager de graver les tranchées après implantation dans des cas spécifiques que pourraient requérir certains dispositifs.The trench is preferably made before the implantation of dopants in the areas of the substrate intended to subsequently form the buried layers. Indeed, after this instant of the process, the heat balance is lower but there is less risk of diffusion of dopants from one layer to the other. However, it is possible to envisage engraving the trenches after implantation in specific cases which certain devices may require.
Cette étape d'implantation est habituellement suivie d'un recuit pour diffuser les dopants en particulier sur une épaisseur de préférence inférieure à la profondeur des tranchées.This implantation step is usually followed by annealing to diffuse the dopants in particular over a thickness preferably less than the depth of the trenches.
Selon un mode de mise en oeuvre, on fait croître ensuite par épitaxie une première couche de silicium monocristallin sur toute la surface du substrat. La très faible dimension des tranchées permet une croissance de silicium monocristallin quasi-homogène sur toute la surface du substrat.According to one embodiment, a first layer of monocrystalline silicon is then grown by epitaxy over the entire surface of the substrate. The very small size of the trenches allows a growth of quasi-homogeneous monocrystalline silicon over the entire surface of the substrate.
Dans cette couche épitaxiale de silicium monocristallin, on peut former des zones de même conductivité que celles des couches enterrées sous-jacentes et l'on procède avantageusement à un recuit tel que le dopant de cette zone épitaxiale soit en continuité avec celui de la zone enterrée.In this epitaxial layer of monocrystalline silicon, zones of the same conductivity as those of the underlying buried layers can be formed and an annealing is advantageously carried out such that the dopant of this epitaxial zone is in continuity with that of the buried zone .
Selon un mode de mise en œuvre, préalablement à l'étape b), on remplit les tranchées avec un matériau diélectrique, de préférence l'oxyde de silicium. On pourrait également utili ser des composés nitrurés, ou bien des composés « isolant + conducteur », comme par exemple du dioxyde de silicium- + du polysilicium.According to one embodiment, prior to step b), the trenches are filled with a dielectric material, preferably silicon oxide. Nitrided compounds could also be used, or else “insulating + conductive” compounds, such as, for example, silicon dioxide + polysilicon.
Le procédé de l'invention peut avantageusement être mis en œuvre pour la réalisation de transistors MOS et/ou bipolaires contigus, notamment dans les technologies BiCMOS et CMOS.The method of the invention can advantageously be implemented for the production of contiguous MOS and / or bipolar transistors, in particular in BiCMOS and CMOS technologies.
La suite de la description se r.éfère aux figures annexées, respectivement les figures la à ld, qui représentent schématiquement les étapes principales de modes de mise en oeuvre particuliers du procédé de réalisation d'un dispositif semi conducteur intégrant des tranchées étroites enterrées selon l'invention. Ces modes de réalisation particuliers ne sont nullement limitatifs du procédé de l'invention.The remainder of the description refers to the appended figures, respectively figures la to ld, which schematically represent the main steps of particular embodiments of the process for producing a semiconductor device incorporating narrow buried trenches according to the invention. These particular embodiments are in no way limitative of the process of the invention.
Le circuit intégré réalisé conformément aux modes de réalisation illustrés par les figure la à lb, comporte des composants nécessitant la contiguïté de trois couches enterrées, dont une centrale d'un premier type de conductivité et deux latérales d'un deuxième type de conductivité. Il est bien entendu que l'invention ne se limite pas à ce cas de figure et englobe notamment également la contiguïté de deux couches enterrées de conductivité différente, ou encore la contiguïté de plus de trois couches enterrées.The integrated circuit produced in accordance with the embodiments illustrated in FIGS. 1a to 1b, comprises components requiring the contiguity of three buried layers, including a central unit of a first type of conductivity and two lateral panels of a second type of conductivity. It is understood that the invention is not limited to this scenario and includes in particular also the contiguity of two buried layers of different conductivity, or the contiguity of more than three buried layers.
Selon le procédé de l'invention, on détermine préalablement et de manière classique sur un substrat semi conducteur 1 , généralement en silicium, l' emplacement des différentes zones d'implantation de dopants de type N ou P, qui constitueront ultérieurement les couches enterrées.According to the method of the invention, the location of the different implantation zones of N or P type dopants, which will later constitute the buried layers, is determined beforehand and in a conventional manner on a semiconductor substrate 1, generally made of silicon.
Selon une mise en œuvre préférentielle du procédé de l'invention, et comme l'illustre la figure la, on grave ensuite des tranchées 2 à l'emplacement des jonctions entre ces différentes zones. Ces tranchées 2 peuvent être profondes ou peu profondes. Leur taille dépend essentiellement de l'implantation ultérieure et de l'épaisseur des couches enterrées, des recuits, et donc plus généralement du composant que l'on souhaite réaliser.According to a preferred implementation of the method of the invention, and as illustrated in FIG. 1a, trenches 2 are then etched at the location of the junctions between these different zones. These trenches 2 can be deep or shallow. Their size depends essentially on the subsequent implantation and the thickness of the buried layers, of the anneals, and therefore more generally of the component which it is desired to produce.
Si leur profondeur peut être variable, la largeur des tranchées 2 constitue un paramètre important. En effet, les tranchées 2 doi vent être suffisamment larges pour que d'une part elles puissent être réalisées techniquement et remplies de façon uniforme avec un matériau diélectrique, et d'autre part elles puissent jouer leur rôle d'isolation entre deux couches de conductivité différente. En outre, les tranchées 2 doivent être suffisamment étroites pour permettre la croissance sur la totalité de la surface de la plaquette d'une couche épitaxiale homogène de silicium monocristallin.If their depth can be variable, the width of the trenches 2 is an important parameter. Indeed, the trenches 2 must be wide enough so that on the one hand they can be produced technically and filled uniformly with a dielectric material, and on the other hand they can play their role of insulation between two layers of conductivity different. In addition, the trenches 2 must be sufficiently narrow to allow the growth over the entire surface of the wafer of a homogeneous epitaxial layer of monocrystalline silicon.
La largeur des tranchées 2 selon le procédé de l'invention est de préférence inférieure à lμm et encore de préférence inférieure à 0,3μm. Plus particulièrement, selon une mise en œuvre préférentielle de l'invention, les tranchées 2 ont une largeur de l'ordre de 0,2μm.The width of the trenches 2 according to the method of the invention is preferably less than 1 μm and more preferably less than 0,3μm. More particularly, according to a preferred implementation of the invention, the trenches 2 have a width of the order of 0.2 μm.
Les tranchées 2 sont ensuite remplies avec un matériau diélectrique 3. On utilisera de préférence de l'oxyde de silicium comme matériau d'isolation dans les tranchées.The trenches 2 are then filled with a dielectric material 3. Preferably, silicon oxide will be used as the insulation material in the trenches.
Comme l'illustre la figure lb, on réalise ensuite de part et d'autre des tranchées des zones de conductivité différente. Dans le dispositif illustré à la figure lb, on a réalisé entre les deux tranchées 2 une zone 5 d'un premier type de conductivité. De l'autre côté des tranchées 2, ou encore à l'extérieur des tranchées 2, on a réalisé deux zones 4 d'un deuxième type de conductivité. Le dopage de ces zones se fait de façon classique par implantation ionique avec des dopants appropriés (par exemple).As illustrated in FIG. 1b, zones of different conductivity are then produced on either side of the trenches. In the device illustrated in FIG. 1b, an area 5 of a first type of conductivity has been produced between the two trenches 2. On the other side of the trenches 2, or even outside of the trenches 2, two zones 4 of a second type of conductivity have been produced. Doping of these areas is done in a conventional manner by ion implantation with appropriate dopants (for example).
D'après la figure lb, la zone centrale est de conductivité P et les zones latérales, de conductivité N. Une conductivité inverse de ces zones entre également dans le cadre du procédé de l'invention. Les zones 4 et 5 constitueront les couches enterrées des composants semi conducteurs réalisés. Ces couches enterrées pourront être par exemple des collecteurs de transistors bipolaires ou encore des prises de fond de caisson pour les transistors MOS .According to FIG. 1b, the central zone is of conductivity P and the lateral zones, of conductivity N. A reverse conductivity of these zones is also part of the process of the invention. Zones 4 and 5 will constitute the buried layers of the semiconductor components produced. These buried layers could, for example, be collectors of bipolar transistors or even bottom receptacles for MOS transistors.
Après le dopage, on procède généralement à un recuit thermique pour que les zones d'implantation 4 et 5, s'étendent en particulier sur toute l'épaisseur souhaitée et de préférence sur une épaisseur inférieure à la profondeur des tranchées 2. Selon une mise en œuvre préférentielle de l'invention, on réalise les tranchées isolantes avant l'implantation des couches enterrées afin d'éviter toute diffusion de dopants d'une zone à l'autre notamment pendant l'étape de recuit.After doping, thermal annealing is generally carried out so that the implantation zones 4 and 5 extend in particular over the entire desired thickness and preferably over a thickness less than the depth of the trenches 2. According to a setting in the preferred embodiment of the invention, the insulating trenches are made before the implantation of the buried layers in order to avoid any diffusion of dopants from one zone to the other, in particular during the annealing step.
À ce stade du procédé de l'invention, les zones de différente conductivité sont séparées les unes des autres par des tranchées isolantes, comme l'illustre la figure lb. Les diffusions latérales des zones 4 et 5 sont limitées. Les dopants de ces différentes zones ne se compensent pas. En outre, les parties fortement dopées ne sont plus en contact les unes avec les autres, comme elles l'étaient précédemment sans les tranchées. Un mur diélectrique sépare les couches enterrées fortement dopées ce qui entraîne une augmentation des tensions de claquage et donc une meilleure tenue des composants semi conducteurs réalisés. Par ailleurs, selon le procédé de l'invention, il est maintenant possible de doper les couches enterrées indépendamment les unes des autres, ce qui rajoute un degré de liberté supplémentaire dans la réalisation des composants. En effet, le choix du niveau de dopage ne dépend plus maintenant que de la nature des composants que l'on souhaite réaliser et respecte leur fonctionnement intrinsèque.At this stage of the process of the invention, the zones of different conductivity are separated from each other by insulating trenches, as illustrated in FIG. 1b. The lateral diffusions of zones 4 and 5 are limited. The dopants in these different zones do not compensate for each other. In addition, the heavily doped parts are no longer in contact with each other, as they were previously without the trenches. A dielectric wall separates the buried heavily doped layers, which causes an increase in breakdown voltages and therefore better resistance of the semiconductor components produced. Furthermore, according to the method of the invention, it is now possible to boost the buried layers independently of each other, which adds an additional degree of freedom in the production of the components. In fact, the choice of the doping level now only depends on the nature of the components that one wishes to produce and respects their intrinsic functioning.
On fait croître ensuite par épitaxie sur toute la plaquette une première couche 6 de silicium monocristallin. Cette couche 6 se développe sur la surface du substrat 1 et des tranchées 2 par croissance épitaxiale verticale et latérale. Comme illustré à la figure le, on réalise ensuite des implantations dans cette première couche épitaxiale 6 et sensiblement au-dessus de chacune des zones réalisées dans l'étape précédente pour former des zones de même conductivité. Ainsi la couche 8 est du premier type de conductivité et les couches 7 sont du deuxième type de conductivité, conformément aux couches 5 et 4 respectivement.A first layer 6 of monocrystalline silicon is then grown by epitaxy on the whole wafer. This layer 6 develops on the surface of the substrate 1 and of the trenches 2 by vertical and lateral epitaxial growth. As illustrated in FIG. 1a, implantations are then carried out in this first epitaxial layer 6 and substantially above each of the zones produced in the previous step to form zones of the same conductivity. Thus layer 8 is of the first type of conductivity and layers 7 are of the second type of conductivity, in accordance with layers 5 and 4 respectively.
Après cette implantation, on procède à un recuit thermique pour que les couches 7 et 8 s'étendent en particulier sur toute l'épaisseur de la couche épitaxiale 6.After this implantation, a thermal annealing is carried out so that the layers 7 and 8 extend in particular over the entire thickness of the epitaxial layer 6.
Comme illustrés à la figure ld, les dopages ont été effectués pour que la région centrale 8 soit dopée P et les régions latérales 7 soient dopées N. Le dopage de la couche épitaxiale dépend de la conductivité des couches enterrées ou du dispositif semiconducteur à réaliser. Une conductivité inverse par rapport au cas de figure illustré entre également dans le cadre de l'invention. Selon le procédé de l'invention, on réalise ensuite dans les zones épitaxiales de conductivité différentes, les composants semi conducteurs souhaités selon les procédés habituels. À titre d'exemple, nullement limitatif, on peut envisager plusieurs types de dispositifs semi conducteurs à réaliser à partir du dispositif illustré à la figure l d.As illustrated in FIG. 1d, the dopings were carried out so that the central region 8 was doped P and the lateral regions 7 were doped N. The doping of the epitaxial layer depends on the conductivity of the buried layers or of the semiconductor device to be produced. Reverse conductivity compared to the illustrated case also falls within the scope of the invention. According to the method of the invention, the semiconductor components are then produced in the epitaxial zones of different conductivity, according to the usual methods. By way of example, in no way limiting, one can envisage several types of semiconductor devices to be produced from the device illustrated in FIG. 1 d.
Selon une première variante, on peut réaliser deux transistors PMOS dans les zones épitaxiales N 7. Les couches enterrées 4 dopéesAccording to a first variant, two PMOS transistors can be produced in the N 7 epitaxial zones. The buried layers 4 doped
N constituent alors les prises de fond des caissons de ces transistors.N then constitute the bottom taps of the boxes of these transistors.
La zone P centrale constitue une zone de séparation de conductivité inverse.The central zone P constitutes a separation zone of reverse conductivity.
Selon une autre variante, on peut envisager de réaliser de la même manière sur une zone épitaxiale 7 un transistor PMOS . Sur l'autre zone épitaxiale 7 dopée N, on peut envisager de réaliser un transistor bipolaire NPN. Auquel cas les couches enterrées N 4 constitueront respectivement la prise de fond de caisson du transistor MOS et le collecteur du transistor bipolaire. La zone centrale dopée P, constituée des couches 5 et 8, peut alors servir de base à la réalisation d'un transistor NMOS .According to another variant, it is possible to envisage producing a PMOS transistor in the same way on an epitaxial zone 7. On the other N-doped epitaxial zone 7, it is possible to envisage making an NPN bipolar transistor. In which case the buried layers N 4 will respectively constitute the bottom socket of the MOS transistor and the collector of the bipolar transistor. The P-doped central zone, consisting of layers 5 and 8, can then be used as a basis for producing an NMOS transistor.
Ces différents dispositifs sont isolés les uns des autres par jonction 20, et par isolation diélectrique en profondeur 3.These different devices are isolated from each other by junction 20, and by deep dielectric isolation 3.
Le procédé de l'invention est particulièrement approprié à la réalisation de transistors de technologie MOS , CMOS ou encoreThe method of the invention is particularly suitable for the production of MOS, CMOS or even technology transistors.
BICMOS .BICMOS.
Les dispositifs semi conducteurs réalisés selon le procédé de l'invention présentent une meilleure tenue au claquage et l'on observe un perçage immédiat des couches enterrées considérablement réduit, voire inexistant.The semiconductor devices produced according to the method of the invention exhibit better breakdown resistance and there is immediate piercing of the buried layers considerably reduced, or even non-existent.
L' invention s' applique également aux dispositifs de puisssance en permettant une isolation diélectrique en profondeur.The invention also applies to power devices by allowing deep dielectric isolation.
Elle s' applique également aux dispositifs capteurs en permettant une élimination des courants de fuite latéraux des jonctions profondes. It also applies to sensor devices by allowing elimination of lateral leakage currents from deep junctions.

Claims

REVENDICATIONS
1. Circuit intégré, comprenant un substrat semiconducteur, caractérisé par le fait que le substrat semiconducteur comporte au moins une tranchée (2) enterrée, verticale, diélectriquement isolante et ayant une hauteur au moins cinq fois supérieure à sa largeur, ladite tranchée séparant latéralement deux régions (4, 5), et une couche semiconductrice épitaxiale recouvrant ladite tranchée.1. Integrated circuit, comprising a semiconductor substrate, characterized in that the semiconductor substrate comprises at least one buried trench (2), vertical, dielectrically insulating and having a height at least five times greater than its width, said trench laterally separating two regions (4, 5), and an epitaxial semiconductor layer covering said trench.
2. Circuit selon la revendication 1 , caractérisé par le fait que les deux régions (4,5) ont des conductivités de type différent.2. Circuit according to claim 1, characterized in that the two regions (4,5) have conductivities of different type.
3. Circuit selon l' une des revendications précédentes, caractérisé par le fait que le substrat est formé de silicium monocristallin.3. Circuit according to one of the preceding claims, characterized in that the substrate is formed of monocrystalline silicon.
4. Circuit selon l' une des revendications précédentes, caractérisé par le fait que la largeur de la tranchée est inférieure à 0,3 microns.4. Circuit according to one of the preceding claims, characterized in that the width of the trench is less than 0.3 microns.
5. Circuit selon la revendication 4, caractérisé par le fait que la tranchée a une largeur égale à 0,2 microns, une hauteur supérieure à 5 microns, et par le fait qu' elle est enterrée à une profondeur d' au moins 0,8 microns.5. Circuit according to claim 4, characterized by the fact that the trench has a width equal to 0.2 microns, a height greater than 5 microns, and by the fact that it is buried at a depth of at least 0, 8 microns.
6. Circui t selon l' une des revendications précédentes, caractérisé par le fait que le substrat comporte au moins deux tranchées enterrées (2) et au moins trois zones enterrées adjacentes de conductivité alternée (4 et 5), chacune de ces zones enterrée étant séparée latéralement de celle qui lui est adj acente par une tranchée (2).6. Circui t according to one of the preceding claims, characterized in that the substrate comprises at least two buried trenches (2) and at least three adjacent buried zones of alternating conductivity (4 and 5), each of these buried zones being laterally separated from that adjoining it by a trench (2).
7. Circuit selon la revendication 6, caractérisé par le fait que le substrat comporte sensiblement au-dessus des trois zones enterrées de conductivité alternée (4 et 5), trois zones épitaxiales (7 et 8) ayant respectivement les mêmes types de conductivité que les trois zones enterrées, et par le fait que le circuit comporte deux transistors MOS de même nature réalisés dans les deux zones épitaxiales (7) ayant le même type de conductivité. 7. Circuit according to claim 6, characterized in that the substrate comprises substantially above the three buried zones of alternating conductivity (4 and 5), three epitaxial zones (7 and 8) having respectively the same types of conductivity as the three buried zones, and by the fact that the circuit comprises two MOS transistors of the same kind produced in the two epitaxial zones (7) having the same type of conductivity.
8. Circuit selon la revendication 6, caractérisé par le fait que le substrat comporte sensiblement au-dessus des trois zones enterrées de conductivité alternée (4 et 5), trois zones épitaxiales (7 et 8) ayant respectivement les mêmes types de conductivité que les trois zones enterrées, et par le fait que le circuit comporte deux transistors MOS de nature différente, respectivement réalisés dans les deux zones épitaxiales (7 , 8) ayant deux types de conductivité différents.8. Circuit according to claim 6, characterized in that the substrate comprises substantially above the three buried zones of alternating conductivity (4 and 5), three epitaxial zones (7 and 8) having respectively the same types of conductivity as the three buried zones, and by the fact that the circuit comprises two MOS transistors of different nature, respectively produced in the two epitaxial zones (7, 8) having two different types of conductivity.
9. Circuit selon la revendication 8, caractérisé par le fait qu' il comporte en outre un transistor bipolaire réalisé dans la troisième zone épitaxiale (7).9. Circuit according to claim 8, characterized in that it further comprises a bipolar transistor produced in the third epitaxial zone (7).
10. Procédé de fabrication d' un circuit intégré, caractérisé par le fait qu' il comprend la réalisation dans le substrat semiconducteur du circuit d' au moins une tranchée (2) enterrée, verticale, diélectriquement isolante et ayant une hauteur au moins cinq fois supérieure à sa largeur, ladite tranchée séparant latéralement deux régions (4, 5), et d' une couche semiconductrice épitaxiale recouvrant ladite tranchée.10. A method of manufacturing an integrated circuit, characterized in that it comprises the production in the semiconductor substrate of the circuit of at least one buried trench (2), vertical, dielectrically insulating and having a height at least five times greater than its width, said trench laterally separating two regions (4, 5), and of an epitaxial semiconductor layer covering said trench.
1 1. Procédé selon la revendication 10, caractérisé par le fait que les deux régions (4,5) ont des conductivités de type différent obtenues par implantation de dopants.1 1. Method according to claim 10, characterized in that the two regions (4,5) have conductivities of different type obtained by implantation of dopants.
12. Procédé selon l ' une des revendications 10 ou 11 , caractérisé par le fait que la largeur de la tranchée est inférieure à 0,3 microns.12. Method according to one of claims 10 or 11, characterized in that the width of the trench is less than 0.3 microns.
13. Procédé selon l' une des revendications 10 à 12, caractérisé par le fait que le substrat étant en silicium, a) on réalise ladite tranchée (2) dans le substrat, b) on forme de part et d' autre de la tranchée, par implantation, les deux régions (4,5) ayant le même type de conductivité ou bien deux types différents de conductivité, c) on procède à un recuit, d) on fait croître par épitaxie ladite couche épitaxiale sur la structure obtenue à l'étape c). 13. Method according to one of claims 10 to 12, characterized in that the substrate being made of silicon, a) said trench (2) is made in the substrate, b) it is formed on either side of the trench , by implantation, the two regions (4,5) having the same type of conductivity or else two different types of conductivity, c) annealing is carried out, d) said epitaxial layer is grown by epitaxy on the structure obtained at l 'step c).
14. Procédé selon la revendication 13, caractérisé par le fait que préalablement à l'étape b), on remplit les tranchées avec un matériau diélectrique, de préférence l'oxyde de silicium.14. The method of claim 13, characterized in that prior to step b), the trenches are filled with a dielectric material, preferably silicon oxide.
15. Procédé selon l' une des revendications 10 à 14, caractérisé par le fait qu' on réalise dans le substrat au moins deux tranchées enterrées (2) et au moins trois zones enterrées adjacentes de conductivité alternée (4 et 5), chacune de ces zones enterrée étant séparée latéralement de celle qui lui est adjacente par une tranchée (2), par le fait qu' on réalise dans la couche épitaxiale, sensiblement au- dessus des trois zones enterrées de conductivité alternée (4 et 5), trois zones épitaxiales (7 et 8) ayant respectivement les mêmes types de conductivité que les trois zones enterrées.15. Method according to one of claims 10 to 14, characterized in that one carries out in the substrate at least two buried trenches (2) and at least three adjacent buried zones of alternating conductivity (4 and 5), each of these buried zones being separated laterally from that which is adjacent to it by a trench (2), by the fact that there are formed in the epitaxial layer, substantially above the three buried zones of alternating conductivity (4 and 5), three zones epitaxial (7 and 8) respectively having the same types of conductivity as the three buried zones.
16. Procédé selon la revendication 15, caractérisé par le fait qu' on réalise deux transistors MOS de même nature dans les deux zones épitaxiales (7) ayant le même type de conductivité.16. Method according to claim 15, characterized in that two MOS transistors of the same kind are produced in the two epitaxial zones (7) having the same type of conductivity.
17.' Procédé selon la revendication 15, caractérisé par le fait qu' on réalise deux transistors MOS de nature différente, respectivement dans les deux zones épitaxiales (7, 8) ayant deux types de conductivité différents. 17. ' Method according to claim 15, characterized in that two MOS transistors of different nature are produced, respectively in the two epitaxial zones (7, 8) having two different types of conductivity.
18. Procédé selon la revendication 17, caractérisé par le fait qu' on réalise en outre un transistor bipolaire dans la troisième zone épitaxiale (7). 18. Method according to claim 17, characterized in that a bipolar transistor is further produced in the third epitaxial zone (7).
EP02710091A 2001-01-12 2002-01-09 Insulating structures of buried layers with buried trenches and method for making same Withdrawn EP1352420A1 (en)

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FR0100412A FR2819629B1 (en) 2001-01-12 2001-01-12 INTEGRATED CIRCUIT WITH REDUCED PIERCING RISK BETWEEN BURIED LAYERS, AND MANUFACTURING PROCESS
FR0100412 2001-01-12
PCT/FR2002/000055 WO2002056363A1 (en) 2001-01-12 2002-01-09 Insulating structures of buried layers with buried trenches and method for making same

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FR2819629B1 (en) 2003-07-04
WO2002056363A1 (en) 2002-07-18

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