EP1239616B1 - Method and System for demodulating an RDS-Signal - Google Patents

Method and System for demodulating an RDS-Signal Download PDF

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Publication number
EP1239616B1
EP1239616B1 EP20020003953 EP02003953A EP1239616B1 EP 1239616 B1 EP1239616 B1 EP 1239616B1 EP 20020003953 EP20020003953 EP 20020003953 EP 02003953 A EP02003953 A EP 02003953A EP 1239616 B1 EP1239616 B1 EP 1239616B1
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Prior art keywords
signal
input
rds
output
oscillator
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EP20020003953
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German (de)
French (fr)
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EP1239616A2 (en
EP1239616A3 (en
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Stefan Dr.-Ing. Gierl
Christoph Dipl.-Ing. Benz
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Harman Becker Automotive Systems GmbH
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Harman Becker Automotive Systems GmbH
Harman Becker Automotive Systems Becker Division GmbH
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
    • H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
    • H04H40/54—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving generating subcarriers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/28—Arrangements for simultaneous broadcast of plural pieces of information
    • H04H20/33—Arrangements for simultaneous broadcast of plural pieces of information by plural channels
    • H04H20/34—Arrangements for simultaneous broadcast of plural pieces of information by plural channels using an out-of-band subcarrier signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H2201/00—Aspects of broadcast communication
    • H04H2201/10—Aspects of broadcast communication characterised by the type of broadcast system
    • H04H2201/13—Aspects of broadcast communication characterised by the type of broadcast system radio data system/radio broadcast data system [RDS/RBDS]

Definitions

  • the invention relates to a method and a circuit arrangement for demodulating the RDS signal.
  • the radio data system abbreviated RDS
  • RDS was used by FM radio stations introduced to data about the broadcasters and the program they broadcast on the radio stations to send where this data on an optical display device, has a liquid crystal screen reproduced become.
  • the RDS data is, for example, the program identification PI that the received program or the Specifies the name of the set station or the program type identifier PTY, which is the type of program for example Music show, news show, etc., or around the Traffic announcement identifier TA or around the radio text RT, the program accompanying Contains information such as B. Notes on Pieces of music, artists, program changes and the like.
  • the radio data system is mainly used by car radios.
  • RDS-compatible car radios switch on deteriorating reception of the currently tuned station automatically to a better or the best receivable and the same program broadcasting station.
  • the information required for this is the program identification PI and the list of alternative frequencies AF that be broadcast by RDS-compatible radio stations.
  • radio data system also offers this for home receivers Advantages for listeners, e.g. B. the program type identifier PTY and the radio text RT, which have already been mentioned and explained.
  • the RDS signal is a binary signal that consists of a continuous binary data stream with a bit rate of 1.1875 KBit / s exists.
  • FM radio transmitters send the so-called stereo multiplex signal from the audio center signal - also called mono signal - up to 15 KHz, the stereo pilot tone at 19 KHz, the stereo signal from 23 KHz to 53 KHz and the ARI signal, a narrow band amplitude-modulated signal with a carrier of 57 KHz becomes.
  • ARI is the acronym for Driver Broadcasting Information.
  • the RDS signal which has a wider bandwidth than the ARI signal is superimposed on the ARI signal.
  • this achieves a high data rate for the RDS signal is, on the other hand, disturbances of the audio center signal, the Stereo signal, the stereo pilot tone and the ARI signal the RDS signal is excluded is the frequency spectrum of the RDS signal limited to ⁇ 2.4 KHz.
  • the RDS signal is extracted from the RDS data stream by double sideband amplitude modulation generated with carrier suppression. Moreover becomes the suppressed RDS carrier compared to the ARI carrier from 57 kHz by 90 ° out of phase. Through this quadrature modulation become interference of the ARI signal by the RDS signal largely suppressed.
  • the broadcaster becomes the carrier of the type described Formed stereo multiplex signal frequency-modulated and broadcast.
  • the received frequency-modulated is on the receiver side Carrier demodulated to obtain the stereo multiplex signal, from which by demodulation in addition to the audio signals the RDS signal is won.
  • a circuit for demodulating an RDS signal is known from document EP-A-0 471 412.
  • this task is performed with those specified in claim 1
  • the sampled stereo multiplex signal in a first branch with the kophasal component multiplied by a digital oscillator and the resulting Signal is then low pass filtered that the sampling rate of the low-pass filtered signal by a predeterminable Division factor is divided that the low-pass filtered High pass filtered signal at the divided sampling rate that the high pass filtered signal in an RDS decoder is decoded that the stereo multiplex signal in a second branch with the quadrature component of the digital Multiplied the oscillator and then the resulting signal is low pass filtered that the sampling rate of the low-pass filtered signal by a predeterminable division factor is shared that the low-pass filtered signal with the divided sampling rate is high pass filtered and that from the high-pass filtered signal of the first and second branches and the RDS bit clock the phase position between the carrier of the RDS signal and the output signal of the oscillator Error signal is calculated from after filtering generates a correction signal for the digital
  • the sampled stereo multiplex signal at the first input of a first multiplier and a second multiplier is that the kophasal component a digital oscillator at the second input of the first multiplier and the quadrature component of the digital Oscillator at the second input of the second multiplier is that the output of the first multiplier by is connected to the input of a first low pass, whose output is connected to the input of a first divider, the Output connected to the input of a first high pass is that the output of the second multiplier by Input of a second low pass is connected, the output is connected to the input of a second divider, the Output connected to the input of a second high pass is that the exit of the first high pass with the first Input of a computing unit, the input of an RDS decoder, at the output of which the RDS data can be removed, and connected to the first control input of a clock generator is that the output of the second high pass with the second Input of
  • the method according to the invention provides that the received Stereo multiplex signal is first sampled.
  • the sampled Stereo multiplex signal is in a first branch with the Multiplied kophasal component of a digital oscillator.
  • the resulting signal is low pass filtered.
  • the sampling rate of the low-pass filtered signal is determined by a division factor divided. This low pass filtered in the sampling rate decimated Signal is high pass filtered and decoded in an RDS decoder.
  • a second branch the sampled stereo multiplex signal with the quadrature component of the digital oscillator multiplied.
  • the resulting signal becomes like the first Low pass filtered branch.
  • the sampling rate of the low pass filtered Signals is also shared.
  • the low pass filtered and in the decimated sampling rate signal is high pass filtered.
  • Out the high-pass filtered signal from the first and second branches as well as from the RDS bit clock the phase position between the carrier of the RDS signal and the output signal of the oscillator descriptive error signal calculated from which after filtering generates a correction signal for the digital oscillator becomes.
  • the sampling frequency for sampling the received stereo multiplex signal is chosen so that the spectrum of the RDS signal in the area around its carrier completely from the digital signal is represented.
  • the sampling frequency is preferably higher chosen as 120 KHz.
  • the division factor for dividing the sampling rate of the low-pass filtered Signals is selected to be 16, for example.
  • the RDS bit clock is used, for example, by a clock generator generated by the digital oscillator and the high-pass filtered Signal from the first branch is controlled.
  • the sampled stereo multiplex signal MPX is at the first input a multiplier M1 and a multiplier M2.
  • the kophasal component I of a digital oscillator OZ lies at the second input of multiplier M1, while the quadrature component Q of the digital oscillator OZ at the second input of the multiplier M2.
  • the output of the multiplier M1 is connected to the input of a low pass TP1, whose output is connected to the input of a divider D1 is.
  • the output of the divider D1 is connected to the input one High pass HP1 connected, the output of which is connected to the input of a RDS decoder DE and with the first input of a computing unit RE is connected.
  • the output of multiplier is M2 connected to the input of a low pass TP2, its output is connected to the input of a divider D2.
  • the exit the divider D2 is connected to the input of a high pass HP2, its output with the second input of the computing unit RE is connected.
  • the output of the computing unit is RE via a filter F, preferably a loop filter, with a Control unit SE connected, the output of which is connected to the control input of the digital oscillator OZ is connected.
  • a clock generator CG is provided, the Clock output with the clock input of the computing unit RE and the RDS decoder DE is connected.
  • the exit of the high pass HP1 is at the first input and the output of the digital Oscillator OZ to the second input of the clock generator CG connected.
  • the sampled stereo multiplex signal MPX is in a first Branch in multiplier M1 with the Kophasalkomponent I des digital oscillator OZ multiplied, then in low pass TP1 low pass filtered, its sampling rate is as follows Divider D1 divided and finally the stereo multiplex signal MPX in high pass HP1 high pass filtered.
  • Divider D1 divided and finally the stereo multiplex signal MPX in high pass HP1 high pass filtered.
  • the sampling frequency for sampling the stereo multiplex signal MPX is chosen so that the spectrum of the RDS signal is complete and correctly represented in the area around the 57 KHz carrier becomes.
  • the sampling frequency for sampling the stereo multiplex signal MPX should therefore be selected to be greater than 120 KHz.
  • the Decimation factor to decimate the sampling rate of the two low pass filtered signals should be selected so that the RDS signal is displayed correctly in the baseband.
  • the division factor is chosen to be 16.
  • the two high passes HP1 and HP2 are used for equal shares or to suppress low-frequency signal components caused by causes an ARI signal contained in the stereo multiplex signal MPX can be.
  • the computing unit RE receives an error signal after filtering fed through the loop filter F to the control unit SE becomes.
  • the control unit SE calculates a control signal Control of the digital oscillator OZ. That from the computing unit RE calculated error signal provides a measure of the phase deviation between the digital oscillator and the carrier of the RDS signal.
  • the RDS bit clock is generated by the clock generator CG high pass filtered signal at the output of high pass HP1 and controlled by the output signal of the digital oscillator OZ becomes.
  • the computing unit RE and the RDS decoder DE are clocked by the clock generator CG.
  • the circuit arrangement in the figure represents a phase locked loop which is often abbreviated to PLL - for phase locked loop becomes.
  • the calculation of the error signal in the computing unit RE is coupled with the RDS bit clock, the calculation of the Error signals only at the times when the kophasal component I is maximum. This is every quarter and a quarter a three-quarter bit clock period. By this measure it is avoided with certainty that the error signal from the computing unit RE is calculated at a point in time at which the kophasal component I has a zero crossing.
  • the clock generator CG runs free.
  • the amplitude of the Kophasal component checked.
  • the carrier synchronization can be found when a Zero crossing in kophasal component I the calculation cycle shifted by a quarter bit clock period for the error signal become. This measure will be a very quick one and reliable synchronization on the carrier of the RDS signal achieved.
  • the carrier frequency of the RDS signal and the frequency of the digital Oscillators OZ are 57 KHz each.
  • the invention which is characterized by a very fast synchronization on the carrier of the RDS signal is special suitable for car radios.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

The method involves processing a sampled stereo multiplex signal (MPX) in two branches, computing an error signal describing the phase angle between the RDS signal carrier and the output signal of an oscillator (OZ) from the high pass filtered signals of the first and second branches and the RDS bit clock (CL) and generating a correction signal for the oscillator from the error signal after filtering. Independent claims are also included for the following: a circuit for demodulation of radio data system or RDS signal.

Description

Die Erfindung betrifft ein Verfahren und eine Schaltungsanordnung zur Demodulation des RDS-Signals.The invention relates to a method and a circuit arrangement for demodulating the RDS signal.

Das Radio-Daten-System, abgekürzt RDS, wurde bei UKW-Rundfunksendern eingeführt, um Daten über die Rundfunksender und das von ihnen ausgestrahlte Programm zu den Rundfunksendern zu senden, wo diese Daten auf einer optischen Anzeigevorrichtung, weist ein Flüssigkeitskristallbildschirm, wiedergegeben werden.The radio data system, abbreviated RDS, was used by FM radio stations introduced to data about the broadcasters and the program they broadcast on the radio stations to send where this data on an optical display device, has a liquid crystal screen reproduced become.

Bei den RDS-Daten handelt es sich zum Beispiel um die Programmidentifikation PI, die das empfangene Programm oder den Namen des eingestellten Senders angibt, oder um die Programmartkennung PTY, welche die Art des Programms zum Beispiel Musiksendung, Nachrichtensendung usw. anzeigt, oder um die Verkehrsdurchsagekennung TA oder um den Radiotext RT, der programmbegleitende Informationen enthält wie z. B. Hinweise auf Musikstücke, Interpreten, Programmänderungen und dergleichen.The RDS data is, for example, the program identification PI that the received program or the Specifies the name of the set station or the program type identifier PTY, which is the type of program for example Music show, news show, etc., or around the Traffic announcement identifier TA or around the radio text RT, the program accompanying Contains information such as B. Notes on Pieces of music, artists, program changes and the like.

Das Radio-Daten-System wird hauptsächlich von Autoradios benutzt. Beispielsweise schalten RDS-taugliche Autoradios bei sich verschlechterndem Empfang des gerade eingestellten Senders automatisch auf einen besser oder den am besten empfangbaren und das gleiche Programm ausstrahlenden Sender um. Die hierfür erforderlichen Informationen sind die Programmidentifikation PI und die Liste der alternativen Frequenzen AF, die von RDS-tauglichen Rundfunksendern ausgestrahlt werden.The radio data system is mainly used by car radios. For example, RDS-compatible car radios switch on deteriorating reception of the currently tuned station automatically to a better or the best receivable and the same program broadcasting station. The The information required for this is the program identification PI and the list of alternative frequencies AF that be broadcast by RDS-compatible radio stations.

Doch auch für Heimempfänger bietet das Radio-Datensystem den Hörern Vorteile, z. B. die Programmartkennung PTY und der Radiotext RT, die bereits erwähnt und erläutert wurden.But the radio data system also offers this for home receivers Advantages for listeners, e.g. B. the program type identifier PTY and the radio text RT, which have already been mentioned and explained.

Das RDS-Signal ist ein binäres Signal, das aus einem kontinuierlichen binären Datenstrom mit einer Bitrate von 1,1875 KBit/s besteht.The RDS signal is a binary signal that consists of a continuous binary data stream with a bit rate of 1.1875 KBit / s exists.

UKW-Rundfunksender senden das sogenannte Stereomultiplexsignal aus, das aus dem Audiomittensignal - auch Monosignal genannt - bis 15 KHz, dem Stereopilotton bei 19 KHz, dem Stereosignal von 23 KHz bis 53 KHz und dem ARI-Signal, einem schmalbandigen amplitudenmodulierten Signal bei einem Träger von 57 KHz, gebildet wird. ARI ist die Abkürzung für Autofahrer-Rundfunk-Information.FM radio transmitters send the so-called stereo multiplex signal from the audio center signal - also called mono signal - up to 15 KHz, the stereo pilot tone at 19 KHz, the stereo signal from 23 KHz to 53 KHz and the ARI signal, a narrow band amplitude-modulated signal with a carrier of 57 KHz becomes. ARI is the acronym for Driver Broadcasting Information.

Das RDS-Signal, das eine größere Bandbreite als das ARI-Signal aufweist, wird dem ARI-Signal überlagert.The RDS signal, which has a wider bandwidth than the ARI signal is superimposed on the ARI signal.

Damit einerseits eine hohe Datenrate beim RDS-Signal erzielt wird, andererseits aber Störungen des Audiomittensignals, des Stereosignals, des Stereopilottons und des ARI-Signals durch das RDS-Signal ausgeschlossen sind, ist das Frequenzspektrum des RDS-Signals auf ±2,4 KHz begrenzt.On the one hand, this achieves a high data rate for the RDS signal is, on the other hand, disturbances of the audio center signal, the Stereo signal, the stereo pilot tone and the ARI signal the RDS signal is excluded is the frequency spectrum of the RDS signal limited to ± 2.4 KHz.

Das RDS-Signal wird aus dem RDS-Datenstrom durch Zweiseitenbandamplitudenmodulation mit Trägerunterdrückung erzeugt. Außerdem wird der unterdrückte RDS-Träger gegenüber dem ARI-Träger von 57 KHz um 90° phasenverschoben. Durch diese Quadraturmodulation werden Störungen des ARI-Signals durch das RDS-Signal weitestgehend unterdrückt. In einem RDS-tauglichen Rundfunksender wird der Träger vom auf die beschriebene Art gebildeten Stereomultiplexsignal frequenzmoduliert und ausgestrahlt.The RDS signal is extracted from the RDS data stream by double sideband amplitude modulation generated with carrier suppression. Moreover becomes the suppressed RDS carrier compared to the ARI carrier from 57 kHz by 90 ° out of phase. Through this quadrature modulation become interference of the ARI signal by the RDS signal largely suppressed. In an RDS-compatible The broadcaster becomes the carrier of the type described Formed stereo multiplex signal frequency-modulated and broadcast.

Auf der Empfängerseite wird der empfangene frequenzmodulierte Träger demoduliert, um das Stereomultiplexsignal zu gewinnen, aus dem durch Demodulation neben den Audiosignalen das RDS-Signal gewonnen wird.The received frequency-modulated is on the receiver side Carrier demodulated to obtain the stereo multiplex signal, from which by demodulation in addition to the audio signals the RDS signal is won.

Bei Empfang mittels eines Autoradios kann es infolge der häufig wechselnden und oft ungenügenden Empfangsbedingungen längere Zeit dauern, bis das Autoradio auf den Träger von 57 KHz des RDS-Signales synchronisiert ist.When received by means of a car radio, it can occur frequently due to the changing and often insufficient reception conditions longer Take time to get the car radio onto the carrier of 57 KHz of the RDS signal is synchronized.

Eine Schaltung zur Demodulation eines RDS - Signals ist aus Dokument EP-A-0 471 412 bekannt.A circuit for demodulating an RDS signal is known from document EP-A-0 471 412.

Es ist daher Aufgabe der Erfindung, ein Verfahren und eine Schaltungsanordnung zur Demodulation des RDS-Signals so zu gestalten, dass eine möglichst schnelle Synchronisation auf den Träger des RDS-Signals erzielt wird.It is therefore an object of the invention, a method and a To design circuitry for demodulating the RDS signal so that the fastest possible synchronization on the Carrier of the RDS signal is achieved.

Verfahrensmäßig wird diese Aufgabe mit den im Anspruch 1 angegebenen Merkmalen dadurch gelöst, dass das abgetastete Stereomultiplexsignal in einem ersten Zweig mit der Kophasalkomponente eines digitalen Oszillators multipliziert und das resultierende Signal anschließend tiefpaßgefiltert wird, dass die Abtastrate des tiefpaßgefilterten Signals durch einen vorgebbaren Teilungsfaktor geteilt wird, dass das tiefpaßgefilterte Signal mit der geteilten Abtastrate hochpaßgefiltert wird, dass das hochpaßgefilterte Signal in einem RDS-Decodierer decodiert wird, dass das Stereomultiplexsignal in einem zweiten Zweig mit der Quadraturkomponente des digitalen Oszillators multipliziert und das resultierende Signal anschließend tiefpaßgefiltert wird, dass die Abtastrate des tiefpaßgefilterten Signals durch einen vorgebbaren Teilungsfaktor geteilt wird, dass das tiefpaßgefilterte Signal mit der geteilten Abtastrate hochpaßgefiltert wird und dass aus dem hochpaßgefilterten Signal des ersten und des zweiten Zweiges sowie dem RDS-Bittakt ein die Phasenlage zwischen dem Träger des RDS-Signals und dem Ausgangssignal des Oszillators beschreibendes Fehlersignal berechnet wird, aus dem nach Filtering ein Korrektursignal für den digitalen Oszillator erzeugt wird.In procedural terms, this task is performed with those specified in claim 1 Features solved in that the sampled stereo multiplex signal in a first branch with the kophasal component multiplied by a digital oscillator and the resulting Signal is then low pass filtered that the sampling rate of the low-pass filtered signal by a predeterminable Division factor is divided that the low-pass filtered High pass filtered signal at the divided sampling rate that the high pass filtered signal in an RDS decoder is decoded that the stereo multiplex signal in a second branch with the quadrature component of the digital Multiplied the oscillator and then the resulting signal is low pass filtered that the sampling rate of the low-pass filtered signal by a predeterminable division factor is shared that the low-pass filtered signal with the divided sampling rate is high pass filtered and that from the high-pass filtered signal of the first and second branches and the RDS bit clock the phase position between the carrier of the RDS signal and the output signal of the oscillator Error signal is calculated from after filtering generates a correction signal for the digital oscillator becomes.

Schaltungsmäßig wird diese Aufgabe mit den im Anspruch 4 angegebenen Merkmalen dadurch gelöst, dass das abgetastete Stereomultiplexsignal am ersten Eingang eines ersten Multiplizierers und eines zweiten Multiplizierers liegt, dass die Kophasalkomponente eines digitalen Oszillators am zweiten Eingang des ersten Multiplizierers und die Quadraturkomponente des digitalen Oszillators am zweiten Eingang des zweiten Multiplizierers liegt, dass der Ausgang des ersten Multiplizierers mit dem Eingang eines ersten Tiefpasses verbunden ist, dessen Ausgang mit dem Eingang eines ersten Teilers verbunden ist, dessen Ausgang an den Eingang eines ersten Hochpasses angeschlossen ist, dass der Ausgang des zweiten Multiplizierers mit dem Eingang eines zweiten Tiefpasses verbunden ist, dessen Ausgang mit dem Eingang eines zweiten Teilers verbunden ist, dessen Ausgang an den Eingang eines zweiten Hochpasses angeschlossen ist, dass der Ausgang des ersten Hochpasses mit dem ersten Eingang einer Recheneinheit, dem Eingang eines RDS-Decodierers, an dessen Ausgang die RDS-Daten abnehmbar sind, und mit dem ersten Steuereingang eines Taktgenerators verbunden ist, dass der Ausgang des zweiten Hochpasses mit dem zweiten Eingang der Recheneinheit verbunden ist, deren Ausgang mit dem Eingang eines Filters verbunden ist, dass der Ausgang des Filters mit dem Eingang einer Steuereinheit verbunden ist, deren Ausgang an den Steuereingang des digitalen Oszillators angeschlossen ist, und dass der Ausgang des digitalen Oszillators an den zweiten Steuereingang des Taktgenerators angeschlossen ist, dessen Taktausgang mit dem Takteingang der Recheneinheit und des RDS-Decodierers verbunden ist.In terms of circuitry, this task with those specified in claim 4 Features solved in that the sampled stereo multiplex signal at the first input of a first multiplier and a second multiplier is that the kophasal component a digital oscillator at the second input of the first multiplier and the quadrature component of the digital Oscillator at the second input of the second multiplier is that the output of the first multiplier by is connected to the input of a first low pass, whose output is connected to the input of a first divider, the Output connected to the input of a first high pass is that the output of the second multiplier by Input of a second low pass is connected, the output is connected to the input of a second divider, the Output connected to the input of a second high pass is that the exit of the first high pass with the first Input of a computing unit, the input of an RDS decoder, at the output of which the RDS data can be removed, and connected to the first control input of a clock generator is that the output of the second high pass with the second Input of the computing unit, the output of which is connected connected to the input of a filter that the output of the Filters is connected to the input of a control unit, the Output connected to the control input of the digital oscillator is and that the output of the digital oscillator connected to the second control input of the clock generator is whose clock output with the clock input of the computing unit and the RDS decoder is connected.

Das erfindungsgemäße Verfahren sieht vor, dass das empfangene Stereomultiplexsignal zunächst abgetastet wird. Das abgetastete Stereomultiplexsignal wird in einem ersten Zweig mit der Kophasalkomponente eines digitalen Oszillators multipliziert. Das resultierende Signal wird tiefpaßgefiltert. Die Abtastrate des tiefpaßgefilterten Signals wird durch einen Teilungsfaktor geteilt. Dieses tiefpaßgefilterte in der Abtastrate dezimierte Signal wird hochpaßgefiltert und in einem RDS-Decodierer decodiert.The method according to the invention provides that the received Stereo multiplex signal is first sampled. The sampled Stereo multiplex signal is in a first branch with the Multiplied kophasal component of a digital oscillator. The resulting signal is low pass filtered. The sampling rate of the low-pass filtered signal is determined by a division factor divided. This low pass filtered in the sampling rate decimated Signal is high pass filtered and decoded in an RDS decoder.

In einem zweiten Zweig wird das abgetastete Stereomultiplexsignal mit der Quadraturkomponente des digitalen Oszillators multipliziert. Das resultierende Signal wird wie im ersten Zweig tiefpaßgefiltert. Die Abtastrate des tiefpaßgefilterten Signals wird ebenfalls geteilt. Das tiefpaßgefilterte und in der Abtastrate dezimierte Signal wird hochpaßgefiltert. Aus dem hochpaßgefilterten Signal des ersten und des zweiten Zweiges sowie aus den RDS-Bittakt wird ein die Phasenlage zwischen dem Träger des RDS-Signals und dem Ausgangssignal des Oszillators beschreibendes Fehlersignal berechnet, aus dem nach Filterung ein Korrektursignal für den digitalen Oszillator erzeugt wird. In a second branch the sampled stereo multiplex signal with the quadrature component of the digital oscillator multiplied. The resulting signal becomes like the first Low pass filtered branch. The sampling rate of the low pass filtered Signals is also shared. The low pass filtered and in the decimated sampling rate signal is high pass filtered. Out the high-pass filtered signal from the first and second branches as well as from the RDS bit clock the phase position between the carrier of the RDS signal and the output signal of the oscillator descriptive error signal calculated from which after filtering generates a correction signal for the digital oscillator becomes.

Die Abtastfrequenz zur Abtastung des empfangenen Stereomultiplexsignals ist so gewählt, dass das Spektrum des RDS-Signals im Bereich um seinen Träger vollständig vom digitalen Signal repräsentiert wird. Vorzugsweise ist die Abtastfrequenz größer als 120 KHz gewählt.The sampling frequency for sampling the received stereo multiplex signal is chosen so that the spectrum of the RDS signal in the area around its carrier completely from the digital signal is represented. The sampling frequency is preferably higher chosen as 120 KHz.

Der Teilungsfaktor zur Teilung der Abtastrate der tiefpaßgefilterten Signale ist beispielsweise zu 16 gewählt.The division factor for dividing the sampling rate of the low-pass filtered Signals is selected to be 16, for example.

Der RDS-Bittakt wird beispielsweise von einem Taktgenerator erzeugt, der vom digitalen Oszillator und vom hochpaßgefilterten Signal aus dem ersten Zweig gesteuert wird.The RDS bit clock is used, for example, by a clock generator generated by the digital oscillator and the high-pass filtered Signal from the first branch is controlled.

Das erfindungsgemäße Verfahren und die erfindungsgemäße Schaltungsanordnung werden anhand eines in der Figur dargestellten Ausführungsbeispieles näher beschrieben und erläutert.The method according to the invention and the circuit arrangement according to the invention are shown with the help of one in the figure Embodiment described and explained in more detail.

Das abgetastete Stereomultiplexsignal MPX liegt am ersten Eingang eines Multiplizierers M1 und eines Multiplizierers M2. Die Kophasalkomponente I eines digitalen Oszillators OZ liegt am zweiten Eingang des Multiplizierers M1, während die Quadraturkomponente Q des digitalen Oszillators OZ am zweiten Eingang des Multiplizierers M2 liegt. Der Ausgang des Multiplizierers M1 ist mit dem Eingang eines Tiefpasses TP1 verbunden, dessen Ausgang an den Eingang eines Teilers D1 angeschlossen ist. Der Ausgang des Teilers D1 ist mit dem Eingang eines Hochpasses HP1 verbunden, dessen Ausgang mit dem Eingang eines RDS-Decodierers DE und mit dem ersten Eingang einer Recheneinheit RE verbunden ist. Der Ausgang des Multiplizierers M2 ist mit dem Eingang eines Tiefpasses TP2 verbunden, dessen Ausgang an dem Eingang eines Teilers D2 angeschlossen ist. Der Ausgang des Teilers D2 ist mit dem Eingang eines Hochpasses HP2 verbunden, dessen Ausgang mit dem zweiten Eingang der Recheneinheit RE verbunden ist. Der Ausgang der Recheneinheit RE ist über ein Filter F, vorzugsweise ein Schleifenfilter, mit einer Steuereinheit SE verbunden, deren Ausgang mit dem Steuereingang des digitalen Oszillators OZ verbunden ist. Zur Erzeugung des RDS-Taktes CL ist ein Taktgenerator CG vorgesehen, dessen Taktausgang mit dem Takteingang der Recheneinheit RE und des RDS-Decodierers DE verbunden ist. Der Ausgang des Hochpasses HP1 ist an den ersten Eingang und der Ausgang des digitalen Oszillators OZ an den zweiten Eingang des Taktgenerators CG angeschlossen.The sampled stereo multiplex signal MPX is at the first input a multiplier M1 and a multiplier M2. The kophasal component I of a digital oscillator OZ lies at the second input of multiplier M1, while the quadrature component Q of the digital oscillator OZ at the second input of the multiplier M2. The output of the multiplier M1 is connected to the input of a low pass TP1, whose output is connected to the input of a divider D1 is. The output of the divider D1 is connected to the input one High pass HP1 connected, the output of which is connected to the input of a RDS decoder DE and with the first input of a computing unit RE is connected. The output of multiplier is M2 connected to the input of a low pass TP2, its output is connected to the input of a divider D2. The exit the divider D2 is connected to the input of a high pass HP2, its output with the second input of the computing unit RE is connected. The output of the computing unit is RE via a filter F, preferably a loop filter, with a Control unit SE connected, the output of which is connected to the control input of the digital oscillator OZ is connected. For generation of the RDS clock CL, a clock generator CG is provided, the Clock output with the clock input of the computing unit RE and the RDS decoder DE is connected. The exit of the high pass HP1 is at the first input and the output of the digital Oscillator OZ to the second input of the clock generator CG connected.

Das abgetastete Stereomultiplexsignal MPX wird in einem ersten Zweig im Multiplizierer M1 mit der Kophasalkomponente I des digitalen Oszillators OZ multipliziert, anschließend im Tiefpaß TP1 tiefpaßgefiltert, seine Abtastrate wird im folgenden Teiler D1 geteilt und schließlich wird das Stereomultiplexsignal MPX im Hochpaß HP1 hochpaßgefiltert. Parallel hierzu wird das abgetastete Stereomultiplexsignal MPX im Multiplizierer M2 mit der Quadraturkomponente Q des digitalen Oszillators OZ multipliziert, anschließend im Tiefpaß TP2 tiefpaßgefiltert, im folgenden Teiler D2 wird seine Abtastrate geteilt und schließlich wird es im Hochpaß HP2 hochpaßgefiltert.The sampled stereo multiplex signal MPX is in a first Branch in multiplier M1 with the Kophasalkomponent I des digital oscillator OZ multiplied, then in low pass TP1 low pass filtered, its sampling rate is as follows Divider D1 divided and finally the stereo multiplex signal MPX in high pass HP1 high pass filtered. In parallel to this the sampled stereo multiplex signal MPX in multiplier M2 with the quadrature component Q of the digital oscillator OZ multiplied, then low pass filtered in low pass TP2, in the following divider D2 its sampling rate is divided and finally it is high pass filtered in high pass HP2.

Die Abtastfrequenz zur Abtastung des Stereomultiplexsignals MPX ist so gewählt, dass das Spektrum des RDS-Signals vollständig und korrekt im Bereich um den Träger von 57 KHz repräsentiert wird. Die Abtastfrequenz zur Abtastung des Stereomultiplexsignals MPX ist daher größer als 120 KHz zu wählen. Der Dezimationsfaktor zur Dezimierung der Abtastrate der beiden tiefpaßgefilterten Signale ist so zu wählen, dass das RDS-Signal im Basisband korrekt dargestellt wird. Vorzugs-weise ist der Teilungsfaktor zu 16 gewählt.The sampling frequency for sampling the stereo multiplex signal MPX is chosen so that the spectrum of the RDS signal is complete and correctly represented in the area around the 57 KHz carrier becomes. The sampling frequency for sampling the stereo multiplex signal MPX should therefore be selected to be greater than 120 KHz. The Decimation factor to decimate the sampling rate of the two low pass filtered signals should be selected so that the RDS signal is displayed correctly in the baseband. Preferably the division factor is chosen to be 16.

Die beiden Hochpässe HP1 und HP2 dienen dazu, gleiche Anteile oder tieffrequente Signalanteile zu unterdrücken, die durch ein im Stereomultiplexsignal MPX enthaltenes ARI-Signal verursacht werden können.The two high passes HP1 and HP2 are used for equal shares or to suppress low-frequency signal components caused by causes an ARI signal contained in the stereo multiplex signal MPX can be.

Aus den hochpaßgefilterten Signalen an den Ausgängen der beiden Hochpässe HP1 und HP2 sowie aus dem RDS-Takt CL berechnet die Recheneinheit RE ein Fehlersignal, das nach Filterung durch das Schleifenfilter F der Steuereinheit SE zugeführt wird. Die Steuereinheit SE berechnet ein Steuersignal zur Steuerung des digitalen Oszillators OZ. Das von der Recheneinheit RE berechnete Fehlersignal stellt ein Maß für die Phasenabweichung zwischen dem digitalen Oszillator und dem Träger des RDS-Signales dar.From the high-pass filtered signals at the outputs of the two High passes HP1 and HP2 and calculated from the RDS clock CL the computing unit RE receives an error signal after filtering fed through the loop filter F to the control unit SE becomes. The control unit SE calculates a control signal Control of the digital oscillator OZ. That from the computing unit RE calculated error signal provides a measure of the phase deviation between the digital oscillator and the carrier of the RDS signal.

Der RDS-Bittakt wird vom Taktgenerator CG erzeugt, der vom hochpaßgefilterten Signal am Ausgang des Hochpasses HP1 und vom Ausgangssignal des digitalen Oszillators OZ gesteuert wird. Die Recheneinheit RE sowie der RDS-Decodierer DE werden vom Taktgenerator CG getaktet.The RDS bit clock is generated by the clock generator CG high pass filtered signal at the output of high pass HP1 and controlled by the output signal of the digital oscillator OZ becomes. The computing unit RE and the RDS decoder DE are clocked by the clock generator CG.

Die Schaltungsanordung in der Figur stellt einen Phasenregelkreis dar, der häufig mit PLL - für Phase locked loop- abgekürzt wird.The circuit arrangement in the figure represents a phase locked loop which is often abbreviated to PLL - for phase locked loop becomes.

Weil die Berechnung des Fehlersignales in der Recheneinheit RE mit dem RDS-Bittakt gekoppelt ist, erfolgt die Berechnung des Fehlersignales nur zu den Zeitpunkten, zu denen die Kophasalkomponente I maximal ist. Dies ist jeweils nach einer Viertelund einer Dreiviertelbittaktperiode der Fall. Durch diese Maßnahme wird mit Sicherheit vermieden, dass das Fehlersignal von der Recheneinheit RE zu einem Zeitpunkt berechnet wird, zu dem die Kophasalkomponente I einen Nulldurchgang aufweist.Because the calculation of the error signal in the computing unit RE is coupled with the RDS bit clock, the calculation of the Error signals only at the times when the kophasal component I is maximum. This is every quarter and a quarter a three-quarter bit clock period. By this measure it is avoided with certainty that the error signal from the computing unit RE is calculated at a point in time at which the kophasal component I has a zero crossing.

Solange der Phasenregelkreis noch nicht mit dem Träger des RDS-Signales synchronisiert ist, läuft der Taktgenerator CG frei. Um eine Berechnung des Fehlersignals in der Recheneinheit RE bei einem Nulldurchgang der Kophasalkomponente I des digitalen Oszillators OZ zu verhindern, wird die Amplitude der Kophasalkomponente geprüft. Während dieser Initialisierungsphase der Trägersynchronisation kann beim Auffinden eines Nulldurchgangs in der Kophasalkomponente I der Berechnungszyklus für das Fehlersignal um eine Viertelbittaktperiode verschoben werden. Durch diese Maßnahme wird eine sehr schnelle und zuverlässige Synchronisation auf den Träger des RDS-Signales erzielt. Ein weiterer Vorteil des erfindungsgemäßen Verfahrens liegt darin, dass es als Software realisierbar ist.As long as the phase locked loop is not yet with the carrier of the RDS signals is synchronized, the clock generator CG runs free. To calculate the error signal in the computing unit RE at a zero crossing of the Kophasalkomponent I des to prevent digital oscillator OZ, the amplitude of the Kophasal component checked. During this initialization phase the carrier synchronization can be found when a Zero crossing in kophasal component I the calculation cycle shifted by a quarter bit clock period for the error signal become. This measure will be a very quick one and reliable synchronization on the carrier of the RDS signal achieved. Another advantage of the invention The procedure is that it can be implemented as software.

Die Trägerfrequenz des RDS-Signales sowie die Frequenz des digitalen Oszillators OZ betragen jeweils 57 KHz.The carrier frequency of the RDS signal and the frequency of the digital Oscillators OZ are 57 KHz each.

Die Erfindung, die sich durch eine sehr schnelle Synchronisation auf den Träger des RDS-Signales auszeichnet, ist besonders für Autoradios geeignet. The invention, which is characterized by a very fast synchronization on the carrier of the RDS signal is special suitable for car radios.

BezugszeichenlisteLIST OF REFERENCE NUMBERS

CGCG
Taktgeneratorclock generator
CLCL
RDS-BittaktRDS bit clock
DEDE
RDS-DecodiererRDS decoder
D1D1
Teilerdivider
D2D2
Teilerdivider
FF
Schleifenfilterloop filter
HP1HP1
Hochpaßhighpass
HP2HP2
Hochpaßhighpass
II
KophasalkomponenteKophasalkomponente
MPXMPX
StereomultiplexsignalStereo multiplex signal
M1M1
Multiplizierermultipliers
M2M2
Multiplizierermultipliers
OZOZ
digitaler Oszillatordigital oscillator
QQ
Quadraturkomponentequadrature component
RERE
Recheneinheitcomputer unit
SESE
Steuereinheitcontrol unit
TP1TP1
Tiefpaßlowpass
TP2TP2
Tiefpaßlowpass

Claims (12)

  1. Method of demodulating an RDS signal in which the sampled stereo multiplex signal (MPX) is multiplied in a first branch by the in-phase component (I) of an oscillator and the resulting signal is then low-pass filtered, the sampling rate of the low-pass filtered signal is divided by a predeterminable division factor, the low-pass filtered signal which is decimated in the sampling rate is high-pass filtered, the high-pass filtered signal is decoded in a RDS decoder (DE), the sampled stereo multiplex signal (MPX) is multiplied in a second branch by the quadrature component (Q) of the oscillator (OZ) and the resulting signal is then low-pass filtered, the sampling rate of the low-pass filtered signal is divided by a predeterminable division factor, the low-pass filtered signal which is decimated in the sampling rate is high-pass filtered, and from the high-pass filtered signal of the first and second branches as well as the RDS bit clock signal (CL) an error signal is calculated which describes the phase relationship between the carrier of the RDS signal and the output signal of the oscillator (OZ) and from which a correction signal for the oscillator (OZ) is generated after filtering.
  2. Method as claimed in Claim 1, wherein the RDS bit clock signal (CL) is generated by a clock generator (CL) which is controlled by the oscillator (OZ) and by the high-pass filtered signal of the first branch.
  3. Method as claimed in Claim 2, wherein the RDS decoder (DE) is clocked with the RDS bit clock signal (CL).
  4. Method as claimed in Claims 1, 2 or 3, wherein the error signal is calculated at the times at which the in-phase component (I) is at a maximum.
  5. Method as claimed in Claims 1, 2, 3 or 4, wherein before synchronisation of the oscillator (OZ) with the carrier of the RDS signal the amplitude of the in-phase component (I) is checked and when a zero passage of the in-phase component (I) is detected the calculation cycle for the error signal is shifted by a quarter-bit clock period.
  6. Method as claimed in any one of Claims 1 to 5, wherein the method is implemented as software.
  7. Circuitry for demodulating an RDS signal, in which the sampled stereo multiplex signal (MPX) is applied to the first input of a first multiplier (M1) and of a second multiplier (M2), the in-phase component (I) of an oscillator (OZ) is applied to the second input of the first multiplier (M1) and the quadrature component (Q) of the oscillator (OZ) is applied to the second input of the second multiplier (M2), the output of the first multiplier (M1) is connected to the input of a first low-pass (TP1), the output of which is connected to the input of a first divider (D1), the output of which is connected to the input of a first high-pass (HP), the output of the second multiplier (M2) is connected to the input of a second low-pass (TP2), the output of which is connected to the input of a second divider (D2), the output of which is connected to the input of a second high-pass (H2), the output of the first high-pass (HP1) is connected to the first input of an arithmetic unit (RE), to the input of an RDS decoder (DE), at the output of which the RDS data can be retrieved, and to the first control input of a clock generator (CG), the output of the second high-pass (HP) is connected to the second input of the arithmetic unit (RE), the output of which is connected to the input of a filter (F), the output of the filter (F) is connected to the input of a control unit (SE), the output of which is connected to the control input of the oscillator (OZ), and the output of the oscillator (OZ) is connected to the second control input of the clock generator (CE), the clock output of which is connected to the clock input of the arithmetic unit (R) and of the RDS decoder (DE).
  8. Circuitry as claimed in Claim 7, wherein a loop filter is provided for the filter (F).
  9. Method or circuitry as claimed in any one of the preceding claims, wherein the sampling frequency for the stereo multiplex signal (MPX) is selected in such a way that the spectrum of the RDS signal in the region around the carrier of the RDS signal is represented completely by the digital signal.
  10. Method or circuitry as claimed in Claim 9, wherein the sampling frequency is selected to be greater than 120 KHz.
  11. Method or circuitry as claimed in any one of the preceding claims, wherein the division factor is selected to be 16.
  12. Method or circuitry as claimed in any one of the preceding claims, wherein a digital oscillator is provided for the oscillator (OZ).
EP20020003953 2001-03-10 2002-02-22 Method and System for demodulating an RDS-Signal Expired - Lifetime EP1239616B1 (en)

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DE10111590A DE10111590B4 (en) 2001-03-10 2001-03-10 Method and circuit arrangement for demodulating the RDS signal

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EP1239616A2 (en) 2002-09-11
US20020140515A1 (en) 2002-10-03
ATE278272T1 (en) 2004-10-15
US20040247133A1 (en) 2004-12-09
US6661292B2 (en) 2003-12-09
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DE10111590B4 (en) 2004-05-06
DE10111590A1 (en) 2002-10-02

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