EP1187330B1 - Voltage comparator circuit for the envelope of an AC voltage and method of comparing - Google Patents
Voltage comparator circuit for the envelope of an AC voltage and method of comparing Download PDFInfo
- Publication number
- EP1187330B1 EP1187330B1 EP01440236A EP01440236A EP1187330B1 EP 1187330 B1 EP1187330 B1 EP 1187330B1 EP 01440236 A EP01440236 A EP 01440236A EP 01440236 A EP01440236 A EP 01440236A EP 1187330 B1 EP1187330 B1 EP 1187330B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- voltage
- threshold
- threshold voltage
- output signal
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
Definitions
- the invention relates to a method for determining the overshoot or undershoot of the envelope of an AC voltage of a threshold voltage by means of a voltage comparator circuit and a voltage comparator circuit for the envelope of an AC voltage with three parallel-connected comparators to which the AC voltage is applied.
- Such a voltage comparator circuit is known from DE 692 20 851 T2 known.
- the envelope of an alternating voltage exceeds or falls below a threshold value
- the low-pass filter must be adapted to the maximum temporal dynamics of the time course of the envelope. The setting is fixed and can not be automatically adapted to changing dynamic conditions.
- the maximum frequency of the envelope and the AC voltage must not be close to each other because of the steep-edge transmission characteristic of the filter and the associated long filter settling times.
- the voltage comparator circuit of DE 692 20 851 T2 has a first comparator for comparing an input signal with a reference signal and a second comparator for detecting when the input signal exceeds the zero point.
- a differentiating circuit which generates a differentiated signal of an input signal and a divider circuit which divides the output of a circuit for holding a signal peak value so as to generate a reference signal are provided.
- a D flip-flop is provided with only a single data input, wherein the S input and the data input are connected directly to a voltage source, while the R input as well as the clock pulse input are connected via resistors to the voltage source and wherein the output of the flip-flop via a resistor having a high resistance value to achieve a hysteresis characteristic in the inverse operation of the flip-flop, is connected to the input of a first comparator.
- a diversity receiving radio receiver with two receivers known.
- a envelope wave detector is provided for generating an output voltage corresponding to the strength of the electromagnetic signal wave received by the receiver.
- a hysteresis comparator compares the outputs of the two envelope detectors and generates a switching control signal. In response to the switching signal, a switching device makes a selection between the signals generated by the first and second receivers.
- the magnitude of the hysteresis in the comparator is adjustable so that no or only a minimal oscillation occurs between the outputs of the two receivers.
- the hysteresis refers to the comparison of two envelopes and not to the exceeding or falling below a threshold value by the envelope due to superimposed interference voltages.
- a circuit for monitoring the level of AC signals which supplies a second potential at a digital output at a digital output lying at a predetermined level threshold level peaks of the AC signal and a second potential at a level limit exceeding level peaks.
- an output signal initially has the logic level "Low”. As soon as an AC voltage exceeds a lower voltage threshold, the output signal changes to a logic high level. This level is maintained until the input signal drops below the lower voltage threshold.
- Object of the present invention is therefore to develop a voltage comparator circuit of the type mentioned in such a way and to develop a method so that the exceeding or falling below the envelope of an AC voltage of a threshold voltage can be determined, with a hysteresis applied to eliminate the effect of superimposed interference voltages shall be.
- This method has the advantage that disturbances, for example in the case of input and output oscillations of the AC voltage, do not immediately become noticeable in the first output signal. Small disturbances are therefore tolerated so that a change in the level of the first output signal does not immediately occur with a slight change in the envelope of the AC voltage.
- the first output signal thus has a hysteresis characteristic.
- the method according to the invention can be implemented by a simple circuit.
- a variant of the method is characterized in that a second output signal assumes the "high” level when the first output signal has the “high” level and the alternating voltage is greater than the fourth threshold voltage U 1 .
- the second output signal represents a switched clock, which is only available when the first output signal has the "high” level. This switched clock can be used for downstream circuits.
- the object of the present invention is also achieved by a voltage comparator circuit, with the features of claim 3.
- the voltage comparator circuit according to the invention has no frequency-determining parts, e.g. Filter on. Therefore, there is no limitation on the temporal dynamics, i. the voltage comparator circuit is independent of the frequency of the AC voltage and the time dynamics of the envelope. Furthermore, the maximum frequency of the envelope need not be significantly less than the frequency of the AC voltage. Another advantage is that the circuit is extremely simple.
- the first output signal will not become high until the maximum threshold voltage is exceeded AC voltage is reached.
- the "low" level is not established just because the highest threshold voltage, e.g. due to noise occurring during an oscillation is not achieved, but only when the second largest threshold voltage is not reached during a vibration.
- the second threshold voltage is below and the third Threshold voltage above the mean value of the AC voltage.
- the first, third and fourth threshold voltages are positive.
- the positive half-wave of the AC voltage is essentially sufficient. If the fourth voltage threshold is not reached within a positive half cycle of the AC voltage, then the first output signal can be immediately switched to the "low" level.
- a feedback resistor is provided for each comparator. Through this feedback resistor, the hysteresis can be adjusted. Especially for the first comparator, the feedback resistance is important because it allows the threshold voltages of the first comparator to be adjusted.
- the oscillations of the AC voltage can be detected without errors.
- a second output signal is provided which assumes the level “high” when the first output signal has the level “high” and the AC voltage is greater than the fourth threshold voltage U 1 .
- downstream circuits are provided with a switched clock.
- a particularly preferred embodiment is characterized in that a broadband full-wave rectifier is provided.
- a broadband full-wave rectifier is provided.
- the second and third threshold voltages must be adjusted accordingly when using a full-wave rectifier, ie above and below the mean value of the rectified voltage.
- the comparator downstream evaluation circuit can be made particularly simple if it comprises a D flip-flop, two RS flip-flops and a JK flip-flop.
- Fig. 1 shows a block diagram 1 of the voltage comparator circuit according to the invention.
- An alternating voltage U in is connected to the negative input 2 of a first comparator 3 , via a resistor 4 to the positive input 5 of a second comparator 6 and via a resistor 7 to the positive input 8 of a third comparator 9 .
- At the positive input 10 of the first comparator 3 is located above a resistor 11, the average value of the AC voltage U at.
- the output 12 of the first comparator 3 is fed back via a resistor 13 to the positive input 10. this causes a hysteresis of the output signal G of the first comparator 3.
- the negative input 14 of the second comparator 6 is a, threshold voltage U 1 at.
- the output 15 of the second comparator 6 is fed back via a resistor 16 to the positive input 5 of the second comparator 6.
- the output signal F of the second comparator 6 assumes positive values as long as the AC voltage U in is greater than the threshold voltage U 1 and negative values as long as it is less than U 1 .
- the third comparator 9 At the negative input 17 of the third comparator 9 is a threshold voltage U 2 .
- the output 18 of the third comparator 9 is fed back via a resistor 19 to the positive input 8 of the third comparator 9.
- the output E of the third comparator assumes positive values as long as the AC voltage U in is greater than the threshold voltage U 2 and negative values as long as it is less than U 2 .
- the output 18 of the third comparator 9 is connected to the S input of an RS flip-flop 20 .
- the R input of the RS flip-flop 20 is connected to the output 12 of the first comparator 3.
- the output 15 of the second comparator 6 is connected to the S input of an RS flip-flop 21 .
- the R input of the RS flip-flop 21 is connected to the output 12 of the first comparator 3.
- the RS flip-flop 20 is connected to its Q output to an AND gate 22 .
- the output of the AND gate 22 is connected to one input of a OR gate 23 is connected and the output of the OR gate 23 is connected to the clock input of a JK flip-flop 24 .
- the output signal of the OR gate 23 thus acts as a clock signal of the JK flip-flop 24.
- Both control inputs of the JK flip-flop 24 are connected to a voltage source 25 and are thus permanently at a "high" level. For each clock signal, therefore, the output level is changed.
- the output level at the Q output of the JK flip-flop 24 represents the first output signal X of the voltage comparator circuit 1.
- An output signal X "high” means that the envelope of the AC voltage U in is within a usable range and no major interference voltages occur. Due to the fact that the level "High” is only assumed by the signal X when the threshold voltage U 2 is exceeded and that only when the threshold voltage U 1 is not reached, interference voltages become active when the threshold voltage U 2 is exceeded. and decay processes of the AC voltage U in not immediately noticeable in the signal X.
- the signal X thus has a hysteresis characteristic.
- the output of the JK flip-flop 24 is connected to the second input of the AND gate 22.
- the Q output of the RS flip-flop 21 is connected to the control input of a D flip-flop 25, which is clocked by the signal G.
- the Q Output of the D flip-flop 25 is connected to an input of an AND gate 26 .
- the other input of the AND gate 26 is connected to the Q output of the JK flip-flop 24.
- the output of the AND gate 26 is connected to the input of the OR gate 23.
- the Q output of the RS flip-flop 21 is further connected to the input of an AND gate 27 .
- the other input of the AND gate 27 is connected to the Q output of the JK flip-flop 24.
- the output signal of the AND gate 27 represents the second output signal Y. It assumes the level "high” when the output signal X has the level "high” and the AC voltage U in is greater than U 1 .
- FIG. 2 shows a schematic state diagram 30 for explaining the mode of operation of the voltage comparator circuit 1.
- the voltage comparator circuit 1 assumes the first output signal X to the "low" level.
- the threshold voltage U 2 Once the positive half-wave of the AC voltage U exceeds the threshold voltage U 2, theenskomparatorschalung goes to state 32 and the output signal X assumes the level “high” to. This means that the envelope of the AC voltage U in is greater than a predetermined threshold voltage U 2 . If the AC voltage U in towards the end of the positive half-wave smaller than the threshold voltage U 0a , which below the average value U the AC voltage U in is selected, the voltage comparator circuit 1 assumes the state 33 . The output signal X retains the "high" level.
- the AC voltage U After passing through the negative half-wave of the AC voltage U in, the AC voltage U passes through in the threshold voltage U 0b, the above the mean U the AC voltage U in is selected. As soon as the alternating voltage U in becomes greater than the threshold voltage U 0b , the voltage comparator circuit 1 assumes the state 34 . The output signal X maintains the level "High". Increases the AC voltage U in further to the threshold voltage V 1, so the voltage comparator circuit 1 receives a state 35th If the threshold voltage U 1 is not reached and the AC voltage U in again falls below the threshold voltage U 0a , the state 31 is taken and the output signal X assumes the level "low", which means that an interference voltage has occurred and the envelope of the AC voltage U in no longer usable. In state 35, the output signal X maintains the "high" level. If the AC voltage U in falls below the threshold voltage U 0a again , then the voltage comparator circuit 1 assumes the state 33.
- the alternating voltage U in is derived from an upstream steep-edge bandpass filter. Until the time of about 1 ms there is an undisturbed transient. From the time 4ms there is a disturbed decay, which does not change the output signal X causes. At about 5 ms, a disturbance occurs which causes a change in the output signal X. At about 7 ms, a transient begins again and at 9 ms again a disturbed decay occurs.
- the threshold voltages U 0a and U 0b were in the immediate vicinity of the mean value in this example U from 0V. The resolution of the representation is not sufficient to between U , U 0a and U 0b to distinguish.
- the threshold voltages U 1 and U 2 of the comparators 6, 9 are represented by horizontal lines.
- the signal E of the comparator 9 takes a positive value when the AC voltage exceeds the threshold voltage U in U. 2 This positive value is held until the AC voltage U in again falls below the threshold voltage U 2 .
- the comparator 9 is a comparator with hysteresis. This ensures that the generated pulses are not too short, so that they can also be detected by the evaluation logic.
- the signal E assumes a negative value.
- the signal F of the comparator 6 takes a positive value when the AC voltage exceeds the threshold voltage U in U. 1 This positive value is held until the AC voltage U in again falls below the threshold voltage U 1 . When the AC voltage U in is smaller than the threshold voltage U 1 , the signal F assumes a negative value.
- the comparator 6 has a hysteresis.
- the signal G assumes a positive value when the AC voltage U in falls below the threshold voltage U 0a and assumes a negative value when the AC voltage U in greater than the threshold voltage U 0b .
- the output signal X of the voltage comparator circuit has the "low” level at the beginning.
- the level “High” is assumed as soon as the AC voltage U in exceeds the threshold voltage U 2 for the first time.
- the level “Low” is resumed when the AC voltage U in after passing through the threshold voltage U 0b, the threshold voltage U 0a passes through without having reached the threshold voltage U 1 in between.
- the output signal Y assumes the level “high” when the output signal X has the level “high” and the signal F is positive, that is, the AC voltage U in greater than the threshold voltage U 1 .
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Measurement Of Current Or Voltage (AREA)
- Manipulation Of Pulses (AREA)
- Inverter Devices (AREA)
Abstract
Description
Die Erfindung betrifft ein Verfahren zur Feststellung des Über- oder Unterschreitens der Einhüllenden einer Wechselspannung einer Schwellenspannung mittels einer Spannungskomparatorschaltung und eine Spannungskomparatorschaltung für die Einhüllende einer Wechselspannung mit drei parallel geschalteten Komparatoren, an die die Wechselspannung angelegt ist.The invention relates to a method for determining the overshoot or undershoot of the envelope of an AC voltage of a threshold voltage by means of a voltage comparator circuit and a voltage comparator circuit for the envelope of an AC voltage with three parallel-connected comparators to which the AC voltage is applied.
Eine derartige Spannungskomparatorschaltung ist aus der
Zur Feststellung, ob die Einhüllende einer Wechselspannung einen Schwellwert über- oder unterschreitet, ist es bekannt, die Einhüllende mittels eines Tiefpassfilters und nachgeschaltetem Komparator mit Hysterese zu ermitteln. Allerdings muss der Tiefpassfilter auf die maximale zeitliche Dynamik des zeitlichen Verlaufs der Einhüllenden angepasst werden. Die Einstellung ist festgelegt und kann nicht automatisch auf sich ändernde dynamische Bedingungen adaptiert werden. Die maximale Frequenz der Einhüllenden und der Wechselspannung dürfen wegen der steilflankigen Übertragungscharakteristik des Filters und der damit verbundenen langen Filtereinschwingzeiten nicht nahe beieinander liegen.To determine whether the envelope of an alternating voltage exceeds or falls below a threshold value, it is known to determine the envelope by means of a low-pass filter and a downstream comparator with hysteresis. However, the low-pass filter must be adapted to the maximum temporal dynamics of the time course of the envelope. The setting is fixed and can not be automatically adapted to changing dynamic conditions. The maximum frequency of the envelope and the AC voltage must not be close to each other because of the steep-edge transmission characteristic of the filter and the associated long filter settling times.
Ferner ist es möglich, die Wechselspannung abzutasten und rechentechnisch zu erfassen. Dies erfordert aber einen hohen Schaltungsaufwand und erlaubt nur eine geringe Maximalfrequenz der Wechselspannung.Furthermore, it is possible to sample the AC voltage and to acquire it by calculation. However, this requires a high circuit complexity and allows only a low maximum frequency of the AC voltage.
Die Spannungskomparatorschaltung der
Allerdings gelingt es mit dieser Schaltung nur, eine Hüllkurve für einen Signalspitzenwert und dessen Lage zu bestimmen. Eine Hysterese für eine Einhüllende einer Wechselspannung wird aber nicht unterstützt.However, with this circuit it is only possible to determine an envelope for a signal peak value and its position. A hysteresis for an envelope of an AC voltage is not supported.
Aus der
Aus der
Aufgabe der vorliegenden Erfindung ist es daher, eine Spannungskomparatorschaltung der eingangs genannten Art derart weiterzubilden und ein Verfahren zu entwickeln, so dass das Über- oder Unterschreiten der Einhüllenden einer Wechselspannung einer Schwellenspannung festgestellt werden kann, wobei eine Hysterese zur Beseitigung der Wirkung von überlagerten Störspannungen angewandt werden soll.Object of the present invention is therefore to develop a voltage comparator circuit of the type mentioned in such a way and to develop a method so that the exceeding or falling below the envelope of an AC voltage of a threshold voltage can be determined, with a hysteresis applied to eliminate the effect of superimposed interference voltages shall be.
Gelöst wird diese Aufgabe erfindungsgemäß durch ein Verfahren mit den Merkmalen des Anspruchs 1.This object is achieved according to the invention by a method having the features of claim 1.
Dieses Verfahren hat den Vorteil, dass sich Störungen z.B. bei Ein- und Ausschwingvorgängen der Wechselspannung nicht sofort im ersten Ausgangssignal bemerkbar machen. Kleine Störungen werden also toleriert, so dass nicht sofort bei einer geringen Veränderung der Einhüllenden der Wechselspannung eine Änderung des Pegels des ersten Ausgangssignals eintritt. Das erste Ausgangssignal weist also eine Hysteresecharakteristik auf. Weiterhin kann das erfindungsgemäße Verfahren durch eine einfache Schaltung implementiert werden.This method has the advantage that disturbances, for example in the case of input and output oscillations of the AC voltage, do not immediately become noticeable in the first output signal. Small disturbances are therefore tolerated so that a change in the level of the first output signal does not immediately occur with a slight change in the envelope of the AC voltage. The first output signal thus has a hysteresis characteristic. Furthermore, the method according to the invention can be implemented by a simple circuit.
Eine Verfahrensvariante zeichnet sich dadurch aus, dass ein zweites Ausgangssignal den Pegel "High" einnimmt, wenn das erste Ausgangssignal den Pegel "High" aufweist und die Wechselspannung größer als die vierte Schwellenspannung U1 ist. Das zweite Ausgangssignal stellt einen geschalteten Takt dar, der nur zur Verfügung steht, wenn das erste Ausgangssignal den Pegel "High" aufweist. Dieser geschaltete Takt kann für nachgeschaltete Schaltungen verwendet werden.A variant of the method is characterized in that a second output signal assumes the "high" level when the first output signal has the "high" level and the alternating voltage is greater than the fourth threshold voltage U 1 . The second output signal represents a switched clock, which is only available when the first output signal has the "high" level. This switched clock can be used for downstream circuits.
Die Aufgabe der vorliegenden Erfindung wird erfindungsgemäß auch durch eine Spannungskomparatorschaltung, mit den Merkmalen des Anspruchs 3 gelöst.The object of the present invention is also achieved by a voltage comparator circuit, with the features of
Die erfindungsgemäße Spannungskomparatorschaltung weist keine frequenzbestimmende Teile wie z.B. Filter auf. Deshalb besteht keine Einschränkung der zeitlichen Dynamik, d.h. die Spannungskomparatorschaltung ist unabhängig von der Frequenz der Wechselspannung und der zeitlichen Dynamik der Einhüllenden. Des Weiteren muss die maximale Frequenz der Einhüllenden nicht wesentlich kleiner sein als die Frequenz der Wechselspannung. Ein weiterer Vorteil ist, dass die Schaltung extrem einfach aufgebaut ist.The voltage comparator circuit according to the invention has no frequency-determining parts, e.g. Filter on. Therefore, there is no limitation on the temporal dynamics, i. the voltage comparator circuit is independent of the frequency of the AC voltage and the time dynamics of the envelope. Furthermore, the maximum frequency of the envelope need not be significantly less than the frequency of the AC voltage. Another advantage is that the circuit is extremely simple.
Ist der Betrag der ersten Schwellenspannung größer ist als der Betrag der vierten Schwellenspannung und der Betrag der vierten Schwellenspannung größer ist als der Betrag der zweiten oder dritten Schwellenspannung, so nimmt das erste Ausgangssignal den Pegel "High" erst ein, wenn die größte Schwellenspannung durch die Wechselspannung erreicht wird. Der Pegel "Low" stellt sich aber nicht schon deshalb ein, weil die höchste Schwellenspannung, z.B. wegen auftretender Störspannungen, während einer Schwingung nicht erreicht wird, sondern erst, wenn auch die zweitgrößte Schwellenspannung während einer Schwingung nicht erreicht wird.If the magnitude of the first threshold voltage is greater than the magnitude of the fourth threshold voltage and the magnitude of the fourth threshold voltage is greater than the magnitude of the second or third threshold voltage, the first output signal will not become high until the maximum threshold voltage is exceeded AC voltage is reached. However, the "low" level is not established just because the highest threshold voltage, e.g. due to noise occurring during an oscillation is not achieved, but only when the second largest threshold voltage is not reached during a vibration.
Bei einer bevorzugten Ausführungsform der Spannungskomparatorschaltung liegt die zweite Schwellenspannung unterhalb und die dritte Schwellenspannung oberhalb des Mittelwerts der Wechselspannung. Durch diese Wahl der zweiten und dritten Schwellenspannungen können die Schwingungen der Wechselspannung detektiert werden.In a preferred embodiment of the voltage comparator circuit, the second threshold voltage is below and the third Threshold voltage above the mean value of the AC voltage. By this choice of the second and third threshold voltages, the oscillations of the AC voltage can be detected.
Bei einer besonders vorteilhaften Ausführungsform sind die erste, dritte und vierte Schwellenspannung positiv. Für die Bewertung der Wechselspannung ist im wesentlichen die positive Halbwelle der Wechselspannung ausreichend. Wird innerhalb einer positiven Halbwelle der Wechselspannung die vierte Spannungsschwelle nicht erreicht, so kann das erste Ausgangssignal sofort auf den Pegel "Low" geschaltet werden.In a particularly advantageous embodiment, the first, third and fourth threshold voltages are positive. For the evaluation of the AC voltage, the positive half-wave of the AC voltage is essentially sufficient. If the fourth voltage threshold is not reached within a positive half cycle of the AC voltage, then the first output signal can be immediately switched to the "low" level.
Besonders vorteilhaft ist es, wenn für jeden Komparator ein Rückkopplungswiderstand vorgesehen ist. Durch diesen Rückkopplungswiderstand kann die Hysterese eingestellt werden. Insbesondere für den ersten Komparator ist der Rückkopplungswiderstand wichtig, da dadurch die Schwellenspannungen des ersten Komparators eingestellt werden können.It is particularly advantageous if a feedback resistor is provided for each comparator. Through this feedback resistor, the hysteresis can be adjusted. Especially for the first comparator, the feedback resistance is important because it allows the threshold voltages of the first comparator to be adjusted.
Ist die Differenz der Beträge der zweiten und dritten Schwellenspannung größer als die Störspannungen, so können die Schwingungen der Wechselspannung fehlerfrei erkannt werden.If the difference of the amounts of the second and third threshold voltage is greater than the interference voltages, the oscillations of the AC voltage can be detected without errors.
Wenn die Differenz der Beträge der ersten und vierten Schwellenspannung größer als die Störspannungen ist, ist ein fehlerfreies Schalten der Spannungskomparatorschaltung sicher gestellt.If the difference of the amounts of the first and fourth threshold voltage is greater than the interference voltages, an error-free switching of the voltage comparator circuit is ensured.
Bei einer vorteilhaften Ausführungsform der erfindungsgemäßen Spannungskomparatorschaltung ist ein zweites Ausgangssignal vorgesehen, das den Pegel "High" annimmt, wenn das erste Ausgangssignal den Pegel "High" hat und die Wechselspannung größer als die vierte Schwellenspannung U1 ist. Dadurch wird nachfolgenden Schaltungen ein geschalteter Takt zur Verfügung gestellt.In an advantageous embodiment of the voltage comparator circuit according to the invention, a second output signal is provided which assumes the level "high" when the first output signal has the level "high" and the AC voltage is greater than the fourth threshold voltage U 1 . As a result, downstream circuits are provided with a switched clock.
Eine besonders bevorzugte Ausführungsform zeichnet sich dadurch aus, dass ein breitbandiger Vollweggleichrichter vorgesehen ist. Durch die Gleichrichtung der Wechselspannung kann die Detektion der Position der Einhüllenden ober- oder unterhalb einer Schwellenspannung beschleunigt werden. Die zweite und dritte Schwellenspannungen sind bei Verwendung eines Vollweggleichrichters entsprechend anzupassen, d.h. ober- und unterhalb des Mittelwerts der gleichgerichteten Spannung zu wählen.A particularly preferred embodiment is characterized in that a broadband full-wave rectifier is provided. By rectifying the AC voltage, the detection of the position of the envelope can be accelerated above or below a threshold voltage. The second and third threshold voltages must be adjusted accordingly when using a full-wave rectifier, ie above and below the mean value of the rectified voltage.
Die den Komparatoren nachgeschaltete Auswerteschaltung kann besonders einfach gestaltet werden, wenn sie ein D-Flip-Flop, zwei RS-Flip-Flops und ein JK-Flip-Flop umfasst.The comparator downstream evaluation circuit can be made particularly simple if it comprises a D flip-flop, two RS flip-flops and a JK flip-flop.
Weitere Vorteile der Erfindung ergeben sich aus der Beschreibung und der Zeichnung. Ebenso können die vorstehend genannten und die noch weiter ausgeführten Merkmale erfindungsgemäß jeweils einzeln für sich oder zu mehreren in beliebigen Kombinationen Verwendung finden. Die gezeigten und beschriebenen Ausführungsformen sind nicht als abschließende Aufzählung zu verstehen, sondern haben vielmehr beispielhaften Charakter für die Schilderung der Erfindung.Further advantages of the invention will become apparent from the description and the drawings. Likewise, according to the invention, the above-mentioned features and those which are still further developed can each be used individually for themselves or for a plurality of combinations of any kind. The embodiments shown and described are not to be understood as exhaustive enumeration, but rather have exemplary character for the description of the invention.
Die Erfindung ist in der Zeichnung dargestellt und wird anhand von Ausführungsbeispielen naher erläutert. Es zeigen:
- Fig. 1
- ein Blockschaltbild der erfindungsgemäßen Spannungskomparatorschaltung;
- Fig. 2
- ein schematisches Zustandsdiagramm zur Erläuterung der Funktionsweise der Spannungskomparatorschaltung; und
- Fig. 3
- eine Wechselspannung, Ausgangssignale der Komparatoren und Ausgangssignale der Spannungskomparatorschaltung.
- Fig. 1
- a block diagram of the voltage comparator circuit according to the invention;
- Fig. 2
- a schematic state diagram for explaining the operation of the voltage comparator circuit; and
- Fig. 3
- an alternating voltage, output signals of the comparators and output signals of the voltage comparator circuit.
Fig. 1 zeigt ein Blockschaltbild 1 der erfindungsgemäßen Spannungskomparatorschaltung. Eine Wechselspannung Uin liegt am negativen Eingang 2 eines ersten Komparators 3, über einen Widerstand 4 am positiven Eingang 5 eines zweiten Komparators 6 und über einen Widerstand 7 am positiven Eingang 8 eines dritten Komparators 9 an. Am positiven Eingang 10 des ersten Komparators 3 liegt über einen Widerstand 11 der Mittelwert der Wechselspannung
Am negativen Eingang 14 des zweiten Komparators 6 liegt eine , Schwellenspannung U1 an. Der Ausgang 15 des zweiten Komparators 6 ist über einen Widerstand 16 auf den positiven Eingang 5 des zweiten Komparators 6 rückgekoppelt. Das Ausgangssignal F des zweiten Komparators 6 nimmt positive Werte an, solange die Wechselspannung Uin größer ist als die Schwellenspannung U1 und negative Werte, solange sie kleiner als U1 ist.At the
Am negativen Eingang 17 des dritten Komparators 9 liegt eine Schwellenspannung U2 an. Der Ausgang 18 des dritten Komparators 9 ist über einen Widerstand 19 auf den positiven Eingang 8 des dritten Komparators 9 rückgekoppelt. Das Ausgangssignal E des dritten Komparators nimmt positive Werte an, solange die Wechselspannung Uin größer ist als die Schwellenspannung U2 und negative Werte, solange sie kleiner als U2 ist.At the
Der Ausgang 18 des dritten Komparators 9 ist mit dem S-Eingang eines RS-Flip-Flops 20 verbunden. Der R-Eingang des RS-Flip-Flops 20 ist mit dem Ausgang 12 des ersten Komparators 3 verbunden.The
Der Ausgang 15 des zweiten Komparators 6 ist mit dem S-Eingang eines RS-Flip-Flops 21 verbunden. Der R-Eingang des RS-Flip-Flops 21 ist mit dem Ausgang 12 des ersten Komparators 3 verbunden.The
Das RS-Flip-Flop 20 ist mit seinem Q-Ausgang mit einem AND-Gatter 22 verbunden. Der Ausgang des AND-Gatters 22 ist mit dem einen Eingang eines OR-Gatters 23 verbunden und der Ausgang des OR-Gatters 23 ist mit dem Takteingang eines JK-Flip-Flops 24 verbunden. Das Ausgangssignal des OR-Gatters 23 wirkt also als Taktsignal des JK-Flip-Flops 24. Beide Steuereingänge des JK-Flip-Flops 24 sind mit einer Spannungsquelle 25 verbunden und sind somit permanent auf einem "High"-Pegel. Bei jedem Taktsignal wird daher der Ausgangspegel gewechselt. Der Ausgangspegel am Q-Ausgang des JK-Flip-Flops 24 stellt das erste Ausgangssignal X der Spannungskomparatorschaltung 1 dar. Ein Ausgangssignal X "High" bedeutet, dass die Einhüllende der Wechselspannung Uin in einem nutzbaren Bereich liegt und keine größeren Störspannungen auftreten. Dadurch, dass der Pegel "High" vom Signal X erst eingenommen wird, wenn die Schwellspannung U2 überschritten wird und dass erst in den "Low" Zustand geschaltet wird, wenn die Schwellenspannung U1 nicht mehr erreicht wird, machen sich Störspannungen bei Ein- und Ausschwingvorgängen der Wechselspannung Uin nicht sofort im Signal X bemerkbar. Das Signal X weist also eine Hysteresecharakteristik auf. Der
Fig. 2 zeigt ein schematisches Zustandsdiagramm 30 zur Erläuterung der Funktionsweise der Spannungskomparatorschaltung 1. Im Ausgangszustand 31 der Spannungskomparatorschaltung 1 nimmt das erste Ausgangssignal X den Pegel "Low" an. Sobald die positive Halbwelle der Wechselspannung Uin die Schwellenspannung U2 überschreitet, geht die Spannungskomparatorschalung in den Zustand 32 und das Ausgangssignal X nimmt den Pegel "High" an. Das bedeutet, dass die Einhüllende der Wechselspannung Uin größer ist als eine vorgegeben Schwellenspannung U2. Wird die Wechselspannung Uin gegen Ende der positiven Halbwelle kleiner als die Schwellenspannung U0a, welche unterhalb des Mittelwertes
Fig. 3 zeigt exemplarisch einen zeitlichen Verlauf der Wechselspannung Uin, sowie der Ausgangssignale E,F,G der Komparatoren 3,6,9 und der Ausgangssignale X und Y. Die Wechselspannung Uin stammt von einem vorgeschalteten steilflankigen Bandpassfilter. Bis zum Zeitpunkt von etwa 1ms liegt ein ungestörter Einschwingvorgang vor. Ab dem Zeitpunkt 4ms erfolgt ein gestörter Ausschwingvorgang, der noch keine Änderung des Ausgangssignals X bewirkt. Bei etwa 5ms tritt eine Störung auf, die eine Änderung des Ausgangssignals X bewirkt. Bei etwa 7ms beginnt erneut ein Einschwingvorgang und bei 9ms tritt wieder ein gestörter Ausschwingvorgang auf. Die Schwellenspannung U0a und U0b wurden in diesem Beispiel in unmittelbarer Nähe des Mittelwertes
Das Signal E des Komparators 9 nimmt einen positiven Wert an, sobald die Wechselspannung Uin die Schwellenspannung U2 überschreitet. Dieser positive Wert wird gehalten, bis die Wechselspannung Uin wieder unter die Schwellenspannung U2 fällt. Beim Komparator 9 handelt es sich um einen Komparator mit Hysterese. Damit wird bewirkt, dass die erzeugten Impulse nicht zu kurz sind, so dass sie von der Auswertelogik auch detektiert werden können. Wenn die Wechselspannung Uin kleiner als die Schwellenspannung U2 ist, nimmt das Signal E einen negativen Wert an.The signal E of the
Das Signal F des Komparators 6 nimmt einen positiven Wert an, sobald die Wechselspannung Uin die Schwellenspannung U1 überschreitet. Dieser positive Wert wird gehalten, bis die Wechselspannung Uin wieder unter die Schwellenspannung U1 fällt. Wenn die Wechselspannung Uin kleiner als die Schwellenspannung U1 ist, nimmt das Signal F einen negativen Wert an. Der Komparator 6 weist eine Hysterese auf.The signal F of the
Das Signal G nimmt einen positiven Wert an, wenn die Wechselspannung Uin unter die Schwellenspannung U0a fällt und nimmt einen negativen Wert an, wenn die Wechselspannung Uin größer als die Schwellenspannung U0b wird.The signal G assumes a positive value when the AC voltage U in falls below the threshold voltage U 0a and assumes a negative value when the AC voltage U in greater than the threshold voltage U 0b .
Das Ausgangssignal X der Spannungskomparatorschaltung hat zu Begin den Pegel "Low". Der Pegel "High" wird eingenommen, sobald die Wechselspannung Uin zum ersten Mal die Schwellenspannung U2 überschreitet.The output signal X of the voltage comparator circuit has the "low" level at the beginning. The level "High" is assumed as soon as the AC voltage U in exceeds the threshold voltage U 2 for the first time.
Der Pegel "Low" wird wieder eingenommen, wenn die Wechselspannung Uin nach Durchlaufen der Schwellenspannung U0b die Schwellenspannung U0a durchläuft, ohne dazwischen die Schwellenspannung U1 erreicht zu haben. Das Ausgangssignal Y nimmt den Pegel "High" an, wenn das Ausgangssignal X den Pegel "High" hat und das Signal F positiv ist, d.h. die Wechselspannung Uin größer als die Schwellenspannung U1 ist.The level "Low" is resumed when the AC voltage U in after passing through the threshold voltage U 0b, the threshold voltage U 0a passes through without having reached the threshold voltage U 1 in between. The output signal Y assumes the level "high" when the output signal X has the level "high" and the signal F is positive, that is, the AC voltage U in greater than the threshold voltage U 1 .
Claims (11)
- Method to establish that the envelope of an AC voltage (Uin) has exceeded or not reached a threshold voltage by means of a voltage comparator circuit (1),
characterised in that
a first output signal (X) has the "Low" level at the beginning and takes up the "High" level as soon as the AC voltage (Uin) exceeds a first, largest threshold voltage (U2) according to the amount and the output signal (X) takes up the "Low" level again if, after exceeding a second threshold voltage (U0a) below the average value (U ) of the AC voltage (Uin), a third threshold voltage (U0b) above the average value (U ) is not reached by the AC voltage (Uin), without a second largest, fourth threshold voltage (Ua) according to the amount being reached in the meantime, in which the second or third threshold voltages (U0a, U0b) are smaller than the second largest, fourth threshold voltage (U1) according to the amount. - Method according to claim 1, characterised in that a second output signal (Y) takes up the "High" level, if the first output signal (X) has the "High" level and the AC voltage (Uin) is greater than the fourth threshold value (U1).
- Voltage comparator circuit (1) for the envelope of an AC voltage (Uin) with three comparators (3, 6, 9), to which the AC voltage (Uin) is connected in parallel,
characterised in that
comparators with hysteresis are provided as comparators (3, 6, 9), the first comparator (3) has a second and third threshold voltage (U0a, U0b), the second comparator (6) has a fourth threshold voltage (U1) and the third comparator (9) has a first threshold voltage (U2) and a logic circuit is provided to identify an output signal (X) depending on the output signals (G, F, E) of the comparators (3, 6, 9) made in such a way that the output signal (X) changes from a first to a second logic level, as soon as the AC voltage (Uin) exceeds a first threshold voltage (U2) and the output signal (X) changes from the second to the first logic level, if the fourth threshold voltage (U1) is not reached during an oscillation of the AC voltage (Uin), in which the amount of the first threshold voltage (U2) is greater than the amount of the fourth threshold voltage (U1) and the amount of the fourth threshold voltage (U1) is greater than the amount of the second or third threshold voltage (U0a, U0b). - Voltage comparator circuit according to claim 3, characterised in that the second threshold voltage (U0a) is below and the third threshold voltage (U0b) is above the average value of the AC voltage (Uin).
- Voltage comparator circuit according to one of claims 3 or 4, characterised in that the first (U2), third (U0b) and fourth (U1) threshold voltages are positive.
- Voltage comparator circuit according to one of claims 3 to 5, characterised in that a feedback resistance (13, 16, 19) is provided for each comparator (3, 6, 9).
- Voltage comparator circuit according to one of claims 3 to 6, characterised in that the difference in the amounts of the second and third threshold voltages (U0a, U0b) is greater than the interference voltages.
- Voltage comparator circuit according to one of claims 3 to 7, characterised in that the difference in the amounts of the first and fourth threshold voltages (U2, U1) is greater than the interference voltages.
- Voltage comparator circuit according to one of claims 3 to 8, characterised in that a second output signal (Y) is provided, which takes on the "High" level, if the first output signal (X) has the "High" level and the AC voltage (Uin) is greater than the fourth threshold voltage (U1).
- Voltage comparator circuit according to one of claims 3 to 9, characterised in that a full wave rectifier is provided.
- Voltage comparator circuit according to one of claims 3 to 10, characterised in that the logic circuit comprises a D flip flop, two RS flip flops and a JK flip flop.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10042270 | 2000-08-29 | ||
DE10042270A DE10042270A1 (en) | 2000-08-29 | 2000-08-29 | Voltage comparator circuit for the envelope of an AC voltage and method therefor |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1187330A2 EP1187330A2 (en) | 2002-03-13 |
EP1187330A3 EP1187330A3 (en) | 2004-02-25 |
EP1187330B1 true EP1187330B1 (en) | 2007-09-26 |
Family
ID=7654089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01440236A Expired - Lifetime EP1187330B1 (en) | 2000-08-29 | 2001-07-25 | Voltage comparator circuit for the envelope of an AC voltage and method of comparing |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1187330B1 (en) |
AT (1) | ATE374452T1 (en) |
DE (2) | DE10042270A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10223514B4 (en) | 2002-05-27 | 2010-01-28 | Infineon Technologies Ag | comparator circuit |
EP1521364B1 (en) | 2003-09-29 | 2013-08-21 | EM Microelectronic-Marin SA | Method and apparatus for filtering signals generated by a piezoelectric accelerometer, and application in a portable object such as a watch |
GB2421317B (en) | 2004-12-15 | 2009-02-11 | Agilent Technologies Inc | A method and apparatus for detecting leading pulse edges |
DE102006040795B4 (en) * | 2006-08-31 | 2009-01-15 | Infineon Technologies Ag | Threshold circuit arrangement |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3718305C1 (en) * | 1987-05-30 | 1988-09-22 | Rohde & Schwarz | Circuit for monitoring the level of alternating-voltage signals |
JP2960200B2 (en) * | 1991-05-14 | 1999-10-06 | 株式会社日本コンラックス | Peak detection circuit |
AT412600B (en) * | 1996-10-29 | 2005-04-25 | Bernhard Dipl Ing Rzepa | CIRCUIT ARRANGEMENT FOR HYSTERESIZED THRESHOLD DETECTION OF THE PEAK VALUE OF A PERIODIC INPUT SIGNAL |
-
2000
- 2000-08-29 DE DE10042270A patent/DE10042270A1/en not_active Withdrawn
-
2001
- 2001-07-25 DE DE50113055T patent/DE50113055D1/en not_active Expired - Lifetime
- 2001-07-25 EP EP01440236A patent/EP1187330B1/en not_active Expired - Lifetime
- 2001-07-25 AT AT01440236T patent/ATE374452T1/en active
Non-Patent Citations (1)
Title |
---|
None * |
Also Published As
Publication number | Publication date |
---|---|
EP1187330A3 (en) | 2004-02-25 |
ATE374452T1 (en) | 2007-10-15 |
DE50113055D1 (en) | 2007-11-08 |
EP1187330A2 (en) | 2002-03-13 |
DE10042270A1 (en) | 2002-03-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE2945331C2 (en) | Device in a signal or data processing system for setting a signal processing circuit | |
DE2853353B2 (en) | Circuit arrangement for processing pulse-shaped signals amplified in an amplifier | |
DE3713821A1 (en) | ISOLATING AMPLIFIER WITH EXACT TIME OF THE SIGNALS COUPLED OVER THE INSULATION BARRIER | |
DE60026962T2 (en) | Adjustable harmonic distortion detector and method using this detector | |
DE2727201A1 (en) | TOUCH CONTROL BUTTONS | |
DE2027544C3 (en) | ||
EP1187330B1 (en) | Voltage comparator circuit for the envelope of an AC voltage and method of comparing | |
DE3026715C2 (en) | ||
DE2210152B2 (en) | In its frequency voltage controllable sawtooth generator | |
DE2512612C2 (en) | Search circuit | |
DE3148242A1 (en) | CABLE EQUALIZER CIRCUIT | |
DE112007000795T5 (en) | Jitter amplifier, jitter enhancement method, electronic device, tester and test method | |
DE2522504A1 (en) | RECIPIENTS | |
EP1257058B1 (en) | Device and method for determining the present logic level of a digital signal | |
DE19616214B4 (en) | Apparatus for controlling the amplitude of a frequency modulated signal using a PLL | |
DE2521403A1 (en) | CIRCUIT ARRANGEMENT FOR SYNCHRONIZING AN OUTPUT SIGNAL IN THE CYCLE OF A PERIODIC PULSE-SHAPED INPUT SIGNAL | |
DE2238964C3 (en) | Frequency control arrangement | |
EP0727897B1 (en) | Circuit for receiving a signal transmitted on a bus as voltage level variations | |
CH631845A5 (en) | DEVICE FOR LEVEL CONTROL IN AM-PM RECEIVERS. | |
EP0022558B1 (en) | Circuit arrangement for amplitude control in an automatic adaptive time domain equalization of the side lobes of an at least three level base band signal | |
DE3937055C2 (en) | ||
DE10352191B4 (en) | Method and arrangement for converting optical received pulses into electrical output pulses | |
DE19615745A1 (en) | Measuring circuit | |
DE3347484C2 (en) | ||
DE3245344A1 (en) | Circuit arrangement for a receiver for data transmission by means of four-stage phase shift keying |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: 7H 03K 5/08 A Ipc: 7H 03K 5/125 B |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
AX | Request for extension of the european patent |
Extension state: AL LT LV MK RO SI |
|
17P | Request for examination filed |
Effective date: 20040122 |
|
17Q | First examination report despatched |
Effective date: 20040908 |
|
AKX | Designation fees paid |
Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: ALCATEL LUCENT |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: ALCATEL TRANSPORT SOLUTIONS HOLDING GMBH |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
REF | Corresponds to: |
Ref document number: 50113055 Country of ref document: DE Date of ref document: 20071108 Kind code of ref document: P |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: LANGUAGE OF EP DOCUMENT: GERMAN |
|
GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20071025 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070926 |
|
RAP2 | Party data changed (patent owner data changed or rights of a patent transferred) |
Owner name: THALES SECURITY SOLUTIONS & SERVICES GMBH |
|
NLV1 | Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act | ||
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20071227 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070926 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20080106 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FD4D |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20080226 |
|
ET | Fr: translation filed | ||
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20071226 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: CD |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070926 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20080627 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070926 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20080731 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20080731 Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20080731 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070926 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20080731 Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20080725 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070926 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 16 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 17 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 18 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20200713 Year of fee payment: 20 Ref country code: DE Payment date: 20200714 Year of fee payment: 20 Ref country code: FR Payment date: 20200724 Year of fee payment: 20 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: AT Payment date: 20200728 Year of fee payment: 20 Ref country code: IT Payment date: 20200728 Year of fee payment: 20 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R071 Ref document number: 50113055 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: PE20 Expiry date: 20210724 |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK07 Ref document number: 374452 Country of ref document: AT Kind code of ref document: T Effective date: 20210725 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION Effective date: 20210724 |