Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
  • H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
  • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
  • H03F1/0216—Continuous control
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
  • H04B1/40—Circuits
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/02—Transmitters
  • H04B1/04—Circuits
  • H04B2001/0408—Circuits with power amplifiers
  • H04B2001/045—Circuits with power amplifiers with means for improving efficiency

Definitions

• This invention relates to amplifiers. Specifically, the present invention relates to systems and methods for improving the performance of and extending the battery life of wireless phones and accompanying cellular telecommunications systems by selectively controlling power amplifier performance.
• Cellular telecommunications systems are characterized by a plurality of mobile transceivers, such as mobile phones (also called wireless phones, mobile stations, or cellular telephones) in communication with one or more base stations.
• Wireless phones include a transceiver having a transmit section and a receive section.
• RF radio frequency
• IF intermediate frequency
• Signal processing circuits perform noise filtering and adjust the magnitude of the signal via analog automatic gain control (AGC) circuitry.
• AGC analog automatic gain control
• An IF section then mixes the signal down to baseband and converts the analog signal to a digital signal.
• the digital signal is then input to a baseband processor for further signal processing to output voice or data.
• the transmit section receives a digital input from the baseband processor and converts the input to an analog signal. This signal is then filtered and upconverted by an IF stage to an intermediate frequency. The gain of the transmit signal is adjusted and the IF signal is upconverted to ultrahigh frequency (UHF) in preparation for radio transmission.
• UHF ultrahigh frequency
• Wireless phones transfer voice or data signals between other wireless phones or land based telephones via a base station and /or a mobile switching center.
• a public switched telephone network (PSTN) communicates with the base station or mobile switching center and facilitates the routing of signals between land based phones and the wireless network.
• PSTN public switched telephone network
• a large base station may govern a region divided into several cells, each cell associated with a base station transceiver subsystem (BTS). Alternatively, a single base station may govern a particular cell associated with a given geographic region.
• BTS base station transceiver subsystem
• the communications link (forward or reverse link) between a base station or BTS and a mobile station is a fading channel, which is a channel that is severely degraded.
• the degradation results from numerous effects including multipath fading, severe attenuation due to the receipt via multiple paths of reflections of the transmitted signal off objects and structures in the atmosphere and on the surface, and from interference caused by other users of the communications system.
• Other effects contributing to the impairment of the faded channel include Doppler shift due to the movement of the receiver relative to the transmitter and additive noise.
• CDMA code division multiple access
• a WGN additive white Gaussian noise
• the power levels of transmitted communications signals fluctuate in accordance with a Raleigh distribution.
• the power typically fluctuates over a dynamic range of lOdB to 50dB.
• the duration of the fades is a function of the velocity of a mobile station, i.e., cellular telephone, the frequency channel assigned to the mobile station, and overall signal environment. As the velocity of a mobile unit increases, fade duration decreases, leading to shorter error bursts. As the velocity of the mobile unit decreases, fade duration increases, leading to longer error bursts.
• a wireless phone When a wireless phone transmits a signal such as a voice signal to a base station, the requisite power of the transmitted signal depends on the interference characteristics of the channel, which often varies in accordance with the relative proximity of the wireless phone to the associated base station. When in close proximity to a base station, a wireless phone requires less power to effectively communicate with an associated base station.
• the requisite power level of the signal transmitted by the wireless phone varies in accordance with the varying noise and fading characteristics of the channel.
• Some wireless phone technologies fail to account for the varying power requirements and instead broadcast continuously at full power. This results in reduced phone battery life and may contribute to increased channel interference.
• many conventional wireless phones employ automatic gain control circuitry to adjust the gain of the signal in the transmit section.
• the phones may switch between high and low power modes depending on the proximity of the phone with respect to a transmitting base station and /or the interference characteristics of the channel between the base station and the wireless phone.
• the channel introduces less interference to the transmitted signal, and the power level of the transmitted signal is reduced accordingly to save power and extend the battery life and talk time of the wireless phone.
• Wireless phones include additional power amplifiers and filters, whose performance and power consumption vary with temperature as well as signal operating environment. Existing systems fail to effectively control the power consumption and performance of these additional amplifiers and fail to efficiently accommodate temperature variations to maximize phone performance and battery life. Wireless phones often include a power amplifier, whose efficient performance is particularly important for extending battery life and associated talk time.
• the inventive system is adapted for use with code division multiple access
• CDMA Code Division Multiple Access
• CDMA code Division Multiple Access
• a second circuit provides a transmit signal.
• a third circuit amplifies the transmit signal in preparation for transmission.
• the third circuit requires a biasing signal.
• a fourth circuit selectively alters the power dissipated by the third circuit by selectively changing the biasing signal in response to the control signal.
• the fourth circuit includes a circuit for determining a desirable operational mode of the system as indicated by the control signal.
• the fourth circuit is called an efficiency circuit and also includes a circuit for adjusting the biasing signal in accordance with the desirable operational mode of the system.
• a voltage divider circuit in the efficiency circuit has a node between a first impedance circuit and a second impedance circuit.
• the first impedance circuit includes a switch for altering the impedance of the first impedance circuit in accordance with the desirable operational mode.
• the first impedance circuit includes a first resistor in parallel with a second resistor.
• the switch is a transistor for isolating the first resistor or the second resistor from the voltage divider in accordance with the desirable operational mode.
• the first circuit for providing the control signal includes a digital chip or phone modem.
• the digital chip runs software for establishing the control signal in response to the detection of an operating environment of the wireless phone and accompanying system.
• a receiver provides information to the software to help determine the operational mode.
• the mode is a high-power mode or a low-power mode associated with an electrically noisy signal environment or an electrically clear signal environment, respectively, as indicated by the information.
• the second circuit has a transmit path that includes the digital chip connected to an automatic gain control circuit connected to an intermediate frequency to radio frequency mixing circuit that is connected to a filter section.
• the filter section outputs the transmit signal.
• the efficiency circuit selectively controls the power consumption, gain, and /or performance with respect to temperature of the third circuit, which acts as a power amplifier, according to a power-mode of the wireless phone, signal operating environment, and /or temperature.
• control over the performance of the third circuit is greatly enhanced, which results in improved phone battery life and talk time as well as improved performance with respect to variations in temperature.
• Fig. 1 is a diagram of a wireless phone transceiver having an efficiency circuit constructed in accordance with the teachings of the present invention.
• Fig. 2 is a more detailed diagram of the efficiency circuit of Fig. 1.
• Fig. 3 is an alternative embodiment of the efficiency circuit of Fig. 2.
• Fig. 1 is a diagram of a wireless phone transceiver 10 having an efficiency circuit 12 constructed in accordance with the teachings of the present invention. For clarity, several details such as speakers, microphones, vocoders, clocking circuitry, reference oscillators and other circuits of the transceiver 10 have been omitted from Fig. 1. With access to the present teachings, those ordinarily skilled in the art will know where to position and how to implement the additional circuitry.
• the transceiver 10 is implemented as a wireless code division multiple access (CDMA) phone and includes a battery 14 that powers the transceiver 10.
• the transceiver 10 includes a transmit path 16 and a receive path 18.
• CDMA wireless code division multiple access
• the transmit path 16 includes, from left to right, a digital control chip 20, an automatic gain control (AGC) circuit 22, an intermediate frequency (IF) to radio frequency (RF) mixer 24, a driver 28, a power amplifier (PA) 32, an isolator 33, a duplexer 34, and an antenna 36.
• the receive path 18 also includes the antenna 36, the duplexer 34, the digital control chip 20, and further includes a receive section 38 connected between the duplexer 34 and the digital control chip 20.
• the battery 14 is connected to the digital control chip 20, the AGC 22, the mixer 24, the receive section 38, the driver 28, the power amplifier 32, and the efficiency circuit 12.
• An output of the efficiency circuit 12 is connected to a biasing input of the power amplifier 32.
• the duplexer 34 facilitates the sharing of antenna resources between transmitting functions and receiving functions implemented via the transmit path 16 and the receive path 18, respectively.
• the isolator 33 isolates the power amplifier 32 from the antenna 36 and duplexer 34 and prevents power reflection back from the antenna 36 to the power amplifier 32.
• the receive section 38 contains filters and signal mixing and downconversion circuitry (not shown) that prepare the received signal for processing via a baseband processor (not shown) included in the digital control chip 20.
• Those ordinarily skilled in the art can easily design and implement the receive section 38 to suit the needs of a given application.
• the antenna 36, duplexer 34, receive section 38, and the digital control chip 20 implement the receiver portion of the wireless phone transceiver 10.
• the digital control chip 20 includes a digital signal processor known as a baseband processor (not shown), a mobile station modem, and other processing circuitry for running software and controlling the operation of the wireless phone 10.
• the digital control chip 20 includes analog-to-digital converters (ADCs) (not shown) for converting analog signals from the receive path to digital signals and includes digital-to-analog (DACs) (not shown) for converting digital signals from the baseband processor to analog signals in preparation for transmission via the transmit path 16.
• Analog transmit signals from the digital control chip 20 are input to the AGC 22 where the gain of the transmit signals is adjusted in accordance with a power mode of the transceiver 10 as determined via software or hardware in the digital control chip 20 as discussed more fully below.
• the transmit signals are then converted to analog UHF signals via the up-converter 24, which acts as a mixer and is synchronized via oscillators (not shown) to an appropriate UHF frequency.
• the up-converted signals are then filtered and scaled via the first filter 26, the driver 28, and the second filter 30 to remove noise and prepare the transmit signals for transmission.
• the resulting filtered transmit signal is amplified by the power amplifier 32, whose gain and power consumption is controlled via the efficiency circuit 12, which selectively changes a biasing signal 42 to the power amplifier 32 in response to the receipt of a control signal 40 from the digital control chip 20.
• the efficiency circuit 12 also stabilizes the performance of the amplifier 32 with respect to temperature by selectively altering the biasing signal 42 in response to changing temperature.
• the efficiency circuit 12 stabilizes the performance of the amplifier 32 over the temperature range of -30oC to HOoC.
• the digital control chip 20 includes a baseband processor (not shown) that runs conventional software or hardware algorithms to measure a signal amplitude or strength and provide a Receive Signal Strength Indication (RSSI) of the received signal in response thereto.
• the digital control chip 20 then provides the control signal 40 to the efficiency circuit 12 in response to the RSSI measurement. If the RSSI is high as compared to a predetermined threshold, the digital control chip 20 sets the transceiver 10 to a low-power mode by issuing the control signal 40 to the efficiency circuit 12 and providing gain adjustment parameters to the AGC circuit 22. Similarly, if the RSSI is low, the digital control chip 20 sets the transceiver to a high-power mode.
• the power of the signal transmitted from the digital control chip 20 via the transmit path 16 is reduced to account for the high quality of the channel as indicated by the high RSSI measurement.
• the transceiver 10 broadcasts with more power, which is drawn from the battery 14.
• the predetermined threshold is application specific and may be easily adjusted by one ordinarily skilled in the art to meet the needs of a given application.
• the efficiency circuit 12 adjusts the gain and resulting output signal power of the amplifier 32 by controlling the biasing signal 42. In the present specific embodiment, when the control signal 40 is in a low voltage state, the magnitude of the biasing signal 42 increases, which increases the gain and power consumption of the amplifier 32. Similarly, when the control signal 40 is in a high voltage state, the magnitude of the biasing signal 42 decreases.
• the biasing signal 42 is a current signal when the power amplifier 32 is a heteroj unction bipolar junction transistor (HBT) amplifier.
• the biasing signal 42 is a voltage signal when the power amplifier is a GaAs field-effect transistor amplifier (GaAs FET).
• Fig. 2 is a more detailed diagram of the efficiency circuit 12 of Fig. 1.
• the battery 14 of Fig. 1 provides a varying battery voltage (Ncc) to a regulator 43, which regulates the varying voltage Ncc and provides an approximately constant voltage (Nreg) at a node 13 connected to a first end of a first resistor Rl and to a first end of a second resistor R2.
• a second end of the first resistor Rl is connected to a negative input terminal of an operational amplifier 50 and to a source of a p-channel metal oxide semiconductor field-effect transistor (MOSFET) 52.
• MOSFET metal oxide semiconductor field-effect transistor
• the gate of the p-channel MOSFET 52 is connected to an output of the operational amplifier 50.
• the drain of the p-channel MOSFET 52 is connected to the power amplifier 32 and provides the biasing signal Iref 42 to a biasing terminal of the power amplifier 32.
• the power amplifier 32 is implemented as an HBT amplifier.
• the operational amplifier 50 is biased via standard circuitry (not shown) that operates in accordance with methods known in the art.
• a positive input terminal of the operational amplifier 50 is connected at a node 15 that connects a second end of the second resistor R2, a first end of a fourth resistor R4, and a first end of a fifth resistor R5.
• a second end of the fifth resistor R5 is connected to ground.
• a second end of the fourth resistor R4 is connected to an emitter of pnp bipolar junction transistor (BJT) 54.
• a collector of the pnp BJT 54 is connected to ground.
• the control signal 40 (Vcontrol) from the digital control chip 20 of Fig. 1 is provided to a first end of a third resistor R3.
• a second end of the third resistor R3 is connected to the base of the pnp BJT 54.
• the pnp BJT 54 acts as a switch that selectively connects the second end of the fourth resistor R4 to ground in response to a low voltage state provided via the control signal (Ncontrol) to a base of the pnp BJT 54 via the resistor R3.
• the transistor 54 may be replaced with another type of switch without departing from the scope of the present invention.
• the operation of the efficiency circuit 12 is such that when the control signal Ncontrol 40 is in a low voltage state, such as 0 volts, the reference signal Iref is a function of the constant voltage Nreg provided by the regulator 43 of Fig. 1 as described by the following equation:
• R4/ /R5 is the parallel operation defined in accordance with the following equation:
• Ncc represents the voltage output by the battery 14 of Fig. 1, which may vary over the charging cycle of the battery 14, while Nreg represents the constant DC reference voltage output from the voltage regulator 43.
• the reference signal Iref is a function of the constant voltage Vreg as described by the following equation:
• the control signal 40 selectively isolates R4 from the efficiency circuit 12 when the control signal 40 is in a high voltage state.
• the lack of the contribution of R4 causes a corresponding increase in the voltage (V+) at the positive input terminal of the operational amplifier 50 and an increase in the voltage (V-) at the negative input terminal of the operational amplifier 50.
• the increased voltage decreases the current flowing through the first resistor Rl (in accordance with Ohm's Law) and hence through the source and drain of the p- channel MOSFET 52. As a result, the current Iref decreases.
• the fourth resistor R4 and the fifth resistor R5 form a first impedance circuit 57 that is connected to a second impedance circuit 59 at the node 15.
• the second impedance circuit 59 includes the first resistor Rl, the second resistor R2, and the node 13 therebetween.
• the resistance of the first impedance circuit 57 is selectively changed via the transistor 54 and the control signal 40. When the transistor 54 is on, the resistance of the first impedance circuit 57 is approximated by equation (2). When the transistor 54 is off, the fourth resistor R4 is isolated, and the resistance or impedance of the first impedance circuit 57 is the value of the fifth resistor R5.
• the biasing signal 42 i.e., the current Iref delivered to the power amplifier 32 is controlled.
• the resistance of the p-channel MOSFET 52 changes with temperature and helps to stabilize the performance of the amplifier 32 in operating environments characterized by temperature extremes.
• the p-channel MOSFET 52 may be replaced with another type of transistor or variable resistor without departing from the scope of the present invention.
• control signal 40 required to turn on and off the pnp BJT 54, respectively, depend on transistor parameters, which may be chosen by those ordinarily skilled in the art to meet the needs of a given application.
• Fig. 3 is an alternative embodiment 60 of the efficiency circuit 12 of Fig. 1.
• the voltage Vcc from the battery 14 of Fig. 1 is provided to a voltage inverter 64, to a first biasing terminal of the operational amplifier 50, and to an input of a precision voltage reference generator 66.
• An output of the inverter 64 is connected to a second biasing terminal of the operational amplifier 50.
• An output of the precision voltage reference generator 66 is connected to a first end of a sixth resistor R6 and to a first end of a seventh resistor R7 and provides a precision voltage reference Vref.
• a second end of the sixth resistor R6 is connected to a switch 68, which may be implemented as an n-channel FET.
• the second end of the sixth resistor R6 is connected to a first end (such as to a drain of an n-channel FET) of the switch 68.
• the control signal 40 is provided to a control terminal (such as the gate of an n-channel FET) of the switch 68, which selectively connects, in response to the control signal 40, the second end of the sixth resistor R6 to a node 69.
• the node 69 is connected to a negative input terminal of the operational amplifier 50, to a second end of the seventh resistor R7 and to a first end of an eighth resistor R8.
• the node 69 is connected to a second end (such as the source (S) of an n-channel FET) of the switch 68.
• a second end of the eighth resistor R8 is connected to an output terminal of the operational amplifier 50 and to a biasing terminal of a metal semiconductor field-effect transistor (MESFET) amplifier 32', which in the present specific embodiment is a GaAs FET amplifier.
• a positive input terminal of the operational amplifier 50 is connected to a ground.
• the precision voltage Vref is a constant voltage whose value is application-specific and may or may not be equivalent to the constant voltage Vreg of Fig. 2 output from the voltage regulator 43 of Fig. 2.
• Vref and Vreg are highly stable and accurate DC reference voltages of predetermined values. Those ordinarily skilled in the art can easily determine an appropriate value for Vref or Vreg to meet the needs of given application.
• the precision voltage reference generator 66 may be constructed by one skilled in the art from a voltage regulator, a voltage scaling circuit, or other similar circuitry.
• the voltage Vcc provided by the battery 14 of Fig. 1 is provided to the first biasing terminal of the operational amplifier 50 and to the inverter 64.
• the inverter 64 inverts the voltage +Vcc and provides a negative battery voltage -Ncc to a second biasing terminal of the operational amplifier 50.
• the voltage reference Vref is a highly stable and accurate DC voltage of a predetermined value.
• the predetermined voltage value is application-specific and may easily be determined by one ordinarily skilled in the art to meet the needs of a given application.
• the switch 60 is switched in and out in response to a high voltage state or a low voltage state respectively, provided to the control terminal of the switch 68 via the control signal 40.
• the switch 68 may be implemented with a transistor such as a FET.
• the biasing signal i.e., voltage (Vgg) provided to the GaAs FET amplifier 32' is a function of the precision voltage reference Vref as described by the following equation:
• the sixth resistor R6 and the second resistor R7 are part of a first impedance circuit 57'.
• the eighth resistor R8 represents a second impedance circuit 59', which is connected to the first impedance circuit 57' at the node 69.
• the resistance of the first impedance circuit 57' is selectively changed via the switch
• the switch 68 When the switch 68 is on, the resistance of the first impedance circuit 57' is approximately R61 I R7. When the switch 68 is off, the sixth resistor R6 is isolated, and the resistance of the first impedance circuit 57' is the value of the seventh resistor R7.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Transmitters (AREA)
• Transceivers (AREA)
• Amplifiers (AREA)
• Circuits Of Receivers In General (AREA)

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• 2000
  • 2000-04-13 KR KR1020017013198A patent/KR20020005686A/ko not_active Application Discontinuation
  • 2000-04-13 AU AU44632/00A patent/AU4463200A/en not_active Abandoned
  • 2000-04-13 CA CA002370209A patent/CA2370209A1/en not_active Abandoned
  • 2000-04-13 WO PCT/US2000/010239 patent/WO2000064062A1/en not_active Application Discontinuation
  • 2000-04-13 JP JP2000613085A patent/JP2002542708A/ja active Pending
  • 2000-04-13 CN CN00807791A patent/CN1352826A/zh active Pending
  • 2000-04-13 EP EP00926034A patent/EP1175732A1/en not_active Withdrawn

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