EP1126351B1 - Circuit for producing a constant voltage - Google Patents

Circuit for producing a constant voltage Download PDF

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Publication number
EP1126351B1
EP1126351B1 EP20010101805 EP01101805A EP1126351B1 EP 1126351 B1 EP1126351 B1 EP 1126351B1 EP 20010101805 EP20010101805 EP 20010101805 EP 01101805 A EP01101805 A EP 01101805A EP 1126351 B1 EP1126351 B1 EP 1126351B1
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Prior art keywords
transistor
emitter
terminals
transistors
current
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German (de)
French (fr)
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EP1126351A1 (en
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Wolfgang Horn
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Infineon Technologies AG
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Infineon Technologies AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to a circuit arrangement for generating constant voltages according to the bandgap principle (bandgap principle), in which the forward voltages of two P-N junctions are used to generate a reference voltage, according to the preamble of claim 1.
  • bandgap principle bandgap principle
  • a further problem can result, for example, according to FIG. 1 in the case of a barrier-layer-isolated mixing technology on a p-substrate 13.
  • the diode formed from an n-type drain terminal 11 and the p-type substrate 13 becomes conductive, and the charge carriers injected into the substrate 13 form the emitter current of a parasitic npn bipolar junction transistor 12.
  • All epitaxial n-wells 10a, ... 10x (for example BJT collectors) of the circuit represent for this transistor 12 potential collectors from which collector currents Icl, .. Icx can be subtracted during reverse operation of the DMOS power transistor.
  • This can lead to sensitive other circuit parts with high impedance connected n-wells, such as a circuit arrangement of the type mentioned in the band-gap principle, be impaired in their function or even fail completely.
  • EP-A-0 680 048 A1 describes a reference voltage circuit operating according to the bandgap principle which has two bipolar transistors whose collector terminals are connected to a supply potential and whose base terminals are short-circuited and likewise connected to the supply potential via a resistor.
  • the emitter terminals of the two bipolar transistors are connected to a circuit arrangement for adjusting the currents through the bipolar transistors to reference potential.
  • the resistor connected to the base terminal of the bipolar transistors is likewise connected to reference potential via a transistor of this circuit device.
  • EP-A-0 329 247 A1 and US-A-4,348,633 describe further bandgap-mode reference voltage circuits.
  • the invention has for its object to provide a circuit arrangement which produces a temperature and operating voltage independent constant voltage with a bandgap reference in other limits and which is particularly insensitive to influences of the reverse operation described above.
  • the object is achieved according to claim 1 with a circuit arrangement of the type mentioned, which is characterized by the following features: a first and a second transistor whose base terminals are connected to each other via a first resistor and whose collector terminals are applied to a supply voltage, and a second resistor , which is connected between the base terminal of the first transistor and the supply voltage, so that by the difference of the base-emitter voltages across the transistors through the first and second resistor is generated according to ground flowing reference current, and a reference to the supply voltage sourced reference voltage at the emitter of the first transistor can be tapped.
  • an output buffer / driver is provided, with which the reference voltage is divided and passed at low impedance at an output.
  • the circuit arrangement preferably comprises a comparator with a current mirror circuit with which the emitter currents of the first and second transistors and the reference current are regulated to an equilibrium state in which these currents are substantially equal.
  • an actuator is provided with a start circuit for acting on the comparator, which has a third transistor, with which a voltage or current difference at the emitter terminals of the first and second transistor is controlled by driving a fourth and fifth transistor in the comparator.
  • the embodiment according to the invention comprises a bandgap circuit 1 for generating a reference voltage according to the bandgap principle, which is related to a positive supply voltage Vdd, an output buffer / driver 4 whose input is connected to the output of the bandgap circuit 1 and to the latter Output is applied to an output reference voltage Vref, a current and voltage comparator 2, which is insensitive to reverse current and is connected via a first and a second terminal A, B to the bandgap circuit 1, and an actuator 3 with start circuit, which acts on the comparator 2 ,
  • the reference voltage generated by the bandgap circuit 1 is divided to almost any desired values (for example ⁇ 1.26 volts) and provided at the output with low resistance.
  • the comparator 2 controls by means of the actuator 3, the bandgap circuit 1, wherein the condition to be met for the controlled state is the equality of the voltages at the two terminals A, B and the equality of the currents I1, I2 through these terminals.
  • FIG. 3 shows an overall circuit diagram of the preferred embodiment, wherein these components are each delimited by dashed lines.
  • the bandgap circuit 1 comprises a first and a second npn bipolar transistor T1, T2, whose base terminals are connected to each other via a first resistor R1.
  • the collector terminals are connected to a positive supply voltage Vdd, while the emitter terminal of the first transistor T1 is connected to the first terminal A and the emitter terminal of the second transistor T2 to the second terminal B.
  • the base terminal of the first transistor T1 is finally connected via a second resistor R2 to the supply voltage Vdd.
  • the comparator 2 comprises a fourth and a fifth bipolar pnp transistor T4, T5, whose base terminals are interconnected, wherein the emitter of the fourth transistor T4 via the second terminal B to the emitter of the second transistor T2 and the emitter of the fifth transistor T5 via the first terminal A is connected to the emitter of the first transistor T1.
  • the collector of the fifth transistor T5 is connected to ground via a first (eg MOSFET) transistor M1 and to a gate of this transistor M1.
  • the collector of the fourth transistor T4 is grounded via a third MOSFET transistor M3.
  • a second MOSFET transistor M2 is provided which allows a reference current Iref to flow from the base of the second transistor T2 to ground.
  • a temperature-independent bias current I BIAS can be generated to ground via a tenth MOSFET transistor M10 and coupled out as required.
  • the circuit arrangement can thus additionally as a generator for a temperature-compensated bias current I BIAS for the relevant chip serve and thus include an inherent "auto-biasing".
  • the bases of the MOSFET transistors M1, M2, M3, M10 are connected together.
  • the actuator 3 comprises a third npn bipolar transistor T3 whose collector is connected to the positive supply voltage Vdd and its emitter to the interconnected base terminals of the fourth and fifth transistors T4, T5 and via a third resistor R3 to ground. Between the supply voltage Vdd and ground, a fourth and a seventh MOSFET transistor M4, M7 are connected in series, between which the base of the third transistor T3 is located. The gate of the fourth MOSFET transistor M4 is connected to the collector of the fourth transistor T4, the gate of the seventh MOSFET transistor M7 is connected to the gate of an eighth MOSFET transistor M8 connected in series with a ninth MOSFET transistor M9 between the supply voltage Vdd and mass is.
  • the gate of the seventh and eighth MOSFET transistors M7, M8 is connected between the eighth and ninth MOSFET transistors M8, M9.
  • the gate of the ninth MOSFET transistor M9 is connected to the interconnected gate terminals of the first, second, third and tenth MOSFET transistors M1, M2, M3, M10.
  • the output buffer / driver 4 comprising a sixth bipolar PNP transistor T6, whose emitter via a series connection of a fourth and fifth resistor R4, R5 to the supply voltage Vdd and its collector via a fifth MOSFET transistor M5 Mass is connected. The emitter is also connected via a sixth MOSFET transistor M6 to ground whose gate is connected to the collector of the sixth transistor T6.
  • the base of the fifth MOSFET transistor M5 is in turn connected to the interconnected gate terminals of the first, second, third, ninth and tenth MOSFET transistors M1, M2, M3, M9, M10.
  • the reference voltage Vref is tapped at the voltage divider formed by the fourth and fifth resistors R4, R5.
  • An essential core of the invention is the implementation of the bandgap principle in the bandgap circuit 1, which is also independent, that is, without the circuit parts 2 to 4 can be used. However, it is particularly suitable for use in combination with the comparator 2, through which the insensitivity of the overall circuit compared to the aforementioned reverse currents results. Furthermore, the temperature response of the difference between the two base-emitter voltages of T1 and T2 dU BE is compensated with the current-determining first resistor R1, so that the reference current Iref is temperature-independent.
  • the circuit is self-sufficient, resulting in two possible operating points, on the one hand a desired and on the other hand such an operating point, in which the reference current Iref is equal to zero and the reference voltage Vref is equal to the positive supply voltage Vdd.
  • the starting circuit which is often difficult to implement in known circuits having this property, is integrated according to the invention into the actuator 3, without requiring a substantial additional outlay.
  • the reference voltage results as the sum of the voltage drop across the second resistor R2 generated by the reference current Iref and the voltage U BE at the base-emitter diode of the first transistor T1.
  • the reference voltage Vref can be tapped off at the first terminal A and related to the positive supply voltage Vdd.
  • the comparator 2 controls in conjunction with the actuator 3, the bandgap circuit 1 always to this equilibrium state, in which the reference current Iref equal to the first and the second current I1, I2 (emitter current of the first and second transistor T1, T2) through the first and second terminal A, B is.
  • This current condition is realized by the current mirror circuit formed by the first to third MOSFET transistors M1, M2, M3.
  • T4, T5 By the upstream of the current mirror pnp transistors T4, T5, a potential difference at the terminals A, B directly results in a current difference and is therefore also regulated.
  • This control process takes place in detail as follows:
  • the third resistor R3 forms a current sink for the third transistor T3 and simultaneously acts as a starting resistor by pulling in the de-energized state, the base terminals of the fourth to sixth transistor T4, T5, T6 to ground and thus excludes the undesirable operating point.
  • the optional output buffer / driver 4 drives the sixth transistor T6 with a base potential and an emitter current which is identical to those at the fourth and fifth transistor T4, T5.
  • the emitter potential corresponds to the potential at the first and second terminals A, B and thus the reference voltage Vref.
  • the requirement of the identical emitter current is met by the fifth and sixth MOSFET transistor M5, M6.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Description

Die Erfindung betrifft eine Schaltungsanordnung zur Erzeugung von Konstantspannungen nach dem Bandgap-Prinzip (Bandabstands-Prinzip), bei dem die Durchflußspannungen zweier P-N-Übergänge zur Erzeugung einer Referenzspannung eingesetzt werden, gemäss dem Oberbegriff von Anspruch 1.The invention relates to a circuit arrangement for generating constant voltages according to the bandgap principle (bandgap principle), in which the forward voltages of two P-N junctions are used to generate a reference voltage, according to the preamble of claim 1.

Ein mit diesen Schaltungen verbundenes Problem besteht darin, dass der Temperaturkoeffizient der Basis-Emitter-Spannung relativ hoch ist und kompensiert werden muß. Zu diesem Zweck ist es zum Beispiel aus "Tietze, Schenk: Halbleiter-Schaltungstechnik" bekannt, mit einem zweiten Transistor eine Spannung mit einem Temperaturkoeffizienten zu erzeugen, der den gleichen Betrag, jedoch entgegengesetztes Vorzeichen aufweist und diese Spannung der Referenzspannung hinzuzuaddieren.A problem associated with these circuits is that the temperature coefficient of the base-emitter voltage is relatively high and must be compensated. For this purpose, for example, it is known from "Tietze, Schenk: Semiconductor Circuitry" to generate with a second transistor a voltage having a temperature coefficient which has the same magnitude but opposite sign and to add this voltage to the reference voltage.

Ein weiteres Problem kann sich zum Beispiel gemäss Figur 1 bei einer sperrschichtisolierten Mischtechnologie auf einem p-Substrat 13 ergeben. Dabei wird bei einer Polaritätsumkehr an einem DMOS-Leistungstransistor (Reversbetrieb) die aus einem n-leitenden Drainanschluss 11 und dem p-Substrat 13 gebildete Diode leitend, und die in das Substrat 13 injizierten Ladungsträger bilden den Emitterstrom eines parasitären bipolaren npn-Flächentransistors 12. Alle epitaxialen n-Wannen 10a, ...10x (zum Beispiel BJT-Kollektoren) der Schaltung stellen für diesen Transistor 12 potentielle Kollektoren dar, aus denen beim Reversbetrieb des DMOS-Leistungstransistors Kollektorströme Icl,.. Icx abgezogen werden können. Dies kann dazu führen, dass empfindliche andere Schaltungsteile mit hochohmig angeschlossenen n-Wannen, wie zum Beispiel eine Schaltungsanordnung der eingangs genannten Art nach dem Band-gap-Prinzip, in ihrer Funktion beeinträchtigt werden oder sogar völlig ausfallen.A further problem can result, for example, according to FIG. 1 in the case of a barrier-layer-isolated mixing technology on a p-substrate 13. At a polarity reversal on a DMOS power transistor (reverse operation), the diode formed from an n-type drain terminal 11 and the p-type substrate 13 becomes conductive, and the charge carriers injected into the substrate 13 form the emitter current of a parasitic npn bipolar junction transistor 12. All epitaxial n-wells 10a, ... 10x (for example BJT collectors) of the circuit represent for this transistor 12 potential collectors from which collector currents Icl, .. Icx can be subtracted during reverse operation of the DMOS power transistor. This can lead to sensitive other circuit parts with high impedance connected n-wells, such as a circuit arrangement of the type mentioned in the band-gap principle, be impaired in their function or even fail completely.

Die EP-A-0 680 048 A1 beschreibt eine nach dem Bandgap-Prinzip funktionierende Referenzspannungsschaltung die zwei Bipolartransistoren aufweist, deren Kollektoranschlüsse an einem Versorgungspotential liegen und deren Basisanschlüsse kurzgeschlossen und über einen Widerstand ebenfalls an Versorgungspotential angeschlossen sind. Die Emitteranschlüsse der beiden Bipolartransistoren sind an eine Schaltungsanordnung zum einstellen der Ströme durch die Bipolartransistoren an Bezugspotential angeschlossen. Der an den Basisanschluss der Bipolartransistoren angeschlossene Widerstand ist über einen Transistor dieser Schaltungseinrichtung ebenfalls an Bezugspotential angeschlossen.EP-A-0 680 048 A1 describes a reference voltage circuit operating according to the bandgap principle which has two bipolar transistors whose collector terminals are connected to a supply potential and whose base terminals are short-circuited and likewise connected to the supply potential via a resistor. The emitter terminals of the two bipolar transistors are connected to a circuit arrangement for adjusting the currents through the bipolar transistors to reference potential. The resistor connected to the base terminal of the bipolar transistors is likewise connected to reference potential via a transistor of this circuit device.

Die EP-A-0 329 247 A1 und US-A-4,348,633 beschreiben weitere nach dem Bandgap-Prinzip funktionierende Referenzspannungsschaltungen.EP-A-0 329 247 A1 and US-A-4,348,633 describe further bandgap-mode reference voltage circuits.

Der Erfindung liegt die Aufgabe zugrunde, eine Schaltungsanordnung zu schaffen, die eine in weiteren Grenzen temperatur- und betriebsspannungsunabhängige Konstantspannung mit einer Bandabstands-Referenz erzeugt und die insbesondere unempfindlich gegen Einflüsse des oben beschriebenen Reversbetriebes ist.The invention has for its object to provide a circuit arrangement which produces a temperature and operating voltage independent constant voltage with a bandgap reference in other limits and which is particularly insensitive to influences of the reverse operation described above.

Gelöst wird die Aufgabe gemäß Anspruch 1 mit einer Schaltungsanordnung der eingangs genannten Art, die sich durch folgende Merkmale auszeichnet: einen ersten und einen zweiten Transistor, deren Basisanschlüsse über einen ersten Widerstand miteinander verbunden sind und deren Kollektoranschlüsse an einer Versorgungsspannung anliegen, sowie einen zweiten Widerstand, der zwischen den Basisanschluss des ersten Transistors und die Versorgungsspannung geschaltet ist, so dass durch die Differenz der Basis-Emitter-Spannungen an den Transistoren ein durch den ersten und zweiten Widerstand nach Masse fließender Referenzstrom erzeugt wird, und eine auf die Versorgungsspannung besogene Referenzspannung an dem Emitter des ersten Transistors abgreifbar ist.The object is achieved according to claim 1 with a circuit arrangement of the type mentioned, which is characterized by the following features: a first and a second transistor whose base terminals are connected to each other via a first resistor and whose collector terminals are applied to a supply voltage, and a second resistor , which is connected between the base terminal of the first transistor and the supply voltage, so that by the difference of the base-emitter voltages across the transistors through the first and second resistor is generated according to ground flowing reference current, and a reference to the supply voltage sourced reference voltage at the emitter of the first transistor can be tapped.

Die Unteransprüche haben vorteilhafte Weiterbildungen der Erfindung zum Inhalt.The dependent claims have advantageous developments of the invention to the content.

Danach ist insbesondere ein Ausgangspuffer / Treiber vorgesehen, mit dem die Referenzspannung geteilt und niederohmig an einem Ausgang geführt wird.After that, in particular, an output buffer / driver is provided, with which the reference voltage is divided and passed at low impedance at an output.

Ferner umfasst die Schaltungsanordnung vorzugsweise einen Komparator mit einer Stromspiegelschaltung, mit der die Emitterströme des ersten und zweiten Transistors sowie der Referenzstrom in einen Gleichgewichtszustand geregelt werden, in dem diese Ströme im wesentlichen gleich sind.Furthermore, the circuit arrangement preferably comprises a comparator with a current mirror circuit with which the emitter currents of the first and second transistors and the reference current are regulated to an equilibrium state in which these currents are substantially equal.

Weiterhin ist vorzugsweise ein Stellglied mit einer Startschaltung zur Beaufschlagung des Komparators vorgesehen, das einen dritten Transistor aufweist, mit dem eine Spannungs- oder Stromdifferenz an den Emitteranschlüssen des ersten und zweiten Transistors durch Ansteuerung eines vierten und fünften Transistors in dem Komparator ausgeregelt wird.Furthermore, an actuator is provided with a start circuit for acting on the comparator, which has a third transistor, with which a voltage or current difference at the emitter terminals of the first and second transistor is controlled by driving a fourth and fifth transistor in the comparator.

Weitere Einzelheiten, Merkmale und Vorteile der Erfindung ergeben sich aus der folgenden Beschreibung einer bevorzugten Ausführungsform anhand der Zeichnung. Es zeigt:

  • Fig. 1 eine schematische Darstellung zur Erläuterung der sich bei einem Reversbetrieb ergebenden Probleme;
  • Fig. 2 ein Blockschaltbild einer erfindungsgemässen Ausführungsform; und
  • Fig. 3 ein Schaltbild der in Figur 2 gezeigten Ausführungsform.
Further details, features and advantages of the invention will become apparent from the following description of a preferred embodiment with reference to the drawing. It shows:
  • Fig. 1 is a schematic representation for explaining the resulting in a reverse operation problems;
  • FIG. 2 is a block diagram of an embodiment according to the invention; FIG. and
  • Fig. 3 is a circuit diagram of the embodiment shown in Figure 2.

Die erfindungsgemässe Ausführungsform umfasst gemäss Figur 2 eine Bandgap-Schaltung 1 zur Erzeugung einer Referenzspanung nach dem Bandabstandsprinzip, die auf eine positive Versorgungsspannung Vdd bezogen ist, einen Ausgangspuffer / Treiber 4, dessen Eingang mit dem Ausgang der Bandgap-Schaltung 1 verbunden ist und an dessen Ausgang eine Ausgangs-Referenzspannung Vref anliegt, einen Strom- und Spannungskomparator 2, der reversstromunempfindlich ist und über eine erste und eine zweite Klemme A, B mit der Bandgap-Schaltung 1 verbunden ist, sowie ein Stellglied 3 mit Startschaltung, das den Komparator 2 beaufschlagt.According to FIG. 2, the embodiment according to the invention comprises a bandgap circuit 1 for generating a reference voltage according to the bandgap principle, which is related to a positive supply voltage Vdd, an output buffer / driver 4 whose input is connected to the output of the bandgap circuit 1 and to the latter Output is applied to an output reference voltage Vref, a current and voltage comparator 2, which is insensitive to reverse current and is connected via a first and a second terminal A, B to the bandgap circuit 1, and an actuator 3 with start circuit, which acts on the comparator 2 ,

Mit dem Ausgangspuffer / Treiber 4 wird die von der Bandgap-Schaltung 1 erzeugte Referenzspannung auf nahezu beliebige Werte (zum Beispiel < 1,26 Volt) geteilt und am Ausgang niederohmig zur Verfügung gestellt. Der Komparator 2 regelt mit Hilfe des Stellgliedes 3 die Bandgap-Schaltung 1 aus, wobei die für den ausgeregelten Zustand zu erfüllende Bedingung die Gleichheit der Spannungen an den beiden Klemmen A, B sowie die Gleichheit der Ströme I1, I2 durch diese Klemmen ist.With the output buffer / driver 4, the reference voltage generated by the bandgap circuit 1 is divided to almost any desired values (for example <1.26 volts) and provided at the output with low resistance. The comparator 2 controls by means of the actuator 3, the bandgap circuit 1, wherein the condition to be met for the controlled state is the equality of the voltages at the two terminals A, B and the equality of the currents I1, I2 through these terminals.

Figur 3 zeigt ein Gesamtschaltbild der bevorzugten Ausführungsform, wobei diese Komponenten jeweils durch gestrichelte Linien abgegrenzt sind.FIG. 3 shows an overall circuit diagram of the preferred embodiment, wherein these components are each delimited by dashed lines.

Die Bandgap-Schaltung 1 umfaßt einen ersten und einen zweiten bipolaren npn-Transistor T1, T2, deren Basisanschlüsse über einen ersten Widerstand R1 miteinander verbunden sind. Die Kollektoranschlüsse liegen an einer positiven Versorgungsspannung Vdd an, während der Emitteranschluss des ersten Transistors T1 an die erste Klemme A und der Emitteranschluss des zweiten Transistors T2 an die zweite Klemme B geführt ist. Der Basisanschluss des ersten Transistors T1 ist schließlich über einen zweiten Widerstand R2 mit der Versorgungsspannung Vdd verbunden.The bandgap circuit 1 comprises a first and a second npn bipolar transistor T1, T2, whose base terminals are connected to each other via a first resistor R1. The collector terminals are connected to a positive supply voltage Vdd, while the emitter terminal of the first transistor T1 is connected to the first terminal A and the emitter terminal of the second transistor T2 to the second terminal B. The base terminal of the first transistor T1 is finally connected via a second resistor R2 to the supply voltage Vdd.

Der Komparator 2 umfaßt einen vierten und einen fünften bipolaren pnp-Transistor T4, T5, deren Basisanschlüsse miteinander verbunden sind, wobei der Emitter des vierten Transistors T4 über die zweite Klemme B mit dem Emitter des zweiten Transistors T2 und der Emitter des fünften Transistors T5 über die erste Klemme A mit dem Emitter des ersten Transistors T1 verbunden ist. Der Kollektor des fünften Transistors T5 ist über einen ersten (z.B. MOSFET-) Transistor M1 mit Masse sowie mit einem Gate dieses Transistors M1 verbunden. Der Kollektor des vierten Transistors T4 liegt über einen dritten MOSFET-Transistor M3 an Masse. Weiterhin ist ein zweiter MOSFET-Transistor M2 vorgesehen, der einen Referenzstrom Iref von der Basis des zweiten Transistors T2 nach Masse fließen läßt. Über einen zehnten MOSFET-Transistor M10 kann schließlich ein temperaturunabhängiger Bias-Strom IBIAS nach Masse erzeugt und bei Bedarf ausgekoppelt werden. Die Schaltungsanordnung kann somit zusätzlich als Generator für einen temperaturkompensierten Biasstrom IBIAS für den betreffenden Chip dienen und umfaßt auf diese Weise ein inherentes "Auto-Biasing". Die Basisanschlüsse der MOSFET-Transistoren M1, M2, M3, M10 sind miteinander verbunden.The comparator 2 comprises a fourth and a fifth bipolar pnp transistor T4, T5, whose base terminals are interconnected, wherein the emitter of the fourth transistor T4 via the second terminal B to the emitter of the second transistor T2 and the emitter of the fifth transistor T5 via the first terminal A is connected to the emitter of the first transistor T1. The collector of the fifth transistor T5 is connected to ground via a first (eg MOSFET) transistor M1 and to a gate of this transistor M1. The collector of the fourth transistor T4 is grounded via a third MOSFET transistor M3. Furthermore, a second MOSFET transistor M2 is provided which allows a reference current Iref to flow from the base of the second transistor T2 to ground. Finally, a temperature-independent bias current I BIAS can be generated to ground via a tenth MOSFET transistor M10 and coupled out as required. The circuit arrangement can thus additionally as a generator for a temperature-compensated bias current I BIAS for the relevant chip serve and thus include an inherent "auto-biasing". The bases of the MOSFET transistors M1, M2, M3, M10 are connected together.

Das Stellglied 3 umfaßt einen dritten bipolaren npn-Transistor T3, dessen Kollektor mit der positiven Versorgungsspannung Vdd und dessen Emitter mit den zusammengeschalteten Basisanschlüssen des vierten und fünften Transistors T4, T5 sowie über einen dritten Widerstand R3 mit Masse verbunden ist. Zwischen die Versorgungsspannung Vdd und Masse sind ein vierter und ein siebter MOSFET-Transistor M4, M7 in Reihe geschaltet, wobei zwischen diesen die Basis des dritten Transistors T3 liegt. Das Gate des vierten MOSFET-Transistors M4 ist mit dem Kollektor des vierten Transistors T4, das Gate des siebten MOSFET-Transistors M7 ist mit dem Gate eines achten MOSFET-Transistors M8 verbunden, der in Reihe mit einem neunten MOSFET-Transistor M9 zwischen der Versorgungsspannung Vdd und Masse liegt. Das Gate des siebten und achten MOSFET-Transistors M7, M8 ist zwischen den achten und neunten MOSFET-Transistor M8, M9 geschaltet. Das Gate des neunten MOSFET-Transistors M9 ist mit den zusammengeschalteten Gateanschlüssen des ersten, zweiten, dritten und zehnten MOSFET-Transistors M1, M2, M3, M10 verbunden.The actuator 3 comprises a third npn bipolar transistor T3 whose collector is connected to the positive supply voltage Vdd and its emitter to the interconnected base terminals of the fourth and fifth transistors T4, T5 and via a third resistor R3 to ground. Between the supply voltage Vdd and ground, a fourth and a seventh MOSFET transistor M4, M7 are connected in series, between which the base of the third transistor T3 is located. The gate of the fourth MOSFET transistor M4 is connected to the collector of the fourth transistor T4, the gate of the seventh MOSFET transistor M7 is connected to the gate of an eighth MOSFET transistor M8 connected in series with a ninth MOSFET transistor M9 between the supply voltage Vdd and mass is. The gate of the seventh and eighth MOSFET transistors M7, M8 is connected between the eighth and ninth MOSFET transistors M8, M9. The gate of the ninth MOSFET transistor M9 is connected to the interconnected gate terminals of the first, second, third and tenth MOSFET transistors M1, M2, M3, M10.

Schließlich ist im linken Schaltungsteil der Ausgangspuffer /Treiber 4 realisiert, der einen sechsten bipolaren pnp-Transistor T6 umfaßt, dessen Emitter über eine Reihenschaltung eines vierten und fünften Widerstandes R4, R5 mit der Versorgungsspannung Vdd und dessen Kollektor über einen fünften MOSFET-Transistor M5 mit Masse verbunden ist. Der Emitter liegt außerdem über einen sechsten MOSFET-Transistor M6 an Masse, dessen Gate mit dem Kollektor des sechsten Transistors T6 verbunden ist. Die Basis des fünften MOSFET-Transistors M5 ist wiederum mit den zusammengeschalteten Gateanschlüssen des ersten, zweiten, dritten, neunten und zehnten MOSFET-Transistors M1, M2, M3, M9, M10 verbunden. Die Referenzspannung Vref wird an dem durch den vierten und fünften Widerstand R4, R5 gebildeten Spannungsteiler abgegriffen.Finally, in the left circuit part of the output buffer / driver 4 is realized, comprising a sixth bipolar PNP transistor T6, whose emitter via a series connection of a fourth and fifth resistor R4, R5 to the supply voltage Vdd and its collector via a fifth MOSFET transistor M5 Mass is connected. The emitter is also connected via a sixth MOSFET transistor M6 to ground whose gate is connected to the collector of the sixth transistor T6. The base of the fifth MOSFET transistor M5 is in turn connected to the interconnected gate terminals of the first, second, third, ninth and tenth MOSFET transistors M1, M2, M3, M9, M10. The reference voltage Vref is tapped at the voltage divider formed by the fourth and fifth resistors R4, R5.

Ein wesentlicher Kern der Erfindung besteht in der Implementierung des Bandgap-Prinzips in der Bandgap-Schaltung 1, die auch eigenständig, das heißt ohne die Schaltungsteile 2 bis 4 einsetzbar ist. Sie ist jedoch insbesondere für den Einsatz in Kombination mit dem Komparator 2 geeignet, durch den sich die Unempfindlichkeit der Gesamtschaltung gegenüber den eingangs genannten Reversströmen ergibt. Ferner wird mit dem strombestimmenden ersten Widerstand R1 der Temperaturgang der Differenz der beiden Basis-Emitterspannungen von T1 und T2 dUBE kompensiert, so dass der Referenzstrom Iref temperaturunabhängig ist.An essential core of the invention is the implementation of the bandgap principle in the bandgap circuit 1, which is also independent, that is, without the circuit parts 2 to 4 can be used. However, it is particularly suitable for use in combination with the comparator 2, through which the insensitivity of the overall circuit compared to the aforementioned reverse currents results. Furthermore, the temperature response of the difference between the two base-emitter voltages of T1 and T2 dU BE is compensated with the current-determining first resistor R1, so that the reference current Iref is temperature-independent.

Darüber hinaus ist die Schaltung selbstversorgend, so dass sich zwei mögliche Arbeitspunkte ergeben, und zwar einerseits ein gewünschter und andererseits ein solcher Arbeitspunkt, bei dem der Referenzstrom Iref gleich Null und die Referenzspannung Vref gleich der positiven Versorgungsspannung Vdd ist. Die bei bekannten Schaltungen mit dieser Eigenschaft häufig nur schwer zu realisierende Startschaltung ist erfindungsgemäss in das Stellglied 3 integriert, ohne einen wesentlichen zusätzlichen Aufwand zu erfordern.In addition, the circuit is self-sufficient, resulting in two possible operating points, on the one hand a desired and on the other hand such an operating point, in which the reference current Iref is equal to zero and the reference voltage Vref is equal to the positive supply voltage Vdd. The starting circuit, which is often difficult to implement in known circuits having this property, is integrated according to the invention into the actuator 3, without requiring a substantial additional outlay.

Die beiden Transistoren T1, T2 der Bandgap-Schaltung 1 weisen unterschiedliche Emitterflächen auf. Wenn das Potential an den Klemmen A, B, das heißt an den Emitteranschlüssen des ersten und zweiten Transistors T1, T2 identisch ist und auch die Ströme I1, I2 gleich sind, so liegt an den Basisanschlüssen die Differenz der beiden Basis-Emitter-Spannungen dUBE von T1 und T2 an. Dadurch ergibt sich für diesen Gleichgewichtszustand ein Referenzstrom durch den ersten Widerstand R1 von Iref = dUBE / R1, der auch über den zweiten Widerstand R2 fließt.The two transistors T1, T2 of the bandgap circuit 1 have different emitter areas. If the potential at the terminals A, B, that is to say at the emitter terminals of the first and second transistors T1, T2, is identical and the currents I1, I2 are equal, the difference between the two base-emitter voltages dU is present at the base terminals BE from T1 and T2. This results for this equilibrium state, a reference current through the first resistor R1 of Iref = dU BE / R1, which also flows through the second resistor R2.

Die Referenzspannung ergibt sich als Summe des durch den Referenzstrom Iref erzeugten Spannungsabfalls an dem zweiten Widerstand R2 und der Spannung UBE an der Basis-Emitter-Diode des ersten Transistors T1. Die Referenzspannung Vref ist an der ersten Klemme A abgreifbar und auf die positive Versorgungsspannung Vdd bezogen.The reference voltage results as the sum of the voltage drop across the second resistor R2 generated by the reference current Iref and the voltage U BE at the base-emitter diode of the first transistor T1. The reference voltage Vref can be tapped off at the first terminal A and related to the positive supply voltage Vdd.

Der Komparator 2 regelt im Zusammenspiel mit dem Stellglied 3 die Bandgap-Schaltung 1 stets auf diesen Gleichgewichtszustand aus, bei dem der Referenzstrom Iref gleich dem ersten und dem zweiten Strom I1, I2 (Emitterstrom des ersten bzw. zweiten Transistors T1, T2) durch die erste bzw. zweite Klemme A, B ist. Diese Strombedingung wird durch die durch den ersten bis dritten MOSFET-Transistor M1, M2, M3 gebildete Stromspiegelschaltung realisiert. Durch die dem Stromspiegel vorgeschalteten pnp-Transistoren T4, T5 hat ein Potentialunterschied an den Klemmen A, B unmittelbar einen Stromunterschied zur Folge und wird daher ebenso ausgeregelt. Dieser Regelvorgang läuft im Detail wie folgt ab:The comparator 2 controls in conjunction with the actuator 3, the bandgap circuit 1 always to this equilibrium state, in which the reference current Iref equal to the first and the second current I1, I2 (emitter current of the first and second transistor T1, T2) through the first and second terminal A, B is. This current condition is realized by the current mirror circuit formed by the first to third MOSFET transistors M1, M2, M3. By the upstream of the current mirror pnp transistors T4, T5, a potential difference at the terminals A, B directly results in a current difference and is therefore also regulated. This control process takes place in detail as follows:

Wenn die Spannung an der ersten Klemme A oder der erste Strom I1 durch diese Klemme A ansteigen, so wird der Gateanschluss des vierten MOS-Transistors M4 des Stellgliedes 3 nach Masse gezogen und dadurch der dritte Transistor T3 aufgesteuert. Dadurch steigt das Potential an den Basisanschlüssen des vierten, fünften und sechsten Transistors T4, T5, T6 an, bis der Gleichgewichtszustand wieder hergestellt ist.When the voltage at the first terminal A or the first current I1 rises through this terminal A, the gate terminal of the fourth MOS transistor M4 of the actuator 3 is pulled to ground, thereby turning on the third transistor T3. As a result, the potential at the base terminals of the fourth, fifth and sixth transistors T4, T5, T6 increases until the equilibrium state is restored.

Der dritte Widerstand R3 bildet dabei eine Stromsenke für den dritten Transistor T3 und wirkt gleichzeitig als Startwiderstand, indem er im stromlosen Zustand die Basisanschlüsse des vierten bis sechsten Transistors T4, T5, T6 nach Masse zieht und so den unerwünschten Arbeitspunkt ausschließt.The third resistor R3 forms a current sink for the third transistor T3 and simultaneously acts as a starting resistor by pulling in the de-energized state, the base terminals of the fourth to sixth transistor T4, T5, T6 to ground and thus excludes the undesirable operating point.

Der optionale Ausgangspuffer / Treiber 4 treibt den sechsten Transistor T6 mit einem Basispotential und einem Emitterstrom, das / der identisch ist mit denjenigen an dem vierten und fünften Transistor T4, T5. Das Emitterpotential entspricht dem Potential an der ersten und zweiten Klemme A, B und somit der Referenzspannung Vref. Die Forderung des identischen Emitterstroms wird durch den fünften und sechsten MOSFET-Transistor M5, M6 erfüllt. Wenn der Emitter- und somit der Kollektorstrom durch den sechsten Transistors T6 steigt, so steigt auch das Potential an dem fünften MOSFET-Transistor M5, so dass der vierte MOSFET-Transistor M4 aufgesteuert wird und den überschüssigen Strom übernimmt.The optional output buffer / driver 4 drives the sixth transistor T6 with a base potential and an emitter current which is identical to those at the fourth and fifth transistor T4, T5. The emitter potential corresponds to the potential at the first and second terminals A, B and thus the reference voltage Vref. The requirement of the identical emitter current is met by the fifth and sixth MOSFET transistor M5, M6. When the emitter and thus the collector current through the sixth transistor T6 increases, so does the potential at the fifth MOSFET transistor M5, so that the fourth MOSFET transistor M4 is turned on and takes over the excess current.

Claims (6)

  1. Circuit arrangement for producing constant voltages in accordance with the bandgap principle,
    characterized by
    - a first and a second transistor (T1, T2) whose base terminals are connected to one another via a first resistor (R1) and whose collector terminals are connected to a supply voltage (Vdd),
    - a second resistor (R2) which is connected between the base terminal of the first transistor (T1) and the supply voltage (Vdd),
    a comparator (2) which is connected to the emitter terminals of the first and second transistors (T1, T2), to the first resistor (R1) and to ground and which, on account of the difference between the base-emitter voltages across the transistors (T1, T2), produces a reference current (Iref) which flows through the first and second resistors (R1, R2) to earth,
    - a reference voltage which is based on the supply voltage (Vdd) being able to be tapped off at the emitter of the first transistor (T1).
  2. Circuit arrangement according to Claim 1,
    characterized by
    an output buffer/driver (4) having a low-resistance output at which a divided reference voltage (Vref) which is dependent on the reference voltage across the emitter of the first transistor (T1) is available.
  3. Circuit arrangement according to Claim 1 or 2,
    characterized in that the comparator (2) has a current mirror circuit (M1, M2, M3) which is supplied with the emitter currents (I1, I2) of the first and second transistors (T1, T2) and the reference current and is designed in such a manner that the emitter currents (I1, I2) are regulated in such a manner that these currents are essentially the same.
  4. Circuit arrangement according to Claim 3,
    characterized in that
    the comparator (2) has a fourth and a fifth transistor (T4, T5) whose gate terminals are connected to one another and whose emitter terminals are connected to the emitter terminals of the first and second transistors (T1, T2), so that a voltage difference across these terminals results in a current difference which is corrected using the current mirror circuit (M1, M2, M3).
  5. Circuit arrangement according to Claim 3 or 4,
    characterized by
    a tenth transistor (M10) which is driven by the current mirror circuit and provides a temperature-independent bias current (IBIAS).
  6. Circuit arrangement according to one of Claims 3 to 5,
    characterized by
    an actuator (3) having a start circuit for acting on the comparator (2), said actuator having a third transistor (T3) which is used to correct a voltage or current difference across the emitter terminals of the first and second transistors (T1, T2) by driving the fourth and fifth transistors (T4, T5).
EP20010101805 2000-02-16 2001-01-26 Circuit for producing a constant voltage Expired - Lifetime EP1126351B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2000106950 DE10006950C1 (en) 2000-02-16 2000-02-16 Circuit arrangement for constant voltage and / or constant current generation
DE10006950 2000-02-16

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EP1126351A1 EP1126351A1 (en) 2001-08-22
EP1126351B1 true EP1126351B1 (en) 2007-03-28

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CN103699171B (en) * 2012-09-27 2015-10-28 无锡华润矽科微电子有限公司 There is the bandgap current circuit structure of high stability

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Publication number Priority date Publication date Assignee Title
US4348633A (en) * 1981-06-22 1982-09-07 Motorola, Inc. Bandgap voltage regulator having low output impedance and wide bandwidth
DE68911708T2 (en) * 1988-02-19 1994-06-30 Philips Nv Bandgap reference voltage circuit.
DE69423742T2 (en) * 1994-04-29 2000-08-31 Sgs-Thomson Microelectronics, Inc. Bandgap reference circuit

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