EP1125007A1 - Submicron metallization using electrochemical deposition - Google Patents
Submicron metallization using electrochemical depositionInfo
- Publication number
- EP1125007A1 EP1125007A1 EP99954748A EP99954748A EP1125007A1 EP 1125007 A1 EP1125007 A1 EP 1125007A1 EP 99954748 A EP99954748 A EP 99954748A EP 99954748 A EP99954748 A EP 99954748A EP 1125007 A1 EP1125007 A1 EP 1125007A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- current density
- electroplating
- metal
- waveform
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/10—Electroplating with more than one layer of the same or of different metals
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/18—Electroplating using modulated, pulsed or reversing current
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
- C25D5/611—Smooth layers
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/615—Microstructure of the layers, e.g. mixed structure
- C25D5/617—Crystalline layers
Definitions
- An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor material.
- Devices which may be formed within the semiconductor material include MOS transistors, bipolar transistors, diodes and diffused resistors.
- Devices which may be formed within the dielectric include thin- film resistors and capacitors.
- more than 100 integrated circuit die (IC chips) are constructed on a single 8 inch diameter silicon wafer.
- the devices utilized in each dice are interconnected by conductor paths formed within the dielectric.
- two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections.
- an aluminum alloy and silicon oxide are typically used for, respectively, the conductor and dielectric.
- signal propagation delay may be characterized by a time delay ⁇ . See E.H. Stevens, Interconnect Technology, QMC, Inc., July 1993. An approximate expression for the time delay, ⁇ , as it relates to the transmission of
- R and C are, respectively, an equivalent resistance and capacitance for the interconnect path
- ISAT and VSAT are, respectively, the saturation (maximum) current and the drain-to-source potential at the onset of current saturation for the transistor that applies a signal to the interconnect path.
- the path resistance is proportional to the resistivity, p, of the conductor material.
- the path capacitance is proportional to the relative dielectric permittivity, Ke, of the dielectric material.
- Ke relative dielectric permittivity
- Ke dielectric should be utilized in the manufacture of high-performance integrated circuits.
- copper interconnect lines within a low-Ke dielectric will likely replace aluminum-alloy lines within a silicon oxide dielectric as the most preferred interconnect structure. See “Copper Goes Mainstream: Low-k to follow", Semiconductor International, November 1997, pp. 67-70. Resistivities of copper films are in the range of 1.7 to 2.0 ⁇ cm. while resistivities of aluminum- alloy films are higher in the range of 3.0 to 3.5 ⁇ cm.
- Another problem is the propensity of copper to oxidize rapidly when immersed in aqueous solutions or when exposed to an oxygen-containing atmosphere. Oxidized surfaces of the copper are rendered non-conductive and thereby limit the current carrying capability of a given conductor path when compared to a similarly dimensioned non-oxidized copper path.
- a still further problem with using copper in integrated circuits is that it is difficult to use copper in a multi-layer, integrated circuit structure with dielectric materials. Using traditional methods of copper deposition, copper adheres only weakly to dielectric materials.
- Fig. 1 illustrates the process steps generally required for implementing the dual damascene architecture.
- Electrodeposition of the copper metallization has been found to be the most efficient way to deposit copper into the trenches and vias. This method has been found to impart the best electromigration resistance performance to the resulting interconnect.
- this method of depositing the copper is not without problems of its own.
- acid copper plating solutions for copper interconnect often contain organic additives to provide improved throwing power, enhanced leveling effect, and proper deposit characteristics. Since these additives play a significant role in copper plating, the concentrations of these additives in the plating bath need to be tightly controlled to ensure consistent trench fill and film properties.
- the present inventors have recognized that it would be desirable to use an additive-free plating solution to improve bath control, thereby eliminate the need to monitor the concentrations of the additives. Further, they have recognized that, even in the presence of such additives, certain plating parameters must be optimized.
- the present inventors have found that application of metallization, particularly copper metallization, using low current density plating waveforms provides better trench and via filling results when compared to high current density plating waveforms. This is particularly true when additive-free plating solutions are used.
- low current density plating waveforms are often quite slow in producing metal films of the requisite thickness. Accordingly, a low current density plating waveform is used during initial plating operations while a high current density plating waveform is used to decrease the fill time and, if desired, provide a different film morphology, some time after the initial plating operations are complete.
- the waveshape and its frequency are used to influence the surface morphology of the copper metallization deposit. Further, high metal concentrations in the additive-free plating solutions are used to provide more effective filling of the trench and via structures.
- plating solutions that include additives
- the present inventors have found that the plating process may be optimized by employing low metal concentration plating solutions. Such solutions produce higher quality filling of the trenches and vias when compared with copper metallization deposited using solutions having high metal concentrations.
- Methods for depositing a metal into a micro-recessed structure in the surface of a microelectronic workpiece are disclosed.
- the methods are suitable for use in connection with additive free as well as additive containing electroplating solutions.
- the method includes making contact between the surface of the microelectronic workpiece and an electroplating solution in an electroplating cell that includes a cathode formed by the surface of the microelectronic workpiece and an anode disposed in electrical contact with the electroplating solution.
- an initial film of the metal is deposited into the micro- recessed structure using at least a first electroplating waveform having a first current density.
- the first current density of the first electroplating waveform is provide to enhance the deposition of the metal at a bottom of the micro-recessed structure. After the this initial plating, deposition of the metal is continued using at least a second electroplating waveform having a second current density.
- the second current density of the second electroplating waveform is provided to assist in reducing the time required to substantially complete filling of the micro-recessed structure.
- Figure 1 is a scanning electron microscope (“SEM") photograph showing a cross-section of a metallization layer plated exterior to a semiconductor substrate wherein the metallization layer was deposited using a plating bath without organic additives and using a low-current plating waveform.
- SEM scanning electron microscope
- Figure 2 is a SEM photograph showing a cross-section of a metallization layer plated exterior to a semiconductor substrate wherein the metallization layer was deposited using a plating bath without organic additives and using a high current density plating waveform.
- Figures 3(a) - (d) are SEM photographs showing cross-sections of metallization layers plated exterior to respective semiconductor substrates wherein the metallization layers were deposited using incremental depositions at different current densities and thicknesses.
- Figure 4 is a SEM photograph showing a cross-section of a metallization layer plated exterior to a semiconductor substrate wherein the metallization layer was deposited using a pulse reverse waveform.
- Figure 5 is a SEM photograph showing a cross-section of a metallization layer plated exterior to a semiconductor substrate wherein the metallization layer was deposited using a two-step waveform comprised of an initial waveform having a low- current density followed by a further waveform having high-current density.
- Figure 6 is a SEM photograph showing a cross-section of a metallization layer plated exterior to a semiconductor substrate wherein the metallization layer was plated using the two-step waveform used to plate the metallization layer of Figure 5, but wherein plating solution had a high copper concentration.
- Figures 7 and 8 are SEM photographs showing cross-sections of metallization layers plated exterior to respective semiconductor substrates wherein the layers were deposited using a one-step waveform in a plating bath having organic additives.
- Figure 9 is a SEM photograph showing a cross-section of a metallization layer plated exterior to a semiconductor substrate wherein the metallization layer was plated using the one-step waveform used in the metallization process of Figures 7 and 8, but wherein the copper concentration of the plating solution has been reduced.
- Figures 10(a) - 10(c) are FIB photographs showing cross-sections of metallization layers plated exterior to respective semiconductor substrates wherein the metallization layers were plated using a plating bath having organic additives, and wherein the photographs illustrate the effect of seed layer quality on the plating process.
- the present invention can be understood with reference to the experiments disclosed herein. Although the experiments were performed in connection with the plating of a metal comprising copper, it will be recognized that the teachings disclosed herein are so applicable to the electroplating of other metals. All the experiments were performed on 200mm wafers using a plating tool, such as a plating tool available from Semitool, Inc., of Kalispell, Montana. Three plating baths were examined. The first one, bath 1 (either 24g/L or 36g/L copper) had no organic additives. The bath 2 (Additive A) and the bath 2 (Additive B) contain organic additives from different vendors.
- FIG. 1 presents a scanning electron microscope ("SEM") cross-section obtained from bath 1 with 24g/L copper. Void- free fill was obtained for 0.5 ⁇ wide, 2:1 aspect ratio trench. The waveshape used was a forward pulse with 1 ms on and 1 ms off (WF1). It was found that the waveshape was not significant for fill as long as the current density was low.
- an electroplating waveform having low current density is used during the initial phases of the trench and/or via filling stage of the process. At some time subsequent to such initial filling, the electroplating waveform transitions to a higher current density waveform to complete the electroplating process and reduce the total time required for the process.
- an initial low current density approach is necessary for gap fill if no-additive bath is used.
- initial low current is helpful to improve the contact to the seed layer, particularly when the seed layer is very thin.
- the drawback of low current is its long processing time.
- a plating recipe with multiple steps is preferred in which a low current plating waveform is used to fill the small feature and, possibly, to enhance the seed layer, and then a high current plating waveform is used to finish the process and to provide smooth surface for one or more subsequent CMP processes.
- Figure 5 shows a cross-section obtained with a two-step waveform of 4mA/cm 2 followed by 32mA/cm 2 . An improvement in gap fill was observed. Using the same two-step waveform, an increase in the copper concentration (36g/L) provided significant improvement of the fill process as illustrated in Figure 6.
- FIG. 7 illustrates a metallization way are plated from such a bath using a 1-step waveform at 20 mA/cm 2 .
- Figure 8 is a cross-section obtained at 20mA/cm 2 with 20g/L copper in the solution. Although the surface of the deposit was smooth, similar to bath 3, voids were observed in the trench at this copper concentration. As the copper concentration decreased from 20 to lOg/L, void-free fill was obtained as in Figure 9. The better gap fill at lower copper concentration in the presence of organic additives is different from that obtained for additive-free bath in which high copper provided better gap fill. This implies a different controlling mechanism for copper growth in the presence of additives. Similar to those obtained from additive-free bath, pulse reverse was found to produce voids and rough surface in this bath with additives.
- Figures 10(a) - (c) illustrates the effect of seed layer on the gap fill.
- the center voids ( Figure 10a) are formed when the top of the feature is pinched off before the filling is completed.
- the overhanging of the seed layer at the top of the feature due to the line-of-sight deposition inherent in the PVD process, is often the main reason for the center voids and the insufficient suppressor of copper growth at the top of the trench during the plating is the other one.
- the former needs the optimization of the PVD process to deposit a conformal layer and may possibly require a combination of PVD process and other techniques such as CVD or electrochemical deposition for small features.
- the latter calls for the optimization of the plating process by changing the bath composition and plating waveform.
- the bottom and sidewall voids are mainly attributed to the insufficient coverage of the seed layer. Copper oxide is always formed on the seed layer prior to the plating when the wafer is exposed to air. This oxide is readily removed, and the underlying copper can be chemically etched when the wafer is in contact with the acidic plating solution. This may lead to the exposure of the barrier layer to the solution and result in the formation of bottom or sidewall voids. There are ways to eliminate these voids either by having a thick layer in the feature or using less aggressive plating solutions for the copper plating. By optimizing the seed layer, void-free gap fill was achieved as in Fig. 10(c).
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Battery Electrode And Active Subsutance (AREA)
- Secondary Cells (AREA)
- Electroplating And Plating Baths Therefor (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10306198P | 1998-10-05 | 1998-10-05 | |
US103061P | 1998-10-05 | ||
PCT/US1999/023187 WO2000020662A1 (en) | 1998-10-05 | 1999-10-05 | Submicron metallization using electrochemical deposition |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1125007A1 true EP1125007A1 (en) | 2001-08-22 |
EP1125007A4 EP1125007A4 (en) | 2003-05-28 |
EP1125007B1 EP1125007B1 (en) | 2010-08-11 |
Family
ID=22293166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP99954748A Expired - Lifetime EP1125007B1 (en) | 1998-10-05 | 1999-10-05 | Submicron metallization using electrochemical deposition |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1125007B1 (en) |
JP (1) | JP2002526663A (en) |
AT (1) | ATE477353T1 (en) |
DE (1) | DE69942669D1 (en) |
WO (1) | WO2000020662A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3641372B2 (en) * | 1998-10-21 | 2005-04-20 | 株式会社荏原製作所 | Electrolytic plating method and electrolytic plating apparatus |
US6913680B1 (en) * | 2000-05-02 | 2005-07-05 | Applied Materials, Inc. | Method of application of electrical biasing to enhance metal deposition |
JP2002121699A (en) * | 2000-05-25 | 2002-04-26 | Nippon Techno Kk | Electroplating method using combination of vibrating flow and impulsive plating current of plating bath |
JP5000941B2 (en) * | 2006-07-27 | 2012-08-15 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP5767154B2 (en) * | 2012-04-13 | 2015-08-19 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP5749302B2 (en) * | 2013-08-20 | 2015-07-15 | 株式会社荏原製作所 | Plating method |
JP6450560B2 (en) * | 2014-10-24 | 2019-01-09 | 新日本無線株式会社 | Semiconductor device and manufacturing method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4514265A (en) * | 1984-07-05 | 1985-04-30 | Rca Corporation | Bonding pads for semiconductor devices |
US4869971A (en) * | 1986-05-22 | 1989-09-26 | Nee Chin Cheng | Multilayer pulsed-current electrodeposition process |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR960114A (en) * | 1942-05-04 | 1950-04-13 | ||
US3894918A (en) * | 1973-12-20 | 1975-07-15 | Western Electric Co | Methods of treating portions of articles |
US4250004A (en) * | 1980-02-25 | 1981-02-10 | Olin Corporation | Process for the preparation of low overvoltage electrodes |
JPH03104230A (en) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH03208347A (en) * | 1990-01-10 | 1991-09-11 | Mitsubishi Electric Corp | Formation of bump |
JPH07336017A (en) * | 1994-06-08 | 1995-12-22 | Hitachi Ltd | Manufacture of thin-film circuit by periodic reverse electrolyzing method and thin-film circuit board, thin-film multilayer circuit board and electronic circuit device using the same |
US5605615A (en) * | 1994-12-05 | 1997-02-25 | Motorola, Inc. | Method and apparatus for plating metals |
JP3561582B2 (en) * | 1996-09-18 | 2004-09-02 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
JPH1098268A (en) * | 1996-09-24 | 1998-04-14 | Oki Electric Ind Co Ltd | Method for plating columnar conductor and multi-layered printed wiring board obtained by it |
US5972192A (en) * | 1997-07-23 | 1999-10-26 | Advanced Micro Devices, Inc. | Pulse electroplating copper or copper alloys |
JP3694594B2 (en) * | 1998-09-03 | 2005-09-14 | 株式会社荏原製作所 | Method for hole-filling plating of substrate having fine holes and / or fine grooves |
-
1999
- 1999-10-05 DE DE69942669T patent/DE69942669D1/en not_active Expired - Lifetime
- 1999-10-05 AT AT99954748T patent/ATE477353T1/en not_active IP Right Cessation
- 1999-10-05 WO PCT/US1999/023187 patent/WO2000020662A1/en active Application Filing
- 1999-10-05 EP EP99954748A patent/EP1125007B1/en not_active Expired - Lifetime
- 1999-10-05 JP JP2000574753A patent/JP2002526663A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4514265A (en) * | 1984-07-05 | 1985-04-30 | Rca Corporation | Bonding pads for semiconductor devices |
US4869971A (en) * | 1986-05-22 | 1989-09-26 | Nee Chin Cheng | Multilayer pulsed-current electrodeposition process |
Non-Patent Citations (1)
Title |
---|
See also references of WO0020662A1 * |
Also Published As
Publication number | Publication date |
---|---|
EP1125007A4 (en) | 2003-05-28 |
JP2002526663A (en) | 2002-08-20 |
ATE477353T1 (en) | 2010-08-15 |
WO2000020662A9 (en) | 2000-09-14 |
EP1125007B1 (en) | 2010-08-11 |
WO2000020662A1 (en) | 2000-04-13 |
DE69942669D1 (en) | 2010-09-23 |
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