EP1118922A1 - Electrical circuit to control a load with two transistors - Google Patents
Electrical circuit to control a load with two transistors Download PDFInfo
- Publication number
- EP1118922A1 EP1118922A1 EP00127024A EP00127024A EP1118922A1 EP 1118922 A1 EP1118922 A1 EP 1118922A1 EP 00127024 A EP00127024 A EP 00127024A EP 00127024 A EP00127024 A EP 00127024A EP 1118922 A1 EP1118922 A1 EP 1118922A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- transistor
- transistors
- voltage
- current
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/573—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
Definitions
- the invention relates to a circuit arrangement with two transistors, which in Interconnect series with a load to be operated.
- a typical example of one about one Output driven load is the electrical ignition element of the Gas generator of an automotive airbag. In this application example is about a short time a defined minimum power to ignite the electrical Ignition element implemented in this.
- the energy supply exists here essentially from an energy storage device, for example a capacitor having. To protect the driver transistors, but also to protect them before an excessive current flows through the load becomes an output stage current-limited, which is due to the use of transistors is realized with current limitation.
- FIG. 1 A known circuit arrangement with current limitation is shown in FIG. 1.
- Such a current-limited output stage generally exists the problem in that the electrical power dissipation on the two Transistors M1 and M2 is uneven and therefore poorly distributed.
- a load R the can be resistive, capacitive or inductive through the two transistors M1 and M2, which are bipolar or field effect transistors can, energized. Since the load R is far from the two transistors M1 and M2 can be located away to avoid damage in operation and a short-circuit protection or current limitation for the two transistors M1 and M2 required. Otherwise they would have short circuits the supply lines with the potentials U1 and U2 against a positive or negative supply damage to transistors M1 or M2 resulted.
- Limiting the current may also be necessary for the load R. For example, to avoid that at the beginning or at the end overcurrents flow in a switched-on state. It can also appear be to prevent such overcurrents because otherwise the Circuit arrangement feeding energy storage discharges itself too quickly. This should, for example, in a motor vehicle application of the circuit arrangement according to the invention for igniting the ignition elements of the gas generators multiple airbags can be prevented. That is after the collapse of the electrical system can still trigger all airbags no greater current than the ignition current is supplied to each ignition element, otherwise the energy in the energy storage will not ignite them all required airbag would be sufficient.
- the current limitation in the transistors M1 and M2 takes place in the manner known per se by means of shunt resistors or by measuring the voltage drop across the transistors or a part of these transistors. It is not physically possible for the same voltage drop and thus the same power to be set across both transistors. The reason for this can be seen in the fact that the transistors have limit currents of different magnitudes due to specimen scatter. As a result, the limitation on one of the two transistors M1, M2 will always have a stronger effect than on the other. A very large voltage drop will thus occur via one of the two transistors M1, M2, with which the far greater part of the power must be absorbed by this transistor. In the circuit arrangement according to FIG. 1 it is assumed that the current limitation over the transistor M2 is slightly smaller than over the transistor M1; in other words, I lim (M1) is greater than I lim (M2) .
- From DE-A-15 13 168 is an output stage for operating a load known, in which two transistors connected in series with one to operating load are switched. One of the two transistors is like this controlled that the current flowing over its conduction path to one Maximum value is limited.
- the invention has for its object a circuit arrangement for Operating a load via two transistors to be connected in series with the load with which it is easily possible to create the power loss distribute evenly across both transistors.
- the two transistors connected to current control circuits at their control inputs, which ensure that the conduction paths of the transistors flowing currents are limited to first or second maximum values.
- the Current limiting value of the first transistor is greater than the current limiting value of the second transistor.
- control signal at the control input of the first transistor if a current flows with the size of the second maximum value, such adjustable that a voltage across the line path of the first transistor drops that is greater than the voltage that would drop if over the conduction path of the first transistor has a current the size of the second Maximum value flows.
- Influencing the control signal at the control input of the first transistor can be done by simply returning the voltage drop across the first Transistor can be realized.
- a coupling or additional interconnection the current limiting circuits of both transistors is in the invention Circuitry not required, so that by conceivable little effort a more even distribution of the two transistors power loss to be implemented is achieved or prevented, that one of the two transistors absorb significantly more power loss has than the other.
- An advantageous further development is a comparator for comparing the voltage drop over the line path of the first transistor with a reference voltage intended. This comparator then gives when the voltage drop over the conduction path of the first transistor is larger than that Reference voltage, an output signal for influencing the first control signal for the control input of the first transistor.
- An even easier one Feedback of the voltage drop across the first transistor to its Control input is realized in that the current limiting circuit of the first transistor as a function of a reference voltage supplying first voltage source is controlled and that the first transistor is connected as a voltage follower. So that the voltage drop over the first transistor at least for a defined time or a defined Operating state does not become greater than the reference voltage, it applies So that the voltage drop across the transistor is essentially the same the reference voltage.
- the circuit arrangement according to FIG. 2 shows a first possibility according to the invention of an improved power distribution to the two transistors M1 and M 2 when current flows through the load R.
- the transistors or actuators are deliberately impressed with different current limits.
- the supply voltage SUG2 of the current limiting circuit CL2 for the transistor M2 is used to generate the control voltage UG2 for the transistor M2.
- This voltage is regulated in the current limiting circuit CL2 for the transistor M2 in such a way that a maximum current I lim (M2) is set via the transistor M2.
- I lim (M2) is set via the transistor M2.
- I lim (M2) is set via the transistor M2.
- I lim (M2) is greater than the current limitation for transistor M2. So the following applies: I lim (M1) is greater than I lim (M2) .
- the reference voltage UREF is freely selectable and so is the power distribution freely selectable on the two transistors M1 and M2.
- the reference voltage UREF can be made using a voltage divider from the supply voltage US generated or applied with a fixed voltage, so that when this voltage at U1 is exceeded, the voltage drop and so the power consumption is minimized or only then fully effective becomes. Combinations of fixed and proportional voltage components to UREF or a change over time is possible.
- FIG. 3 Another embodiment of the circuit arrangement according to the invention shows Fig. 3. This circuit arrangement is compared to the circuit arrangement 2 simplified to the extent that the return of the Voltage at U1 is dispensed with and that for controlling the current limiting circuit CL1 required for the transistor M1 control voltage RSUG1 2 directly from the reference voltage UREF is produced. This is achieved by switching transistor M1 as a voltage follower is. Also in the example according to FIG. 3, at least one applies Time or a defined operating state that the voltage at U1 is substantially equal to the reference voltage UREF.
- a wide range can be achieved with the circuit arrangement according to the invention of power distributions over location, working conditions (voltage) and time adjust without there being a coupling of the current limiting circuits of the two transistors M1 and M2 is required. That means the transistors M1 and M2 can be arranged locally far apart. The transistors M1 and M2 can thus be loaded in a simple manner be optimized.
- Figs. 2 and 3 circuit arrangements shown can be also add to a (full) bridge circuit.
- Fig. 4 shows such a full bridge circuit for the circuit variant according to FIG. 2. Depending on the direction of the current through the load R either flows through the pair of transistors M1, M4 or M2, M3.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Amplifiers (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
Description
Die Erfindung betrifft eine Schaltungsanordnung mit zwei Transistoren, die in Reihe mit einer zu betreibenden Last zu verschalten sind.The invention relates to a circuit arrangement with two transistors, which in Interconnect series with a load to be operated.
Es gibt zahlreiche technische Anwendungen für Schaltungsanordnungen, mit denen über zwei Treibertransistoren eine mit diesen in Reihe geschaltete Last angesteuert wird. Ein typisches Beispiel für eine über eine derartige Ausgangsstufe angesteuerte Last ist das elektrische Anzündelement des Gasgenerators eines Kfz-Airbag. Bei diesem Anwendungsbeispiel wird über eine kurze Zeit eine definierte Mindestleistung zum Zünden des elektrischen Anzündelements in diesem umgesetzt. Die Energieversorgung besteht hierbei im wesentlichen aus einem Energiespeicher, der beispielsweise einen Kondensator aufweist. Zum Schutz der Treibertransistoren, aber auch zum Schutz davor, dass durch die Last ein zu großer Strom fließt, wird eine Ausgangsstufe strombegrenzt ausgelegt, was durch die Verwendung von Transistoren mit Strombegrenzung realisiert wird.There are numerous technical applications for circuit arrangements with a load connected in series with these via two driver transistors is controlled. A typical example of one about one Output driven load is the electrical ignition element of the Gas generator of an automotive airbag. In this application example is about a short time a defined minimum power to ignite the electrical Ignition element implemented in this. The energy supply exists here essentially from an energy storage device, for example a capacitor having. To protect the driver transistors, but also to protect them before an excessive current flows through the load becomes an output stage current-limited, which is due to the use of transistors is realized with current limitation.
Eine bekannte Schaltungsanordnung mit Strombegrenzung ist in Fig. 1 dargestellt. Bei einer solchen strombegrenzten Ausgangsstufe besteht im allgemeinen das Problem darin, dass die elektrische Verlustleistung auf die beiden Transistoren M1 und M2 ungleichmäßig und damit schlecht verteilt ist.A known circuit arrangement with current limitation is shown in FIG. 1. Such a current-limited output stage generally exists the problem in that the electrical power dissipation on the two Transistors M1 and M2 is uneven and therefore poorly distributed.
Bei der bekannten Schaltungsanordnung nach Fig. 1 wird eine Last R, die resistiv, kapazitiv oder induktiv sein kann, durch die beiden Transistoren M1 und M2, bei denen es sich um Bipolar- oder Feldeffekt-Transistoren handeln kann, bestromt. Da die Last R von den beiden Transistoren M1 und M2 weit entfernt angeordnet sein kann, ist zur Vermeidung von Schäden im Betrieb und bei der Montage eine Kurzschlusssicherung bzw. Strombegrenzung für die beiden Transistoren M1 und M2 erforderlich. Andernfalls hätten Kurzschlüsse der Zuführleitungen mit den Potentialen U1 und U2 gegen eine positive oder negative Versorgung eine Beschädigung der Transistoren M1 bzw. M2 zur Folge.In the known circuit arrangement according to FIG. 1, a load R, the can be resistive, capacitive or inductive through the two transistors M1 and M2, which are bipolar or field effect transistors can, energized. Since the load R is far from the two transistors M1 and M2 can be located away to avoid damage in operation and a short-circuit protection or current limitation for the two transistors M1 and M2 required. Otherwise they would have short circuits the supply lines with the potentials U1 and U2 against a positive or negative supply damage to transistors M1 or M2 resulted.
Eine Begrenzung des Stromes kann aber auch für die Last R erforderlich sein. So soll beispielsweise vermieden werden, dass zu Beginn oder zum Ende eines Einschaltzustandes Überströme fließen. Ferner kann es auch angezeigt sein, derartige Überströme deshalb zu unterbinden, weil andernfalls der die Schaltungsanordnung speisende Energiespeicher sich zu schnell entlädt. Dies sollte beispielsweise bei einer Kfz-Anwendung der erfindungsgemäßen Schaltungsanordnung zum Zünden der Anzündelemente der Gasgeneratoren mehrerer Airbag verhindert werden. Damit nämlich noch nach dem Zusammenbruch des Bordnetzes dennoch sämtliche Airbag auslösen können, darf jedem Anzündelement kein größerer Strom als der Zündstrom zugeführt werden, da andernfalls die Energie im Energiespeicher nicht zum Zünden sämtlicher erforderlicher Airbag ausreichend wäre.Limiting the current may also be necessary for the load R. For example, to avoid that at the beginning or at the end overcurrents flow in a switched-on state. It can also appear be to prevent such overcurrents because otherwise the Circuit arrangement feeding energy storage discharges itself too quickly. This should, for example, in a motor vehicle application of the circuit arrangement according to the invention for igniting the ignition elements of the gas generators multiple airbags can be prevented. That is after the collapse of the electrical system can still trigger all airbags no greater current than the ignition current is supplied to each ignition element, otherwise the energy in the energy storage will not ignite them all required airbag would be sufficient.
Die Strombegrenzung in den Transistoren M1 und M2 erfolgt, wie bereits oben kurz erwähnt, in der an sich bekannten Weise durch Shunt-Widerstände oder durch Messung des Spannungsabfalls über den Transistoren oder eines Teils dieser Transistoren. Dabei ist es physikalisch nicht möglich, dass sich über beide Transistoren derselbe Spannungsabfall und damit dieselbe Leistung einstellt. Der Grund hierfür ist darin zu sehen, dass die Transistoren aufgrund von Exemplarstreuungen unterschiedlich große Begrenzungsströme aufweisen. Dies hat zur Folge, dass die Begrenzung an einem der beiden Transistoren M1,M2 stets stärker wirken wird als an dem jeweils anderen. Über einen der beiden Transistoren M1,M2 wird sich also ein sehr großer Spannungsabfall einstellen, womit der weitaus größere Teil der Leistung von diesem Transistor aufgenommen werden muss. In der Schaltungsanordnung gemäß Fig. 1 wird angenommen, dass die Strombegrenzung über dem Transistor M2 geringfügig kleiner ist als über dem Transistor M1; mit anderen Worten gilt also, dass Ilim(M1) größer ist als Ilim(M2).As already briefly mentioned above, the current limitation in the transistors M1 and M2 takes place in the manner known per se by means of shunt resistors or by measuring the voltage drop across the transistors or a part of these transistors. It is not physically possible for the same voltage drop and thus the same power to be set across both transistors. The reason for this can be seen in the fact that the transistors have limit currents of different magnitudes due to specimen scatter. As a result, the limitation on one of the two transistors M1, M2 will always have a stronger effect than on the other. A very large voltage drop will thus occur via one of the two transistors M1, M2, with which the far greater part of the power must be absorbed by this transistor. In the circuit arrangement according to FIG. 1 it is assumed that the current limitation over the transistor M2 is slightly smaller than over the transistor M1; in other words, I lim (M1) is greater than I lim (M2) .
Geht man weiter davon aus, dass die Einschaltwiderstände der Transistoren M1 und M2 bei Vollansteuerung kleiner sind als der Widerstand der Last R und dass der sich aus der Reihenschaltung ergebende Strom größer als die Strombegrenzung an einem der beiden Transistoren M1,M2 ist, wird sich beim Betrieb ein sehr großer Spannungsabfall U2 über dem Transistor M2 und damit eine sehr große Leistungsaufnahme durch den Transistor M2 ergeben. Der Transistor M1 wird voll angesteuert bleiben und durch den geringen Spannungsabfall über diesem Transistor wird nur eine geringe Leistung aufgenommen. Der Rest der Leistung wird über die Last R aufgenommen. Die große Leistungsaufnahme im Transistor M2 kann zu einer sehr starken Erwärmung und schließlich Schädigung dieses Transistors führen. Im allgemeinen ist zumindest eine starke Überdimensionierung des Leistungsaufnahmevermögens des Transistors M2 erforderlich. Dies ist wiederum von Nachteil in Bezug auf den Flächenverbrauch des Transistors, wenn man sich vor Augen führt, dass die Schaltungsanordnung insgesamt als integrierte Schaltung vorliegt.Assuming further that the on-resistances of the transistors M1 and M2 with full control are smaller than the resistance of the load R and that the current resulting from the series connection is greater than that Current limitation on one of the two transistors M1, M2 will, when Operation a very large voltage drop U2 across transistor M2 and thus result in a very large power consumption by the transistor M2. The transistor M1 will remain fully activated and due to the low The voltage drop across this transistor consumes only a small amount of power. The rest of the power is absorbed by the load R. The Large power consumption in transistor M2 can lead to very strong heating and eventually cause damage to this transistor. In general is at least a large oversize of the power consumption of transistor M2 required. This is again a disadvantage in Regarding the area consumption of the transistor when you look at it leads that the circuit arrangement is present overall as an integrated circuit.
Eine Möglichkeit, eine Ungleichverteilung der Verlustleistungen in den Transistoren M1 und M2 zu verhindern bzw. einer derartigen Ungleichverteilung entgegenzuwirken, besteht darin, die beiden Transistoren M1 und M2 miteinander zu verkoppeln, so dass man durch Erkennung der Strombegrenzung am Transistor M2 schaltungstechnisch auf den Transistor M1 einwirken kann, indem man beispielsweise dessen Strombegrenzung kurzzeitig heruntersetzt. Damit würden dann die beiden Transistoren M1 und M2 wechselweise in die Strombegrenzung laufen, was zu nicht gewollten Stromschwingungserscheinungen führt. Außerdem ist es in einer Vielzahl von Anwendungsfällen unerwünscht und teilweise aufgrund großer Entfernungen kaum möglich, die Transistoren M1 und M2 zusätzlich zu verkoppeln, um die Strombegrenzung des einen Transistors in Abhängigkeit von dem Ansprechen der Strombegrenzung des anderen Transistors zu regeln. One way an uneven distribution of the power dissipation in the transistors To prevent M1 and M2 or such an unequal distribution to counteract, is to connect the two transistors M1 and M2 together to couple so that one by recognizing the current limit in terms of circuitry, can act on transistor M1 at transistor M2, for example by briefly reducing its current limit. So that the two transistors M1 and M2 would alternately in the Current limitation run, which leads to unwanted current vibration phenomena leads. It is also undesirable in a variety of applications and partly due to long distances hardly possible, the transistors M1 and M2 additionally couple to limit the current of the a transistor depending on the response of the current limit to regulate the other transistor.
Aus DE-A-15 13 168 ist eine Ausgangsstufe zum Betreiben einer Last bekannt, bei der zwei in Serie geschaltete Transistoren in Reihe mit einer zu betreibenden Last geschaltet sind. Einer der beiden Transistoren ist derart gesteuert, dass der über seinen Leitungspfad fließende Strom auf einen Maximalwert begrenzt ist.From DE-A-15 13 168 is an output stage for operating a load known, in which two transistors connected in series with one to operating load are switched. One of the two transistors is like this controlled that the current flowing over its conduction path to one Maximum value is limited.
Der Erfindung liegt die Aufgabe zugrunde, eine Schaltungsanordnung zum Betreiben einer Last über zwei in Reihe mit der Last zu schaltende Transistoren zu schaffen, mit der es auf einfache Weise möglich ist, die Verlustleistung gleichmäßig auf beide Transistoren zu verteilen.The invention has for its object a circuit arrangement for Operating a load via two transistors to be connected in series with the load with which it is easily possible to create the power loss distribute evenly across both transistors.
Zur Lösung dieser Aufgabe wird mit der Erfindung eine Schaltungsanordnung vorgeschlagen, die versehen ist mit
- einem ersten Transistor, der einen mit einem ersten Steuersignal beaufschlagbaren Steuereingang und einem in Abhängigkeit von dem ersten Steuersignal steuerbaren Leitungspfad aufweist, wobei der über den Leitungspfad fließende Strom auf einen ersten Maximalwert begrenzt ist.
- einem zweiten Transistor, der einen mit einem zweiten Steuersignal beaufschlagbaren Steuereingang und einem in Abhängigkeit von dem zweiten Steuersignal steuerbaren Leitungspfad aufweist, wobei der über den Leitungspfad fließende Strom auf einen zweiten Maximalwert begrenzt ist,
- wobei
- der erste Maximalwert größer ist als der zweite Maximalwert,
- die Last in Reihe mit den Leitungspfaden des ersten und des zweiten Transistors verschaltbar ist und
- bei von einem Strom mit der Größe des zweiten Maximalwerts durchflossener Last das erste Steuersignal an dem Steuereingang des ersten Transistors derart einstellbar ist, dass über den Leitungspfad des ersten Transistors eine Spannung fällt, die größer ist als diejenige Spannung, die abfällt, wenn über dem Leitungspfad des ersten Transistors ein Strom mit der Größe des zweiten Maximalwerts fließt.
- a first transistor which has a control input to which a first control signal can be applied and a line path which can be controlled as a function of the first control signal, the current flowing via the line path being limited to a first maximum value.
- a second transistor which has a control input to which a second control signal can be applied and a line path which can be controlled as a function of the second control signal, the current flowing via the line path being limited to a second maximum value,
- in which
- the first maximum value is greater than the second maximum value,
- the load can be connected in series with the line paths of the first and the second transistor and
- with a current through which the size of the second maximum value flows, the first control signal can be set at the control input of the first transistor in such a way that a voltage drops across the line path of the first transistor that is greater than the voltage that drops when over the line path a current of the size of the second maximum value flows of the first transistor.
Bei der erfindungsgemäßen Schaltungsanordnung sind die beiden Transistoren an ihren Steuereingängen jeweils mit Strombegrenzungsschaltungen verbunden, die dafür sorgen ,dass die über die Leitungspfade der Transistoren fließenden Ströme auf erste bzw. zweite Maximalwerte begrenzt sind. Der Strombegrenzungswert des ersten Transistors ist dabei größer als der Strombegrenzungswert des zweiten Transistors. Dies ist, wie bereits oben im Zusammenhang mit der Beschreibung der im Stand der Technik bekannten Schaltungsanordnung erwähnt, aufgrund vom Exemplarstreuungen der Transistoren an sich der Normalfall. Dieser Normalfall wird erfindungsgemäß bewusst ausgenutzt, indem nämlich der Spannungsabfall über dem ersten Transistor bei in der Strombegrenzung befindlichem zweiten Transistor erhöht wird, um somit einen Teil der andernfalls vom zweiten Transistor aufgenommenen Leistung auf den ersten Transistor zu übertragen. Denn erfindungsgemäß ist das Steuersignal an dem Steuereingang des ersten Transistor dann, wenn ein Strom mit der Größe des zweiten Maximalwerts fließt, derart einstellbar, dass über den Leitungspfad des ersten Transistors eine Spannung abfällt, die größer ist als diejenige Spannung, die abfallen würde, wenn über dem Leitungspfad des ersten Transistors ein Strom mit der Größe des zweiten Maximalwerts fließt.In the circuit arrangement according to the invention, the two transistors connected to current control circuits at their control inputs, which ensure that the conduction paths of the transistors flowing currents are limited to first or second maximum values. The Current limiting value of the first transistor is greater than the current limiting value of the second transistor. This is, as already related above with the description of those known in the prior art Circuit arrangement mentioned, due to the sample scatter of the transistors in itself the normal case. This normal case becomes conscious according to the invention exploited, namely by the voltage drop across the first transistor increased with the second transistor in the current limit is thus a part of those otherwise absorbed by the second transistor Transfer power to the first transistor. Because according to the invention is the control signal at the control input of the first transistor if a current flows with the size of the second maximum value, such adjustable that a voltage across the line path of the first transistor drops that is greater than the voltage that would drop if over the conduction path of the first transistor has a current the size of the second Maximum value flows.
Die Beeinflussung des Steuersignals am Steuereingang des ersten Transistors kann durch einfache Rückführung des Spannungsabfalls über dem ersten Transistor realisiert werden. Eine Verkopplung bzw. zusätzliche Verschaltung der Strombegrenzungsschaltungen beider Transistoren ist also bei der erfindungsgemäßen Schaltungsanordnung nicht erforderlich, so dass durch denkbar geringen Aufwand eine gleichmäßigere Verteilung der in den beiden Transistoren umzusetzenden Verlustleistung erzielt wird bzw. verhindert wird, dass einer der beiden Transistoren deutlich mehr Verlustleistung aufzunehmen hat als der andere. Influencing the control signal at the control input of the first transistor can be done by simply returning the voltage drop across the first Transistor can be realized. A coupling or additional interconnection the current limiting circuits of both transistors is in the invention Circuitry not required, so that by conceivable little effort a more even distribution of the two transistors power loss to be implemented is achieved or prevented, that one of the two transistors absorb significantly more power loss has than the other.
In vorteilhafter Weiterbildung ist ein Vergleicher zum Vergleich des Spannungsabfalls über dem Leitungspfad des ersten Transistors mit einer Referenzspannung vorgesehen. Dieser Vergleicher gibt dann, wenn der Spannungsabfall über dem Leitungspfad des ersten Transistors größer ist als die Referenzspannung, ein Ausgangssignal zur Beeinflussung des ersten Steuersignals für den Steuereingang des ersten Transistors aus. Eine noch einfachere Rückführung des Spannungsabfalls über dem ersten Transistor auf dessen Steuereingang wird dadurch realisiert, dass die Strombegrenzungsschaltung des ersten Transistors in Abhängigkeit von einer eine Referenzspannung liefernden ersten Spannungsquelle gesteuert ist und dass der erste Transistor als Spannungsfolger geschaltet ist. Damit kann der Spannungsabfall über dem ersten Transistor zumindest für eine definierte Zeit oder einen definierten Betriebszustand nicht größer werden als die Referenzspannung, es gilt also, dass der Spannungsabfall über dem Transistor im wesentlichen gleich der Referenzspannung ist.An advantageous further development is a comparator for comparing the voltage drop over the line path of the first transistor with a reference voltage intended. This comparator then gives when the voltage drop over the conduction path of the first transistor is larger than that Reference voltage, an output signal for influencing the first control signal for the control input of the first transistor. An even easier one Feedback of the voltage drop across the first transistor to its Control input is realized in that the current limiting circuit of the first transistor as a function of a reference voltage supplying first voltage source is controlled and that the first transistor is connected as a voltage follower. So that the voltage drop over the first transistor at least for a defined time or a defined Operating state does not become greater than the reference voltage, it applies So that the voltage drop across the transistor is essentially the same the reference voltage.
Nachfolgend wird die Erfindung anhand der Zeichnung näher erläutert. Im einzelnen zeigen:
- Fig. 1
- eine Schaltungsanordnung gemäß dem Stand der Technik und
- Fign. 2 bis 4
- verschiedene Ausführungsbeispiele einer erfindungsgemäßen Schaltungsanordnung zum Betreiben einer Last über zwei mit der Last in Reihe zu schaltende Transistoren.
- Fig. 1
- a circuit arrangement according to the prior art and
- Fig. 2 to 4
- Various exemplary embodiments of a circuit arrangement according to the invention for operating a load via two transistors to be connected in series with the load.
Die Schaltungsanordnung gemäß Fig. 2 zeigt eine erste erfindungsgemäße
Möglichkeit einer verbesserten Leistungsverteilung auf die beiden Transistoren
M1 und M2 bei Stromfluss durch die Last R. Den Transistoren bzw. Stellgliedern
werden bewusst unterschiedliche Strombegrenzungen eingeprägt.
Dabei dient die Speisespannung SUG2 der Strombegrenzungsschaltung CL2
für den Transistor M2 zur Erzeugung der Steuerspannung UG2 für den Transistor
M2. In der Strombegrenzungsschaltung CL2 für den Transistor M2 wird
diese Spannung so geregelt, dass über dem Transistor M2 ein maximaler
Strom Ilim(M2) eingestellt wird. Ähnliches geschieht normalerweise auch für den
Transistor M1. Erfindungsgemäß jedoch wird bewusst eine Strombegrenzung
für den Transistor M1 eingestellt, welche größer ist als die Strombegrenzung
für den Transistor M2. Es gilt also:
Ilim(M1) ist größer als Ilim(M2).The circuit arrangement according to FIG. 2 shows a first possibility according to the invention of an improved power distribution to the two transistors M1 and M 2 when current flows through the load R. The transistors or actuators are deliberately impressed with different current limits. The supply voltage SUG2 of the current limiting circuit CL2 for the transistor M2 is used to generate the control voltage UG2 for the transistor M2. This voltage is regulated in the current limiting circuit CL2 for the transistor M2 in such a way that a maximum current I lim (M2) is set via the transistor M2. The same normally happens for transistor M1. According to the invention, however, a current limitation for transistor M1 is deliberately set which is greater than the current limitation for transistor M2. So the following applies:
I lim (M1) is greater than I lim (M2) .
Das bedeutet, dass im Fall einer Überlast als erstes immer der Spannungsabfall U2 über M2 erhöht wird, da Ilim(M2) die Begrenzung bestimmt. Der Transistor M1 würde normalerweise relativ wenig belastet werden. Durch eine Rückführung wird der Spannungsabfall (Differenz zwischen US und U1) über dem Transistor M1 mit einer Referenzspannung UREF in der Regelung C verglichen. Die Steuerspannung UG1 für den Transistor M1 wird durch die Strombegrenzungsschaltung CL1 des Transistors M1 so eingestellt, dass zusätzlich zu der Strombegrenzung Ilim(M1) an U1 Spannungsgleichheit mit UREF besteht. Es gilt also zumindest für eine definierte Zeit oder einen definierten Betriebszustand, dass U1 gleich UREF ist. Damit wird der Spannungsabfall über dem Transistor M1 künstlich erhöht und ein Teil der andernfalls von dem Transistor M2 aufzunehmenden Leistung wird auf den Transistor M1 "gezogen".This means that in the event of an overload, the voltage drop U2 above M2 is always increased first, since I lim (M2) determines the limitation. The transistor M1 would normally be loaded relatively little. The voltage drop (difference between US and U1) across the transistor M1 is compared with a reference voltage UREF in the control C by a feedback. The control voltage UG1 for the transistor M1 is set by the current limiting circuit CL1 of the transistor M1 such that in addition to the current limitation I lim (M1) at U1 there is voltage equality with UREF. It therefore applies at least for a defined time or a defined operating state that U1 is UREF. The voltage drop across transistor M1 is thus artificially increased and part of the power otherwise to be absorbed by transistor M2 is "pulled" onto transistor M1.
Die Referenzspannung UREF ist frei wählbar und damit ist auch die Leistungsverteilung auf die beiden Transistoren M1 und M2 frei wählbar. Die Referenzspannung UREF kann über einen Spannungsteiler aus der Versorgungsspannung US erzeugt werden oder mit einer festen Spannung beaufschlagt werden, so dass bei Überschreiten dieser Spannung an U1 der Spannungsabfall und damit die Leistungsaufnahme minimiert wird oder dann erst voll wirksam wird. Auch Kombinationen aus festen und proportionalen Spannungsanteilen an UREF oder eine Änderung über der Zeit sind möglich.The reference voltage UREF is freely selectable and so is the power distribution freely selectable on the two transistors M1 and M2. The reference voltage UREF can be made using a voltage divider from the supply voltage US generated or applied with a fixed voltage, so that when this voltage at U1 is exceeded, the voltage drop and so the power consumption is minimized or only then fully effective becomes. Combinations of fixed and proportional voltage components to UREF or a change over time is possible.
Ein weiteres Ausführungsbeispiel der erfindungsgemäßen Schaltungsanordnung zeigt Fig. 3. Diese Schaltungsanordnung ist gegenüber der Schaltungsanordnung gemäß Fig. 2 insofern vereinfacht, als auf die Rückführung der Spannung an U1 verzichtet wird und die zum Steuern der Strombegrenzungsschaltung CL1 für den Transistor M1 benötigte Steuerspannung RSUG1 der Schaltungsanordnung gemäß Fig. 2 direkt aus der Referenzspannung UREF erzeugt wird. Dies gelingt, indem der Transistor M1 als Spannungsfolger geschaltet ist. Auch in dem Beispiel gemäß Fig. 3 gilt zumindest für eine definierte Zeit oder einen definierten Betriebszustand, dass die Spannung an U1 im wesentlichen gleich der Referenzspannung UREF ist.Another embodiment of the circuit arrangement according to the invention shows Fig. 3. This circuit arrangement is compared to the circuit arrangement 2 simplified to the extent that the return of the Voltage at U1 is dispensed with and that for controlling the current limiting circuit CL1 required for the transistor M1 control voltage RSUG1 2 directly from the reference voltage UREF is produced. This is achieved by switching transistor M1 as a voltage follower is. Also in the example according to FIG. 3, at least one applies Time or a defined operating state that the voltage at U1 is substantially equal to the reference voltage UREF.
Mit der erfindungsgemäßen Schaltungsanordnung lässt sich ein weiter Bereich von Leistungsverteilungen über Ort, Arbeitsbedingungen (Spannung) und Zeit einstellen, ohne dass es einer Verkopplung der Strombegrenzungsschaltungen der beiden Transistoren M1 und M2 bedarf. Das bedeutet, dass die Transistoren M1 und M2 örtlich weit auseinanderliegend angeordnet sein können. Damit können auf einfache Weise die Transistoren M1 und M2 in ihren Belastbarkeiten optimiert werden.A wide range can be achieved with the circuit arrangement according to the invention of power distributions over location, working conditions (voltage) and time adjust without there being a coupling of the current limiting circuits of the two transistors M1 and M2 is required. That means the transistors M1 and M2 can be arranged locally far apart. The transistors M1 and M2 can thus be loaded in a simple manner be optimized.
In den hier beschriebenen Ausführungsbeispielen ist stets angenommen worden, dass der Spannungsabfall über dem Transistor M1 künstlich erhöht wird. Es ist aber auch ebenso denkbar, den Spannungsabfall über dem Transistor M2 künstlich zu erhöhen; mit anderen Worten können die in den Fign. 2 und 3 gezeigten Schaltungsanordnungen auch umgekehrt realisiert werden. In diesen Fällen würde die Referenzspannung UREF auf U2 wirken und Ilim(M2) größer als Ilim(M1) sein.In the exemplary embodiments described here, it has always been assumed that the voltage drop across transistor M1 is artificially increased. However, it is also conceivable to artificially increase the voltage drop across transistor M2; in other words, those in FIGS. 2 and 3 circuit arrangements shown can also be realized vice versa. In these cases, the reference voltage UREF would act on U2 and I lim (M2) would be greater than I lim (M1) .
Die in den Fign. 2 und 3 dargestellten Schaltungsanordnungen lassen sich auch zu einer (Voll-)Brückenschaltung ergänzen. Fig. 4 zeigt eine solche Vollbrückenschaltung für die Schaltungsvariante gemäß Fig. 2. Je nach Richtung des Stroms durch die Last R fließt dieser entweder über das Transistorenpaar M1,M4 oder M2,M3.The in Figs. 2 and 3 circuit arrangements shown can be also add to a (full) bridge circuit. Fig. 4 shows such a full bridge circuit for the circuit variant according to FIG. 2. Depending on the direction of the current through the load R either flows through the pair of transistors M1, M4 or M2, M3.
Claims (3)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10002037A DE10002037C1 (en) | 2000-01-19 | 2000-01-19 | Circuit arrangement for operating a load via two transistors |
| DE10002037 | 2000-01-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP1118922A1 true EP1118922A1 (en) | 2001-07-25 |
| EP1118922B1 EP1118922B1 (en) | 2003-07-09 |
Family
ID=7627962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP00127024A Expired - Lifetime EP1118922B1 (en) | 2000-01-19 | 2000-12-09 | Electrical circuit to control a load with two transistors |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6337587B2 (en) |
| EP (1) | EP1118922B1 (en) |
| AT (1) | ATE244906T1 (en) |
| DE (2) | DE10002037C1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19841445C2 (en) * | 1998-09-10 | 2002-04-25 | Infineon Technologies Ag | Semiconductor circuit arrangement |
| DE10049774C2 (en) * | 2000-09-29 | 2002-11-07 | Infineon Technologies Ag | Push-pull output stage for digital signals with regulated output levels |
| JP2002290221A (en) * | 2001-03-27 | 2002-10-04 | Nec Corp | Power conservation circuit for semiconductor output circuit |
| JP4323756B2 (en) * | 2002-05-01 | 2009-09-02 | キヤノン株式会社 | Recording device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB937506A (en) * | 1960-12-01 | 1963-09-25 | Westinghouse Brake & Signal | Improvements relating to power transistors and voltage regulating circuits therefor |
| CH389039A (en) * | 1961-07-20 | 1965-03-15 | Standard Telephon & Radio Ag | Voltage-stabilized DC power supply |
| GB1105259A (en) * | 1964-12-10 | 1968-03-06 | Goerz Electro Gmbh | A voltage stabilising circuit |
| JPS59128617A (en) * | 1983-01-12 | 1984-07-24 | Matsushita Electric Ind Co Ltd | Output device of current |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2990889B2 (en) * | 1991-09-27 | 1999-12-13 | 日本電気株式会社 | Magnetic head drive circuit |
| EP0782268B1 (en) * | 1995-12-29 | 2002-04-24 | STMicroelectronics S.r.l. | Supply voltages switch circuit |
| JP2000268309A (en) * | 1999-03-19 | 2000-09-29 | Mitsubishi Electric Corp | Writing current driving circuit |
| US6262620B1 (en) * | 1999-11-02 | 2001-07-17 | Ranco Incorporated Of Delaware | Driver circuitry for latching type valve and the like |
-
2000
- 2000-01-19 DE DE10002037A patent/DE10002037C1/en not_active Expired - Fee Related
- 2000-12-09 EP EP00127024A patent/EP1118922B1/en not_active Expired - Lifetime
- 2000-12-09 AT AT00127024T patent/ATE244906T1/en not_active IP Right Cessation
- 2000-12-09 DE DE50002823T patent/DE50002823D1/en not_active Expired - Lifetime
-
2001
- 2001-01-19 US US09/764,206 patent/US6337587B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB937506A (en) * | 1960-12-01 | 1963-09-25 | Westinghouse Brake & Signal | Improvements relating to power transistors and voltage regulating circuits therefor |
| CH389039A (en) * | 1961-07-20 | 1965-03-15 | Standard Telephon & Radio Ag | Voltage-stabilized DC power supply |
| GB1105259A (en) * | 1964-12-10 | 1968-03-06 | Goerz Electro Gmbh | A voltage stabilising circuit |
| JPS59128617A (en) * | 1983-01-12 | 1984-07-24 | Matsushita Electric Ind Co Ltd | Output device of current |
Non-Patent Citations (1)
| Title |
|---|
| PATENT ABSTRACTS OF JAPAN vol. 008, no. 259 (P - 317) 28 November 1984 (1984-11-28) * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20010008380A1 (en) | 2001-07-19 |
| DE50002823D1 (en) | 2003-08-14 |
| DE10002037C1 (en) | 2001-08-23 |
| US6337587B2 (en) | 2002-01-08 |
| ATE244906T1 (en) | 2003-07-15 |
| EP1118922B1 (en) | 2003-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE19817767A1 (en) | Semiconductor power circuit | |
| DE102014108576B4 (en) | Driver circuit with Miller clamping functionality for power semiconductor switches, power semiconductor switches and inverter bridges | |
| DE102006054354A1 (en) | Protective circuit for electrical appliance, has short circuit short circuiting output or input clamps during exceedance of threshold value, where control signal regulates limit has same origin as that of circuit that controls short circuit | |
| DE69604761T2 (en) | Power supply for a microcomputer | |
| WO2006072292A1 (en) | Circuit arrangement and method for protecting a circuit from electrostatic discharges | |
| DE102004062032A1 (en) | Circuit arrangement for rapid reduction of an induced current | |
| EP0973084B1 (en) | Integrated circuit with a voltage regulator | |
| EP1118922B1 (en) | Electrical circuit to control a load with two transistors | |
| EP0374288B1 (en) | Integrated circuit diminishing the inverse current of an inversely polarized transistor | |
| EP0957420B1 (en) | Clamping circuit | |
| DE19838109B4 (en) | Control circuit for inductive loads | |
| DE102010010103B3 (en) | Electronic device for controlling current through ignition tablet, has metal oxide semiconductor transistor which is coupled with gate at common gate node and with source connection at ground | |
| DE69812755T2 (en) | Protection circuit against short circuits | |
| EP0876699B1 (en) | Current limiting circuit | |
| DE102006054547B4 (en) | Chip with voltage regulation circuitry | |
| DE2202894A1 (en) | Power supply device for electronic systems | |
| EP1038355B1 (en) | Buffer circuit | |
| DE2404850C3 (en) | Electronic fuse for a push-pull amplifier | |
| DD277562A1 (en) | CIRCUIT FOR CURRENT LIMITATION WITH FOLDBACK BEHAVIOR | |
| EP0741881B1 (en) | Integrated circuit | |
| DE3891380C2 (en) | Amplifier with four transistors connected in a bridge circuit | |
| DE10349629B4 (en) | Electronic circuit | |
| EP0881735A2 (en) | Circuit arrangement for a power supply unit | |
| DE2529883B1 (en) | Circuit arrangement for overload protection | |
| DE19621500B4 (en) | Device for driving a consumer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
| AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
| 17P | Request for examination filed |
Effective date: 20010824 |
|
| 17Q | First examination report despatched |
Effective date: 20011025 |
|
| AKX | Designation fees paid |
Free format text: AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
| AK | Designated contracting states |
Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20030709 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20030709 |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
| REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
| REF | Corresponds to: |
Ref document number: 50002823 Country of ref document: DE Date of ref document: 20030814 Kind code of ref document: P |
|
| REG | Reference to a national code |
Ref country code: CH Ref legal event code: NV Representative=s name: HEPP, WENGER & RYFFEL AG |
|
| REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: GERMAN |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20031009 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20031009 Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20031009 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20031020 |
|
| GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20031110 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20031209 Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20031209 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20031209 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20031231 |
|
| ET | Fr: translation filed | ||
| PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
| 26N | No opposition filed |
Effective date: 20040414 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: CH Payment date: 20081222 Year of fee payment: 9 Ref country code: IE Payment date: 20081218 Year of fee payment: 9 Ref country code: NL Payment date: 20081219 Year of fee payment: 9 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: AT Payment date: 20081218 Year of fee payment: 9 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: IT Payment date: 20081223 Year of fee payment: 9 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20081216 Year of fee payment: 9 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20081219 Year of fee payment: 9 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: BE Payment date: 20090107 Year of fee payment: 9 |
|
| BERE | Be: lapsed |
Owner name: *ELMOS SEMICONDUCTOR A.G. Effective date: 20091231 |
|
| REG | Reference to a national code |
Ref country code: NL Ref legal event code: V1 Effective date: 20100701 |
|
| REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
| GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20091209 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: AT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091209 |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20100831 |
|
| REG | Reference to a national code |
Ref country code: IE Ref legal event code: MM4A |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091231 Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091231 Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091231 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091231 Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091209 Ref country code: NL Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20100701 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091209 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20091209 |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 50002823 Country of ref document: DE Representative=s name: VON KREISLER SELTING WERNER - PARTNERSCHAFT VO, DE |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 50002823 Country of ref document: DE Representative=s name: DOMPATENT VON KREISLER SELTING WERNER - PARTNE, DE Effective date: 20150108 Ref country code: DE Ref legal event code: R082 Ref document number: 50002823 Country of ref document: DE Representative=s name: VON KREISLER SELTING WERNER - PARTNERSCHAFT VO, DE Effective date: 20150108 Ref country code: DE Ref legal event code: R081 Ref document number: 50002823 Country of ref document: DE Owner name: ELMOS SEMICONDUCTOR AKTIENGESELLSCHAFT, DE Free format text: FORMER OWNER: ELMOS SEMICONDUCTOR AG, 44227 DORTMUND, DE Effective date: 20150108 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20191217 Year of fee payment: 20 |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 50002823 Country of ref document: DE Representative=s name: DOMPATENT VON KREISLER SELTING WERNER - PARTNE, DE Ref country code: DE Ref legal event code: R081 Ref document number: 50002823 Country of ref document: DE Owner name: ELMOS SEMICONDUCTOR SE, DE Free format text: FORMER OWNER: ELMOS SEMICONDUCTOR AKTIENGESELLSCHAFT, 44227 DORTMUND, DE |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R071 Ref document number: 50002823 Country of ref document: DE |