EP1095404A1 - Circuit and a method for the production thereof - Google Patents

Circuit and a method for the production thereof

Info

Publication number
EP1095404A1
EP1095404A1 EP99945844A EP99945844A EP1095404A1 EP 1095404 A1 EP1095404 A1 EP 1095404A1 EP 99945844 A EP99945844 A EP 99945844A EP 99945844 A EP99945844 A EP 99945844A EP 1095404 A1 EP1095404 A1 EP 1095404A1
Authority
EP
European Patent Office
Prior art keywords
pressure contact
circuit arrangement
layer
mask
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP99945844A
Other languages
German (de)
French (fr)
Inventor
Thomas Scherg
Josef-Georg Bauer
Hans-Joachim Schulze
Markus Schwerd
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1095404A1 publication Critical patent/EP1095404A1/en
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
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    • H01L24/71Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
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    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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    • H01L2924/1305Bipolar Junction Transistor [BJT]
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    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the invention relates to a circuit arrangement and method for its production.
  • Power semiconductor components such as the IGBT and high-voltage diodes
  • IGBT and high-voltage diodes are currently used in industrial drives and in local transportation, such as metro or light rail. In the future, they will also be used in long-distance railways, large drives, energy transfers and AC switches.
  • Chips i.e. Substrates in which the power semiconductor components or high-voltage diodes are arranged are soldered to a carrier, which in turn is soldered to a base plate. Connections of the chip are connected to the carrier via lines.
  • the carrier is placed in a housing that is hermetically sealed with a soft potting compound.
  • the other pressure housing is used as the structure. Foils made of molybdenum are applied over the connections of the chip, which are located on a front side and a back side of the chip, over which copper blocks are arranged in each case.
  • the chip is placed together with the copper blocks in a housing which exerts pressure on the copper blocks, as a result of which thermal and electrical contact is established between the connections and the copper blocks.
  • Pressure housings are currently used for high-voltage thyristors, diodes and GTOs. Pressure housings appear less suitable for IGBTs or diodes, since the pressure exerted can destroy the connections and the passivation of the chips, which comprise the IGBTs or the diodes, and thus the chips themselves.
  • the invention is based on the problem of specifying a further circuit arrangement which can be arranged in a pressure housing, wherein the circuit arrangement can also be an IGBT or a diode. Furthermore, a method for producing such a circuit arrangement is to be specified.
  • connections of the circuit arrangement are modified compared to the prior art in such a way that the circuit arrangement can be arranged in a pressure housing without a required pressure being able to destroy the connections or the passivation.
  • a pressure contact is arranged on a conductive region of the circuit arrangement to be connected.
  • the pressure contact protrudes over a passivation layer, so that no pressure that could destroy it is exerted on the passivation layer. Since the passivation layer does not absorb the pressure, the pressure leads to an efficient contacting of the pressure contact to the outside.
  • the conductive region can be a metallization level of the circuit arrangement.
  • the connections are reinforced by the pressure contact. The stability of the connections increases because the pressure contact increases the thickness of the connections.
  • the pressure contact can replace the metallization level.
  • the conductive region is part of a substrate in which the circuit arrangement is arranged, such as, for example, se a source region, a drain region or a weakly doped region.
  • the pressure contact forms the connections and is thicker and therefore more stable than the metallization level in the prior art.
  • the pressure contact contains metal.
  • the metal is preferably copper, since copper has a high electrical conductivity, which is greater than aluminum, which is used in the prior art for the metallization level.
  • the thermal conductivity and heat capacity of copper is also great. This is particularly advantageous with power semiconductor components since they generate a lot of heat that has to be dissipated.
  • a lower surface of the pressure contact is adjacent to the conductive area.
  • An upper surface of the pressure contact opposite the lower surface is essentially flat even if the conductive region is highly structured. Any unevenness that may occur is very small and in particular does not correspond to the shape of the conductive area.
  • the thickness of the unevenness corresponds to a grain size of the metal of the pressure contact, which is dependent on the process parameters.
  • the bumps can e.g. range from less than 50nm to 200nm. Due to the flat upper surface, the pressure contact can be contacted particularly effectively. If a film, e.g.
  • the entire upper surface can adjoin the film and a contact resistance between the pressure contact and the film is compared to an uneven surface in which the film only increased Places of the surface touched, lowered.
  • the pressure contact can have essentially vertical flanks. Starting from a limitation of the dimensions of the upper surface of the pressure contact due to the minimal, photolithographically producible structure size, this is in contrast to pressure contacts whose cross section increases towards the bottom. ßert, especially advantageous at a metallization level with narrow conductor tracks, since a higher packing density is easier to implement.
  • the circuit arrangement can initially be generated by a conventional method, which is followed only by an additional process for generating the pressure contact.
  • An integration of a method according to the invention for generating the circuit arrangement into the currently widespread semiconductor production is consequently particularly simple.
  • a mask is applied over the conductive region, which mask does not cover a region of the conductive region to be contacted.
  • the metal is deposited by a galvanic process with electricity (electro-plating), which creates the pressure contact.
  • electro-plating electricity
  • the deposition is ended as long as the upper surface of the pressure contact lies below an upper surface of the mask, since the upper surface of the pressure contact would otherwise bulge outwards and thus become uneven.
  • the flanks of the pressure contact adapt to the shape of the mask and can therefore be generated essentially vertically.
  • all metals that can be deposited with electricity through the galvanic process are suitable as the metal of the pressure contact. These are, for example, silver, gold and nickel.
  • the deposition process in the galvanic process with electricity is orders of magnitude faster, which significantly reduces process costs.
  • the separation speed is between 0.4 ⁇ m / min and 4 ⁇ m / in, for example. which are formed by the conductive region are not or only slightly compensated for by conventional deposition of metal, which is why an upper surface of a pressure contact produced by conventional deposition is much more difficult to contact.
  • by depositing the entire surface and then structuring a thick metal layer no vertical flanks can be produced, which, as explained above, leads to a low packing density. In general, it is unfavorable to deposit thick layers over the entire surface, since layer stresses can lead to bending of the circuit arrangement or to peeling or tearing of the layers.
  • layer stresses in the pressure contact can be avoided in the method according to the invention if the galvanic process is carried out at room temperature.
  • Part of the pressure contact can fill a depression in which the ratio of a vertical dimension of the depression to a horizontal dimension of the depression is greater than 4: 1, the horizontal dimension being between 0.5 ⁇ m and 8 ⁇ m. This is not possible with conventional deposition processes, since with such large aspect ratios cavities would arise in the lower areas of the depression. The ratio can also be smaller.
  • a conductive layer is applied to the conductive area, over which the mask is produced.
  • a voltage is applied between the conductive layer and an electrolyte applied to the circuit arrangement.
  • parts of the conductive layer located outside the pressure contact are removed in order to avoid undesired short circuits.
  • the conductive layer is preferably particularly thin in order to facilitate the later removal of its parts.
  • the conductive layer also serves as a crystallization layer (seed layer) ie as a layer on which the metal of the pressure contact grows particularly easily.
  • Copper is particularly suitable as the material for the conductive layer if the metal is also copper.
  • a layer which acts as a diffusion barrier can be applied before the conductive layer is produced. After removing the mask, the layer, which acts as a diffusion barrier, is structured analogously to the conductive layer.
  • Ti, TiN, Ta, TaN and / or TaSi is suitable as the material for the diffusion barrier.
  • the diffusion barrier is, for example, 10-50 nm thick. If the diffusion barrier is conductive, it is structured analogously to the conductive layer in order to avoid short circuits.
  • a layer on the pressure contact is suitable as the material for the layer that prevents corrosion.
  • the palladium and / or gold is applied in a thickness of approx. 10 nm - 1 ⁇ m by electroless plating. Since the palladium and / or gold only grows on metallic surfaces, the layer that prevents corrosion is automatically formed only on surfaces of the pressure contact and does not have to be structured.
  • a layer which contains, for example, TaN, WTi, TiN, TaSi or Ta is deposited or sputtered on and then structured by a photolithographic process in such a way that it only covers the exposed areas of the pressure contact.
  • Another additional pressure contact according to the invention can also be attached to a back of the substrate.
  • a film which essentially contains molybdenum, can be applied over the pressure contact, over which a copper block is arranged.
  • the circuit arrangement can then be encased in a ceramic housing. be built, whereby the copper block and the foil is pressed onto the pressure contact and thereby an electrical and thermal contact is produced.
  • the circuit arrangement is, for example, a MOSFET, an IGBT, a diode, a GTO, a high-voltage thyristor or another power semiconductor component or high-voltage diode.
  • the circuit arrangement has in particular few connections and is suitable for operation with high voltages and / or high currents.
  • FIG. 1 shows a cross section through a substrate after an IGBT with a metallization level and a passivation layer has been produced.
  • Figure 2 shows the cross section of Figure 1 after a
  • FIG. 3 shows the cross section from FIG. 2 after the mask has been removed, the layer which acts as a diffusion barrier and the conductive layer has been structured and a layer which prevents corrosion has been produced.
  • FIG. 4 shows an enlarged section from FIG. 3.
  • FIG. 5 shows a cross section through the substrate after foils and copper blocks have been applied and the substrate has been packed in a ceramic housing.
  • the figures are not to scale.
  • a circuit arrangement comprises an IGBT which is arranged in a substrate 1.
  • Source regions G are connected to a metallization level M arranged from the substrate 1 (see FIG. 1).
  • Passivation layer S which contains oxide, nitride and polymide, applied and structured photolithographically in such a way that a region of the circuit arrangement to be contacted, i.e. part of the metallization level M is exposed (see FIG. 1).
  • an approximately 50 nm thick layer B which serves as a diffusion barrier, is deposited over the entire surface (see FIG. 2).
  • An approximately 50 nm thick conductive layer L is deposited over the entire surface by sputtering (see FIG. 2).
  • An approximately 10 ⁇ m thick mask P is then produced from photoresist and does not cover at least a part of the part of the metallization level M covered by the layer B, which serves as a diffusion barrier, and the conductive layer L.
  • the conductive layer L is connected to a first voltage connection.
  • the circuit arrangement is immersed in an electrolyte Y, which essentially contains CUSO4, H2SO, CL ⁇ and additives and is connected via an electrode E to a second voltage connection.
  • a current of approximately 2 A / dm2 is impressed between the electrode E and the conductive layer L.
  • copper is applied to the conductive layer L, which serves as a crystallization layer (seed layer), and between flanks of the mass ke P applied.
  • the galvanic process is ended after approx. 9 minutes.
  • An approximately 9 ⁇ m thick pressure contact D made of copper is produced, which has an essentially flat upper surface which lies below an upper surface of the mask P (see FIG. 2).
  • the pressure contact D has essentially vertical flanks and extends beyond the passivation layer S (see FIG. 3).
  • palladium grows to a thickness of approx. 500nm on exposed surfaces of the pressure contact.
  • Gold is then grown on the palladium by a further currentless galvanic process in a thickness of approximately 50 nm.
  • An approximately 550 nm thick layer K is formed on the surfaces of the pressure contact D, which prevents corrosion and contains palladium and gold (see FIG. 3).
  • FIG. 4 shows an enlarged section from FIG. 3, from which it becomes clear that the metallization plane M has depressions in the region of the source regions G.
  • a vertical dimension v of the depressions is approximately 3 times as large as a horizontal dimension h of the depressions.
  • a film F which essentially contains molybdenum, is applied over the pressure contact D and over one side of the substrate 1 facing away from the metallization plane M.
  • a copper block C is arranged above the foils M made of molybdenum.
  • the circuit arrangement is packed in a ceramic housing H.
  • Many variations of the exemplary embodiment are conceivable, which are also within the scope of the invention. So dimensions of the layers can be adapted to the respective requirements.
  • the thickness of the mask P is always so great that the upper surface of the pressure contact D lies below the upper surface of the mask P.
  • the mask P can also be arranged on parts of the layer B, which serves as a diffusion barrier, which originally cover parts of the metallization level M.
  • layer K which prevents corrosion
  • z. B. TaN, WTi, TaSi, Ta or TiN can be used as the material.
  • the layer K is applied over the entire surface.
  • the layer K, which prevents corrosion, is electrically conductive, it is then structured so that it essentially covers only areas of the pressure contact D.
  • the circuit arrangement can also be a MOSFET, a diode, a GTO, a high-voltage thyristor or another power semiconductor component.

Abstract

According to the invention, a pressure contact (D) is arranged on a conducting region of the circuit in order to reinforce the connections of the circuit. Said pressure contact contains metal, e.g. copper, comprises an essentially planar upper surface which is situated above a passivation layer (S), and has flanks which are, to a large extent, essentially vertical. The metal is electrodeposited using a mask (P) which does not cover an area of the conducting region that is to be contacted, thus resulting in the production of the pressure contact (D). The electrodeposition process is concluded as long as the upper surface of the pressure contact (D) is situated underneath an upper surface of the mask (P). A conducting layer (L) which, for example, contains copper can be deposited on the conducting region in order to permit the application of a current for the electrodeposition process and can be deposited as a crystallization base.

Description

Beschreibungdescription
Schaltungsanordnung und Verfahren zu deren HerstellungCircuit arrangement and method for the production thereof
Die Erfindung betrifft eine Schaltungsanordnung und Verfahren zu deren Herstellung.The invention relates to a circuit arrangement and method for its production.
Leistungshalbleiter-Bauelemente, wie der IGBT und Hochvoltdioden, werden derzeit in Industrieantrieben und in Nahver- kehrsmittel, wie Metro oder Stadtbahn, eingesetzt. Zukünftig sollen sie auch in Fernbahnen, Großantrieben, Energieübertragungen und AC-Schaltern verwendet werden.Power semiconductor components, such as the IGBT and high-voltage diodes, are currently used in industrial drives and in local transportation, such as metro or light rail. In the future, they will also be used in long-distance railways, large drives, energy transfers and AC switches.
Als Aufbau verwendet man zum einen den sogenannten Modulauf- bau. Dabei werden Chips, d.h. Substrate, in denen die Leistungshalbleiter-Bauelemente oder Hochvoltdioden angeordnet sind, auf einen Träger gelötet, der wiederum auf eine Bodenplatte gelötet wird. Über Leitungen werden Anschlüsse des Chips mit dem Träger verbunden. Der Träger wird in ein Gehäu- se angeordnet, das mit einem Weichverguß hermetisch verschlossen wird.The so-called module structure is used for the structure. Chips, i.e. Substrates in which the power semiconductor components or high-voltage diodes are arranged are soldered to a carrier, which in turn is soldered to a base plate. Connections of the chip are connected to the carrier via lines. The carrier is placed in a housing that is hermetically sealed with a soft potting compound.
Als Aufbau verwendet man zum anderen Druckgehäuse. Über die Anschlüsse des Chips, die sich auf einer Vorderseite und ei- ner Rückseite des Chips befinden, werden Folien aus Molybdän aufgebracht, über die jeweils Kupferblöcke angeordnet werden. Der Chip wird zusammen mit den Kupferblöcken in einem Gehäuse angeordnet, das Druck auf die Kupferblöcke ausübt, wodurch ein thermischer und elektrischer Kontakt zwischen den An- Schlüssen und den Kupferblöcken entsteht. Druckgehäuse werden derzeit für Hochvoltthyristoren, Dioden und GTOs verwendet. Für IGBTs bzw. Dioden erscheinen Druckgehäuse weniger geeignet, da der ausgeübte Druck die Anschlüsse und die Passivie- rung der Chips, die die IGBTs bzw. die Dioden umfassen, und damit die Chips selber zerstören können. Der Erfindung liegt das Problem zugrunde, eine weitere Schaltungsanordnung anzugeben, die in einem Druckgehäuse angeordnet werden kann, wobei die Schaltungsanordnung auch ein IGBT oder eine Diode sein kann. Ferner soll ein Verfahren zur Her- Stellung einer solchen Schaltungsanordnung angegeben werden.The other pressure housing is used as the structure. Foils made of molybdenum are applied over the connections of the chip, which are located on a front side and a back side of the chip, over which copper blocks are arranged in each case. The chip is placed together with the copper blocks in a housing which exerts pressure on the copper blocks, as a result of which thermal and electrical contact is established between the connections and the copper blocks. Pressure housings are currently used for high-voltage thyristors, diodes and GTOs. Pressure housings appear less suitable for IGBTs or diodes, since the pressure exerted can destroy the connections and the passivation of the chips, which comprise the IGBTs or the diodes, and thus the chips themselves. The invention is based on the problem of specifying a further circuit arrangement which can be arranged in a pressure housing, wherein the circuit arrangement can also be an IGBT or a diode. Furthermore, a method for producing such a circuit arrangement is to be specified.
Das Problem wird gelöst durch eine Schaltungsanordnung gemäß Anspruch 1 sowie ein Verfahren zu deren Herstellung gemäß Anspruch 4. Ausgestaltungen der Erfindung gehen aus den übrigen Ansprüchen hervor.The problem is solved by a circuit arrangement according to claim 1 and a method for its production according to claim 4. Embodiments of the invention emerge from the remaining claims.
Die herkömmlichen Anschlüsse werden durch eine Metallisierungsebene der Schaltungsanordnung gebildet. In einer erfindungsgemäßen Schaltungsanordnung werden Anschlüsse der Schal- tungsanordnung gegenüber dem Stand der Technik derart modifiziert, daß die Schaltungsanordnung in einem Druckgehäuse angeordnet werden kann, ohne daß ein erforderlicher Druck die Anschlüsse oder die Passivierung zerstören kann.The conventional connections are formed by a metallization level of the circuit arrangement. In a circuit arrangement according to the invention, connections of the circuit arrangement are modified compared to the prior art in such a way that the circuit arrangement can be arranged in a pressure housing without a required pressure being able to destroy the connections or the passivation.
In der erfindungsgemäßen Schaltungsanordnung ist ein Druckkontakt auf einem anzuschließenden leitenden Gebiet der Schaltungsanordnung angeordnet. Der Druckkontakt ragt über einer Passivierungsschicht heraus, so daß auf die Passivierungsschicht kein Druck, der diese zerstören könnte, ausgeübt wird. Da die Passivierungsschicht den Druck nicht abfängt, führt der Druck zu einer effizienten Kontaktierung des Druckkontakts nach außen.In the circuit arrangement according to the invention, a pressure contact is arranged on a conductive region of the circuit arrangement to be connected. The pressure contact protrudes over a passivation layer, so that no pressure that could destroy it is exerted on the passivation layer. Since the passivation layer does not absorb the pressure, the pressure leads to an efficient contacting of the pressure contact to the outside.
Das leitende Gebiet kann eine Metallisierungsebene der Schal- tungsanordnung sein. Im Vergleich zum Stand der Technik werden die Anschlüsse durch den Druckkontakt verstärkt. Die Stabilität der Anschlüsse vergrößert sich, da der Druckkontakt die Dicke der Anschlüsse vergrößert.The conductive region can be a metallization level of the circuit arrangement. In comparison to the prior art, the connections are reinforced by the pressure contact. The stability of the connections increases because the pressure contact increases the thickness of the connections.
Der Druckkontakt kann die Metallisierungsebene ersetzen. In diesem Fall ist das leitende Gebiet Teil eines Substrats, in dem die Schaltungsanordnung angeordnet ist, wie beispielswei- se ein Source-Gebiet, ein Drain-Gebiet oder ein schwach dotiertes Gebiet. Der Druckkontakt bildet die Anschlüsse und ist dicker und damit stabiler als die Metallisierungsebene im Stand der Technik.The pressure contact can replace the metallization level. In this case, the conductive region is part of a substrate in which the circuit arrangement is arranged, such as, for example, se a source region, a drain region or a weakly doped region. The pressure contact forms the connections and is thicker and therefore more stable than the metallization level in the prior art.
Der Druckkontakt enthält Metall. Das Metall ist vorzugsweise Kupfer, da Kupfer eine hohe elektrische Leitfähigkeit besitzt, die größer als Aluminium ist, welches im Stand der Technik für die Metallisierungsebene verwendet wird. Auch die Wärmeleitfähigkeit und die Wärmekapazität von Kupfer ist groß. Gerade bei Leistungshalbleiter-Bauelementen ist dies von Vorteil, da sie viel Wärme erzeugen, die abgeführt werden muß .The pressure contact contains metal. The metal is preferably copper, since copper has a high electrical conductivity, which is greater than aluminum, which is used in the prior art for the metallization level. The thermal conductivity and heat capacity of copper is also great. This is particularly advantageous with power semiconductor components since they generate a lot of heat that has to be dissipated.
Eine untere Fläche des Druckkontakts grenzt an das leitende Gebiet an. Eine der unteren Fläche gegenüberliegende obere Fläche des Druckkontakts ist auch dann im wesentlichen eben, wenn das leitende Gebiet stark strukturiert ist. Eventuell auftretende Unebenheiten sind sehr klein und entsprechen ins- besondere nicht den Formen des leitenden Gebiets. Die Dicke der Unebenheiten entspricht einer Korngröße des Metalls des Druckkontakts, die abhängig von Verfahrensparameter ist. Die Unebenheiten können z.B. von unter 50nm bis 200nm reichen. Durch die ebene obere Fläche kann der Druckkontakt besonders effektiv kontaktiert werden. Wird eine Folie, die z.B. Molybdän, Silber, Gold und/oder Ruthenium enthält, auf den Druckkontakt angeordnet, kann die gesamte obere Fläche an die Folie angrenzen und ein Kontaktwiderstand zwischen dem Druckkontakt und der Folie ist im Vergleich zu einer unebenen Flä- ehe, bei der die Folie nur erhöhte Stellen der Fläche berührt, erniedrigt.A lower surface of the pressure contact is adjacent to the conductive area. An upper surface of the pressure contact opposite the lower surface is essentially flat even if the conductive region is highly structured. Any unevenness that may occur is very small and in particular does not correspond to the shape of the conductive area. The thickness of the unevenness corresponds to a grain size of the metal of the pressure contact, which is dependent on the process parameters. The bumps can e.g. range from less than 50nm to 200nm. Due to the flat upper surface, the pressure contact can be contacted particularly effectively. If a film, e.g. Containing molybdenum, silver, gold and / or ruthenium, arranged on the pressure contact, the entire upper surface can adjoin the film and a contact resistance between the pressure contact and the film is compared to an uneven surface in which the film only increased Places of the surface touched, lowered.
Der Druckkontakt kann im wesentlichen senkrechte Flanken aufweisen. Ausgehend von einer Begrenzung von Abmessungen der oberen Fläche des Druckkontakts durch die minimale, photolithographisch herstellbare Strukturgröße ist dies gegenüber Druckkontakten, deren Querschnitt sich nach unten hin vergrö- ßert, insbesondere bei einer Metallisierungsebene mit schmalen Leiterbahnen vorteilhaft, da eine höhere Packungsdichte leichter realisierbar ist.The pressure contact can have essentially vertical flanks. Starting from a limitation of the dimensions of the upper surface of the pressure contact due to the minimal, photolithographically producible structure size, this is in contrast to pressure contacts whose cross section increases towards the bottom. ßert, especially advantageous at a metallization level with narrow conductor tracks, since a higher packing density is easier to implement.
Die Schaltungsanordnung kann zunächst durch ein herkömmliches Verfahren erzeugt werden, dem sich lediglich ein zusätzlicher Prozeß zur Erzeugung des Druckkontakts anschließt. Eine Integration eines erfindungsgemäßen Verfahrens zur Erzeugung der Schaltungsanordnung in die derzeit verbreitete Halbleiterfer- tigung ist folglich besonders einfach.The circuit arrangement can initially be generated by a conventional method, which is followed only by an additional process for generating the pressure contact. An integration of a method according to the invention for generating the circuit arrangement into the currently widespread semiconductor production is consequently particularly simple.
Zur Herstellung der erfindungsgemäßen Schaltungsanordnung wird über dem leitenden Gebiet eine Maske aufgebracht, die einen zu kontaktierenden Bereich des leitenden Gebiets nicht bedeckt. Durch einen galvanischen Prozeß mit Strom (Elektro- Plating) wird das Metall abgeschieden, wodurch der Druckkontakt erzeugt wird. Damit die obere Fläche des Druckkontakts eben wird, wird das Abscheiden beendet, solange die obere Fläche des Druckkontakts unterhalb einer oberen Fläche der Maske liegt, da sich die obere Fläche des Druckkontakts sonst nach außen hin wölbt und damit uneben wird. Die Flanken des Druckkontaktes passen sich der Form der Maske an und können deshalb im wesentlichen senkrecht erzeugt werden.To produce the circuit arrangement according to the invention, a mask is applied over the conductive region, which mask does not cover a region of the conductive region to be contacted. The metal is deposited by a galvanic process with electricity (electro-plating), which creates the pressure contact. In order for the upper surface of the pressure contact to be flat, the deposition is ended as long as the upper surface of the pressure contact lies below an upper surface of the mask, since the upper surface of the pressure contact would otherwise bulge outwards and thus become uneven. The flanks of the pressure contact adapt to the shape of the mask and can therefore be generated essentially vertically.
Beim Abscheiden wird der Stromfluß z.B. wiederholt umgekehrt Alternativ wird ein Gleichstrom eingeprägt.When separating the current flow e.g. Repeatedly reversed Alternatively, a direct current is impressed.
Als Metall des Druckkontakts eignen sich neben Kupfer alle Metalle, die durch den galvanischen Prozeß mit Strom abge- schieden werden können. Dies sind beispielsweise Silber, Gold und Nickel.In addition to copper, all metals that can be deposited with electricity through the galvanic process are suitable as the metal of the pressure contact. These are, for example, silver, gold and nickel.
Im Vergleich zu einer herkömmlichen Abscheidung von Metall ist der Abscheideprozeß beim galvanischen Prozeß mit Strom um Größenordnungen schneller, was die Prozeßkosten erheblich senkt. Die Abscheidegeschwindigkeit beträgt beispielsweise zwischen 0,4 μm/min und 4 μm/ in. Auch werden Unebenheiten, die durch das leitende Gebiet gebildet werden, durch herkömmliches Abscheiden von Metall nicht oder wenig ausgeglichen, weshalb eine durch herkömmliche Abscheidung erzeugte obere Fläche eines Druckkontaktes sich wesentlich schlechter kon- taktieren läßt. Durch ganzflächiges Abscheiden und anschließendem Strukturieren einer dicken Metallschicht lassen sich darüber hinaus keine senkrechten Flanken erzeugen, was, wie oben erläutert, zu einer geringen Packungsdichte führt. Generell ist es ungünstig, dicke Schichten ganzflächig abzuschei- den, da Schichtspannungen zur Verbiegung der Schaltungsanordnung oder zum Abblättern oder Reißen der Schichten führen kann. Darüber hinaus können beim erfindungsgemäßen Verfahren Schichtspannungen im Druckkontakt vermieden werden, wenn der galvanische Prozeß bei Raumtemperatur durchgeführt wird.Compared to a conventional deposition of metal, the deposition process in the galvanic process with electricity is orders of magnitude faster, which significantly reduces process costs. The separation speed is between 0.4 μm / min and 4 μm / in, for example. which are formed by the conductive region are not or only slightly compensated for by conventional deposition of metal, which is why an upper surface of a pressure contact produced by conventional deposition is much more difficult to contact. In addition, by depositing the entire surface and then structuring a thick metal layer, no vertical flanks can be produced, which, as explained above, leads to a low packing density. In general, it is unfavorable to deposit thick layers over the entire surface, since layer stresses can lead to bending of the circuit arrangement or to peeling or tearing of the layers. In addition, layer stresses in the pressure contact can be avoided in the method according to the invention if the galvanic process is carried out at room temperature.
Ein Teil des Druckkontakts kann eine Vertiefung füllen, bei der das Verhältnis einer vertikalen Abmessung der Vertiefung zu einer horizontalen Abmessung der Vertiefung größer als 4:1 beträgt, wobei die horizontale Abmessung zwischen 0,5μm und 8μm beträgt. Mit herkömmlichen Abscheideprozessen ist dies nicht möglich, da bei derart großen Aspektverhältnissen Hohlräume in unteren Bereichen der Vertiefung entstehen würden. Das Verhältnis kann auch kleiner sein.Part of the pressure contact can fill a depression in which the ratio of a vertical dimension of the depression to a horizontal dimension of the depression is greater than 4: 1, the horizontal dimension being between 0.5 μm and 8 μm. This is not possible with conventional deposition processes, since with such large aspect ratios cavities would arise in the lower areas of the depression. The ratio can also be smaller.
Es liegt im Rahmen der Erfindung, wenn auf das leitende Gebiet eine leitende Schicht aufgebracht wird, über der die Maske erzeugt wird. Beim galvanischen Prozeß wird zwischen der leitenden Schicht und einem auf die Schaltungsanordnung aufgebrachten Elektrolyt eine Spannung angelegt. Nach Entfer- nung der Maske werden außerhalb des Druckkontaktes angeordnete Teile der leitenden Schicht entfernt, um unerwünschte Kurzschlüsse zu vermeiden. Die leitende Schicht ist vorzugsweise besonders dünn, um die spätere Entfernung seiner Teile zu erleichtern.It is within the scope of the invention if a conductive layer is applied to the conductive area, over which the mask is produced. In the galvanic process, a voltage is applied between the conductive layer and an electrolyte applied to the circuit arrangement. After the mask has been removed, parts of the conductive layer located outside the pressure contact are removed in order to avoid undesired short circuits. The conductive layer is preferably particularly thin in order to facilitate the later removal of its parts.
Besonders vorteilhaft ist es, wenn die leitende Schicht gleichzeitig als Kristallisationsschicht (Seedlayer) dient, d.h. als Schicht, auf der das Metall des Druckkontakts besonders leicht aufwächst. Als Material für die leitende Schicht eignet sich Kupfer besonders gut, wenn das Metall ebenfalls Kupfer ist. Um Diffusion zwischen der leitenden Schicht und dem leitenden Gebiet zu verhindern, kann vor Erzeugung der leitenden Schicht eine Schicht, die als Diffusionsbarriere wirkt, aufgebracht werden. Nach Entfernung der Maske wird die Schicht, die als Diffusionsbarriere wirkt, analog zur leitenden Schicht strukturiert. Als Material für die Diffusionsbar- riere ist beispielsweise Ti, TiN, Ta, TaN und/oder TaSi geeignet. Die Diffusionsbarriere ist beispielsweise 10-50 nm dick. Ist die Diffusionsbarriere leitend, so wird sie analog zur leitenden Schicht strukturiert, um Kurzschlüsse zu vermeiden.It is particularly advantageous if the conductive layer also serves as a crystallization layer (seed layer) ie as a layer on which the metal of the pressure contact grows particularly easily. Copper is particularly suitable as the material for the conductive layer if the metal is also copper. In order to prevent diffusion between the conductive layer and the conductive region, a layer which acts as a diffusion barrier can be applied before the conductive layer is produced. After removing the mask, the layer, which acts as a diffusion barrier, is structured analogously to the conductive layer. For example, Ti, TiN, Ta, TaN and / or TaSi is suitable as the material for the diffusion barrier. The diffusion barrier is, for example, 10-50 nm thick. If the diffusion barrier is conductive, it is structured analogously to the conductive layer in order to avoid short circuits.
Zum Schutz des Druckkontaktes gegen Korrosion ist es vorteilhaft, eine Schicht auf dem Druckkontakt aufzubringen. Als Material für die Schicht, die die Korrosion verhindert, ist beispielsweise Palladium und/oder Gold geeignet. Das Palladi- um und/oder Gold wird in einer Dicke von ca. 10 nm - 1 um durch stromlose Galvanik aufgebracht. Da dabei das Palladium und/oder Gold nur auf metallische Flächen aufwächst, entsteht die Schicht, die die Korrosion verhindert, automatisch nur an Flächen des Druckkontaktes und muß nicht strukturiert werden. Alternativ wird eine Schicht, die beispielsweise TaN, WTi, TiN, TaSi oder Ta enthält, abgeschieden oder aufgesputtert und durch ein photolithographisches Verfahren anschließend so strukturiert, daß sie lediglich die freiliegenden Flächen des Druckkontaktes bedeckt.To protect the pressure contact against corrosion, it is advantageous to apply a layer on the pressure contact. Palladium and / or gold, for example, is suitable as the material for the layer that prevents corrosion. The palladium and / or gold is applied in a thickness of approx. 10 nm - 1 μm by electroless plating. Since the palladium and / or gold only grows on metallic surfaces, the layer that prevents corrosion is automatically formed only on surfaces of the pressure contact and does not have to be structured. Alternatively, a layer which contains, for example, TaN, WTi, TiN, TaSi or Ta is deposited or sputtered on and then structured by a photolithographic process in such a way that it only covers the exposed areas of the pressure contact.
Ein weiterer zusätzlicher erfindungsgemäßer Druckkontakt kann auch auf einer Rückseite des Substrats angebracht werden.Another additional pressure contact according to the invention can also be attached to a back of the substrate.
Über dem Druckkontakt kann, wie im Stand der Technik bekannt, eine Folie, die im wesentlichen Molybdän enthält, aufgebracht werden, über die ein Kupferblock angeordnet wird. Die Schaltungsanordnung kann anschließend in ein Keramikgehäuse einge- baut werden, wodurch der Kupferblock und die Folie auf den Druckkontakt gedrückt wird und dabei ein elektrischer und thermischer Kontakt erzeugt wird.As is known in the prior art, a film, which essentially contains molybdenum, can be applied over the pressure contact, over which a copper block is arranged. The circuit arrangement can then be encased in a ceramic housing. be built, whereby the copper block and the foil is pressed onto the pressure contact and thereby an electrical and thermal contact is produced.
Die Schaltungsanordnung ist beispielsweise ein MOSFET, ein IGBT, eine Diode, ein GTO, ein Hochvoltthyristor oder ein anderes Leistungshalbleiter-Bauelement oder Hochvoltdiode.The circuit arrangement is, for example, a MOSFET, an IGBT, a diode, a GTO, a high-voltage thyristor or another power semiconductor component or high-voltage diode.
Die Schaltungsanordnung weist insbesondere wenig Anschlüsse auf und ist für einen Betrieb mit hohen Spannungen und/oder hohen Strömen geeignet.The circuit arrangement has in particular few connections and is suitable for operation with high voltages and / or high currents.
Im folgenden wird ein Ausführungsbeispiel der Erfindung, das in den Figuren dargestellt ist, näher erläutert.In the following an embodiment of the invention, which is shown in the figures, is explained in more detail.
Figur 1 zeigt einen Querschnitt durch ein Substrat, nachdem ein IGBT mit einer Metallisierungsebene und eine Passivierungsschicht erzeugt wurde.FIG. 1 shows a cross section through a substrate after an IGBT with a metallization level and a passivation layer has been produced.
Figur 2 zeigt den Querschnitt aus Figur 1, nachdem eineFigure 2 shows the cross section of Figure 1 after a
Schicht, die als Diffusionsbarriere wirkt, eine leitende Schicht, eine Maske und ein Druckkontakt erzeugt wurden. Darüber hinaus sind ein Elektrolyt und eine Elektrode schematisch dargestelltLayer that acts as a diffusion barrier, a conductive layer, a mask and a pressure contact were created. In addition, an electrolyte and an electrode are shown schematically
Figur 3 zeigt den Querschnitt aus Figur 2, nachdem die Maske entfernt wurde, die Schicht, die als Diffusionsbarriere wirkt und die leitende Schicht strukturiert wurden und eine Schicht, die Korrosion verhindert, erzeugt wurde.FIG. 3 shows the cross section from FIG. 2 after the mask has been removed, the layer which acts as a diffusion barrier and the conductive layer has been structured and a layer which prevents corrosion has been produced.
Figur 4 zeigt einen vergrößerten Ausschnitt aus Figur 3.FIG. 4 shows an enlarged section from FIG. 3.
Figur 5 zeigt einen Querschnitt durch das Substrat, nachdem Folien und Kupferblöcke aufgebracht wurden, und das Substrat in ein Keramikgehäuse gepackt wurde. Die Figuren sind nicht maßstabsgetreu.FIG. 5 shows a cross section through the substrate after foils and copper blocks have been applied and the substrate has been packed in a ceramic housing. The figures are not to scale.
In einem Ausführungsbeispiel umfaßt eine Schaltungsanordnung einen IGBT, der in einem Substrat 1 angeordnet ist. Source- Gebiete G (sogenannte DMOS-Zellen) sind mit einer aus dem Substrat 1 angeordneten Metallisierungsebene M verbunden (s. Figur 1) .In one exemplary embodiment, a circuit arrangement comprises an IGBT which is arranged in a substrate 1. Source regions G (so-called DMOS cells) are connected to a metallization level M arranged from the substrate 1 (see FIG. 1).
Zum Schutz der Schaltungsanordnung wird eine ca. 4μm dickeTo protect the circuit arrangement, an approx. 4μm thick
Passivierungsschicht S, die Oxid, Nitrid und Polymid enthält, aufgebracht und photolithographisch so strukturiert, daß ein zu kontaktierender Bereich der Schaltungsanordnung, d.h. ein Teil der Metallisierungsebene M, freigelegt wird (s. Figur 1) .Passivation layer S, which contains oxide, nitride and polymide, applied and structured photolithographically in such a way that a region of the circuit arrangement to be contacted, i.e. part of the metallization level M is exposed (see FIG. 1).
Anschließend wird eine ca. 50 nm dicke Schicht B, die als Diffusionsbarriere dient, ganzflächig abgeschieden (s. Figur 2) .Then an approximately 50 nm thick layer B, which serves as a diffusion barrier, is deposited over the entire surface (see FIG. 2).
Darüber wird durch Sputtern eine ca. 50 nm dicke leitende Schicht L ganzflächig abgeschieden (s. Figur 2).An approximately 50 nm thick conductive layer L is deposited over the entire surface by sputtering (see FIG. 2).
Anschließend wird eine ca. 10 um dicke Maske P aus Photolack erzeugt, die mindestens einen Teil des durch die Schicht B, die als Diffusionsbarriere dient, und die leitende Schicht L bedeckten Teils der Metallisierungsebene M nicht bedeckt.An approximately 10 μm thick mask P is then produced from photoresist and does not cover at least a part of the part of the metallization level M covered by the layer B, which serves as a diffusion barrier, and the conductive layer L.
Die leitende Schicht L wird mit einem ersten Spannungsan- schluß verbunden. Die Schaltungsanordnung wird in einen Elektrolyten Y getaucht, der im wesentlichen CUSO4, H2SO , CL~ und Additive enthält und über eine Elektrode E mit einem zweiten Spannungsanschluß verbunden wird. Zwischen der Elektrode E und der leitenden Schicht L wird ein Strom von ca. 2 A/dm2 eingeprägt. Mit einer Aufwachsrate von ca. 1 μm/min wird Kupfer auf die leitende Schicht L, die als Kristallisationsschicht (Seedlayer) dient, und zwischen Flanken der Mas- ke P aufgebracht. Nach ca. 9 Minuten wird der galvanische Prozeß beendet. Es entsteht ein ca. 9 μm dicker Druckkontakt D aus Kupfer, der eine im wesentlichen ebene obere Fläche besitzt, die unterhalb einer oberen Fläche der Maske P liegt (s. Figur 2) .The conductive layer L is connected to a first voltage connection. The circuit arrangement is immersed in an electrolyte Y, which essentially contains CUSO4, H2SO, CL ~ and additives and is connected via an electrode E to a second voltage connection. A current of approximately 2 A / dm2 is impressed between the electrode E and the conductive layer L. With a growth rate of approx. 1 μm / min, copper is applied to the conductive layer L, which serves as a crystallization layer (seed layer), and between flanks of the mass ke P applied. The galvanic process is ended after approx. 9 minutes. An approximately 9 μm thick pressure contact D made of copper is produced, which has an essentially flat upper surface which lies below an upper surface of the mask P (see FIG. 2).
Anschließend wird die Maske P entfernt. Der Druckkontakt D weist im wesentlichen senkrechte Flanken auf und ragt über die Passivierungsschicht S hinaus (s. Figur 3).Mask P is then removed. The pressure contact D has essentially vertical flanks and extends beyond the passivation layer S (see FIG. 3).
Mit Hilfe von H2O2, HC1 und fluorhaltigen Gasen als Ätzmittel werden freiliegende Teile der leitenden Schicht L und der Schicht B, die als Diffusionsbarriere dient, entfernt (s. Figur 3) .With the help of H2O2, HC1 and fluorine-containing gases as an etchant, exposed parts of the conductive layer L and the layer B, which serves as a diffusion barrier, are removed (see FIG. 3).
Durch einen stromlosen galvanischen Prozeß wächst Palladium in einer Dicke von ca. 500nm auf freiliegende Flächen des Druckkontakt auf. Anschließend wird durch einen weiteren stromlosen galvanischen Prozeß Gold in einer Dicke von ca. 50nrα auf das Palladium aufgewachsen. Es entsteht an den Flächen des Druckkontaktes D eine ca. 550nm dicke Schicht K, die die Korrosion verhindert und Palladium und Gold enthält (s. Figur 3) .Through an electroless galvanic process, palladium grows to a thickness of approx. 500nm on exposed surfaces of the pressure contact. Gold is then grown on the palladium by a further currentless galvanic process in a thickness of approximately 50 nm. An approximately 550 nm thick layer K is formed on the surfaces of the pressure contact D, which prevents corrosion and contains palladium and gold (see FIG. 3).
Figur 4 zeigt einen vergrößerten Ausschnitt aus Figur 3, aus dem deutlich wird, daß die Metallisierungsebene M im Bereich der Source-Gebiete G Vertiefungen aufweist. Eine vertikale Abmessung v der Vertiefungen ist ca. 3 mal so groß wie eine horizontale Abmessung h der Vertiefungen.FIG. 4 shows an enlarged section from FIG. 3, from which it becomes clear that the metallization plane M has depressions in the region of the source regions G. A vertical dimension v of the depressions is approximately 3 times as large as a horizontal dimension h of the depressions.
Über dem Druckkontakt D und über eine der Metallisierungsebene M abgewandten Seite des Substrats 1 wird jeweils eine Folie F, die im wesentlichen Molybdän enthält, aufgebracht. Über den Folien F aus Molybdän wird jeweils ein Kupferblock C angeordnet. Die Schaltungsanordnung wird in ein Keramikgehäuse H gepackt. Es sind viele Variationen des Ausführungsbeispiels denkbar, die ebenfalls im Rahmen der Erfindung liegen. So können Abmessungen der Schichten an die jeweiligen Erfordernisse angepaßt werden. Eine Dicke der Maske P ist dabei immer so groß, daß die obere Fläche des Druckkontaktes D unterhalb der oberen Fläche der Maske P liegt.A film F, which essentially contains molybdenum, is applied over the pressure contact D and over one side of the substrate 1 facing away from the metallization plane M. A copper block C is arranged above the foils M made of molybdenum. The circuit arrangement is packed in a ceramic housing H. Many variations of the exemplary embodiment are conceivable, which are also within the scope of the invention. So dimensions of the layers can be adapted to the respective requirements. The thickness of the mask P is always so great that the upper surface of the pressure contact D lies below the upper surface of the mask P.
Die Maske P kann auch auf Teilen der Schicht B, die als Diffusionsbarriere dient, angeordnet sein, die ursprünglich Tei- le der Metallisierungsebene M bedecken.The mask P can also be arranged on parts of the layer B, which serves as a diffusion barrier, which originally cover parts of the metallization level M.
Als Schicht K, die die Korrosion verhindert, können auch z. B. TaN, WTi, TaSi, Ta oder TiN als Material verwendet werden. In diesem Fall wird die Schicht K ganzflächig aufgebracht. Für den Fall, daß die Schicht K, die die Korrosion verhindert, elektrisch leitet, wird sie anschließend strukturiert, so daß sie im wesentlichen nur Flächen des Druckkontaktes D bedeckt.As layer K, which prevents corrosion, z. B. TaN, WTi, TaSi, Ta or TiN can be used as the material. In this case, the layer K is applied over the entire surface. In the event that the layer K, which prevents corrosion, is electrically conductive, it is then structured so that it essentially covers only areas of the pressure contact D.
Die Schaltungsanordnung kann statt ein IGBT auch ein MOSFET, eine Diode, ein GTO, ein Hochvoltthyristor oder ein anderes Leistungshalbleiter-Bauelement sein. Instead of an IGBT, the circuit arrangement can also be a MOSFET, a diode, a GTO, a high-voltage thyristor or another power semiconductor component.

Claims

Patentansprüche claims
1 . Schaltungsanordnung,1 . Circuit arrangement,
- bei der ein Druckkontakt (D) über einem leitenden Gebiet der Schaltungsanordnung angeordnet ist und das leitende Gebiet kontaktiert,a pressure contact (D) is arranged above a conductive region of the circuit arrangement and contacts the conductive region,
- bei der der Druckkontakt (D) Metall enthält,- where the pressure contact (D) contains metal,
- bei der eine obere Fläche des Druckkontakts (D) im wesentlichen eben ist, - bei der die obere Fläche des Druckkontakts (D) oberhalb einer Passivierungsschicht (S) der Schaltungsanordnung liegt.- in which an upper surface of the pressure contact (D) is substantially flat, - in which the upper surface of the pressure contact (D) lies above a passivation layer (S) of the circuit arrangement.
2. Schaltungsanordnung nach Anspruch 1,2. Circuit arrangement according to claim 1,
- bei der der Druckkontakt (D) im wesentlichen senkrechte Flanken aufweist.- In which the pressure contact (D) has essentially vertical flanks.
3. Schaltungsanordnung nach einem der Ansprüche 1 oder 2,3. Circuit arrangement according to one of claims 1 or 2,
- bei der mindestens ein Teil des Druckkontakts (D) eine Vertiefung füllt, - bei der das Verhältnis einer vertikalen Abmessung (v) der Vertiefung zu einer horizontalen Abmessung (h) der Vertiefung größer als 4:1 beträgt, wobei die horizontale Abmessung (h) zwischen 0.5μm und 8μm beträgt.- in which at least part of the pressure contact (D) fills a depression, - in which the ratio of a vertical dimension (v) of the depression to a horizontal dimension (h) of the depression is greater than 4: 1, the horizontal dimension (h ) is between 0.5μm and 8μm.
4. Schaltungsanordnung nach einem der Ansprüche 1 bis 3,4. Circuit arrangement according to one of claims 1 to 3,
- bei der das leitende Gebiet eine Metallisierungsebene (M) oder Teil eines Substrats (1), in dem die Schaltungsanordnung angeordnet ist, ist.- In which the conductive region is a metallization level (M) or part of a substrate (1) in which the circuit arrangement is arranged.
5. Schaltungsanordnung nach einem der Ansprüche 1 bis 4,5. Circuit arrangement according to one of claims 1 to 4,
- bei der das Metall Kupfer ist.- where the metal is copper.
6. Schaltungsanordnung nach einem der Ansprüche 1 bis 5,6. Circuit arrangement according to one of claims 1 to 5,
- bei der der Druckkontakt (D) ein Leistungshalbleiterbauele- ment kontaktiert.- in which the pressure contact (D) contacts a power semiconductor component.
7. Verfahren zur Herstellung einer Schaltungsanordnung, - bei dem über einem leitenden Gebiet der Schaltungsanordnung eine Maske (P) aufgebracht wird, die einen zu kontaktierenden Bereich des leitenden Gebiets nicht bedeckt,7. Method for producing a circuit arrangement, a mask (P) is applied over a conductive region of the circuit arrangement and does not cover a region of the conductive region to be contacted,
- bei dem Metall durch einen galvanischen Prozeß mit Strom abgeschieden wird, wodurch der Druckkontakt (D) erzeugt wird,- the metal is deposited with current by means of a galvanic process, whereby the pressure contact (D) is generated,
- bei dem das Abscheiden beendet wird, solange eine obere Fläche des Druckkontakts (D) unterhalb einer oberen Fläche der Maske (P) liegt.- in which the deposition is ended as long as an upper surface of the pressure contact (D) lies below an upper surface of the mask (P).
8. Verfahren nach Anspruch 7,8. The method according to claim 7,
- bei dem das Metall Kupfer ist.- where the metal is copper.
9. Verfahren nach Anspruch 7 oder 8, - bei dem auf das leitende Gebiet eine leitende Schicht (L) aufgebracht wird, über die die Maske (P) erzeugt wird,9. The method according to claim 7 or 8, - in which a conductive layer (L) is applied to the conductive region, via which the mask (P) is produced,
- bei dem auf die Schaltungsanordnung ein Elektrolyt für den galvanischen Prozeß aufgebracht wird,in which an electrolyte for the galvanic process is applied to the circuit arrangement,
- bei dem zur Abscheidung des Metalls eine Spannung zwischen der leitenden Schicht (L) und einer Elektrode (E) im Elektrolyt (Y) angelegt wird,in which a voltage is applied between the conductive layer (L) and an electrode (E) in the electrolyte (Y) to deposit the metal,
- bei dem die Maske (P) nach Erzeugung des Druckkontakts (D) entfernt wird,in which the mask (P) is removed after generation of the pressure contact (D),
- bei dem außerhalb des Druckkontakts (D) angeordnete Teile der leitenden Schicht (L) entfernt werden.- At the outside of the pressure contact (D) arranged parts of the conductive layer (L) are removed.
10. Verfahren nach Anspruch 9,10. The method according to claim 9,
- bei dem vor Erzeugung der leitenden Schicht (L) eine Schicht (B) , die als Diffusionsbarriere wirkt, aufgebracht wird,a layer (B), which acts as a diffusion barrier, is applied before the conductive layer (L) is produced,
- bei dem die leitende Schicht (L) im wesentlichen aus Kupfer erzeugt wird,in which the conductive layer (L) is produced essentially from copper,
- bei dem die Schicht (B) , die als Diffusionsbarriere wirkt, wie die leitende Schicht (L) strukturiert wird.- In which the layer (B), which acts as a diffusion barrier, is structured like the conductive layer (L).
11. Verfahren nach einem der Ansprüche 7 bis 10, - bei dem über dem Druckkontakt (D) eine Schicht (K) , die Korrosion verhindert und im wesentlichen Palladium und/oder Gold enthält, durch einen stromlosen galvanischen Prozeß aufgebracht wird.11. The method according to any one of claims 7 to 10, - In which a layer (K), which prevents corrosion and essentially contains palladium and / or gold, is applied over the pressure contact (D) by an electroless galvanic process.
12. Verfahren nach einem der Ansprüche 7 bis 10,12. The method according to any one of claims 7 to 10,
- bei dem nach Erzeugung des Druckkontakts (D) eine Schicht, die Korrosion (K) verhindert, aufgebracht wird und so strukturiert wird, daß sie im wesentlichen nur den Druck- kontakt (D) bedeckt.- In which, after the pressure contact (D) has been produced, a layer which prevents corrosion (K) is applied and is structured in such a way that it essentially only covers the pressure contact (D).
13. Verfahren nach einem der Ansprüche 7 bis 12,13. The method according to any one of claims 7 to 12,
- bei dem das leitende Gebiet eine Metallisierungsebene (M) oder Teil des Substrats (1) ist. - In which the conductive region is a metallization level (M) or part of the substrate (1).
EP99945844A 1998-07-08 1999-07-01 Circuit and a method for the production thereof Ceased EP1095404A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19830537 1998-07-08
DE19830537 1998-07-08
PCT/DE1999/001973 WO2000003437A1 (en) 1998-07-08 1999-07-01 Circuit and a method for the production thereof

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DE102006049354B3 (en) * 2006-10-19 2008-06-05 Infineon Technologies Ag Method for producing a connection contact on a semiconductor body
DE102007036566A1 (en) * 2007-08-03 2009-02-19 Siemens Ag Spring contact of electrical contact surfaces of an electronic component
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