EP0971279A1 - Calibrating method of a resistor in an integrated circuit and apparatus for executing this method - Google Patents

Calibrating method of a resistor in an integrated circuit and apparatus for executing this method Download PDF

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EP0971279A1
EP0971279A1 EP99113054A EP99113054A EP0971279A1 EP 0971279 A1 EP0971279 A1 EP 0971279A1 EP 99113054 A EP99113054 A EP 99113054A EP 99113054 A EP99113054 A EP 99113054A EP 0971279 A1 EP0971279 A1 EP 0971279A1
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Prior art keywords
resistor
switch
integrated circuit
voltage
value
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German (de)
French (fr)
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EP0971279B1 (en
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Ekkehart-Peter Wagner
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the invention relates to a method for adjusting a resistance in an integrated circuit according to the generic term of claim 1.
  • the invention also relates to a device to carry out this procedure.
  • Resistors in integrated circuits usually have a tolerance range of up to ⁇ 30% of their nominal value. More precise resistance values So far, only in complex adjustment procedures using laser incisions be reached in the resistance area. The disadvantage of this method is that such resistors are temperature-dependent due to the material.
  • DE 19520735 A1 describes a circuit arrangement for detection the load current of a power semiconductor component is known, which is a series connection of a measuring resistor connected to ground and a controllable resistor that is set so that the measuring current is proportional to the load current becomes.
  • DE 4101492 A1 describes a circuit arrangement for detection of flowing through a consumer and an output stage Load current known, in which in one with the load circuit connected circuit branch by means of a controllable Resistance whose current is controlled so that this on a resistor a voltage proportional to the load current generated.
  • the present invention is therefore based on the object specify a method that is capable of providing resistance in an integrated circuit to much tighter Adjust tolerance values and its temperature dependency to eliminate.
  • the object of the invention is also a To provide an apparatus for performing this method.
  • the inventive method has the advantage that for comparison of resistance only one at the resistance to be adjusted falling actual voltage by means of an external control circuit a predetermined target voltage is to be adjusted.
  • Another advantage of the method according to the invention is that in this way balanced resistors independent of temperature are because the adjustment process shortly before using the Resistance takes place at the respective temperature. With the method according to the invention has tolerance values around the Target value of up to approx. ⁇ 4% can be achieved.
  • Figure 1 shows an integrated in a not shown Circuit IS arranged field effect transistor M1, the Drain-source path as a controllable resistor in series with a resistor R1 is also integrated.
  • the source connection of the field effect transistor M1 is in this Embodiment with the ground connection GND of the circuit IS connected.
  • a capacitor C1 is arranged between the gate terminal G of the field effect transistor M1 and the ground terminal GND.
  • the gate connection G is connected via a (on-off) switch S2 and a first changeover switch S1 in series with it, either via a charging resistor R3 to a voltage source V1 or via a discharging resistor R2 to the ground connection GND.
  • the charging and discharging of the capacitor C1 can, however, also take place in another way, for example via charging and discharging current sources.
  • the first changeover switch S1 is controlled by the output signal V OP of an operational amplifier OP connected as a comparator, the inverting input "-" of which is a predetermined reference voltage V ref , as explained below.
  • the resistor RM (in this exemplary embodiment, therefore, R1, which, however, can also lie between the source connection and ground reference potential GND) is connected to the non-inverting input "+" of the operational amplifier OP and via a second switch S3 in the position shown with a reference current source I ref , and in the other position with the integrated circuit IS, not shown, in which the trimmed resistor RM is to be used.
  • the first changeover switch S1 is brought into the position shown, whereby the capacitor C1 is charged by the voltage source V1 via the charging resistor R3. This reduces the resistance of the drain-source path of the field effect transistor M1 and thus the voltage V RM .
  • the first changeover switch S1 is brought into the other position by the output signal V OP of the operational amplifier OP, as a result of which the capacitor C1 is discharged via the discharge resistor R2.
  • the resistance across the drain-source path of the field effect transistor M1 increases again.
  • the actual value of the voltage V RM then oscillates around the predetermined setpoint of the reference voltage V ref .
  • the components OP, V1, C1, S1, R2 and R3 therefore represent a two-point controller.
  • the resistance RM has reached its target value of approximately RM ⁇ 4%.
  • Tightly tolerated resistance values can be done in the same way can also be generated without an integrated resistor R1 by only the drain-source path of the field effect transistor M1 serves as a resistance value RM.
  • the control circuit including the reference current source I ref is switched off, ie switch S2 is opened (by a command from the integrated circuit IS or from outside) and the second switch is switched to its other position.
  • the resistor RM is connected to the integrated circuit IS and the gate voltage V G for a certain period, which depends on the quality of the capacitor C1, frozen ".
  • the resistance RM remains constant for a certain time and can be refreshed by repeated trimming processes.
  • the inventive method enables in a simple way, integrated resistors dynamically in the Match operation. Expensive and time-consuming test steps for subsequent laser trimming of the resistor omitted. In addition, the temperature response of the integrated Resistance dynamically compared.
  • FIG. 2 shows the course of the gate voltage over time during the adjustment process and thereafter and FIG. 3 shows the size of the resistance RM as a quotient V RM / I M over time, likewise during the adjustment process and afterwards.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

Dem einen steuerbaren Widerstand M1 (FET )enthaltenden abzugleichenden Widerstand RM wird ein Konstantstrom IM eingeprägt, dann der Istwert der durch den Konstantstrom IM am abzugleichenden Widerstand RM verursachten Spannung VRM mit einer als Sollwert vorgegebenen Referenzspannung Vref verglichen und der steuerbare Widerstand M1 solange verändert, bis der Istwert der am Widerstand RM abfallenden Spannung VRM mit dem Sollwert der Referenzspannung Vref übereinstimmt. <IMAGE>A constant current IM is impressed on the resistor RM to be trimmed, which contains a controllable resistor M1 (FET), then the actual value of the voltage VRM caused by the constant current IM at the resistor RM to be trimmed is compared with a reference voltage Vref specified as a setpoint value, and the controllable resistor M1 is changed until the actual value of the voltage VRM dropping across the resistor RM corresponds to the nominal value of the reference voltage Vref. <IMAGE>

Description

Verfahren zum Abgleichen eines Widerstandes in einer integrierten Schaltung und Vorrichtung zur Durchführung dieses Verfahrens.Method of matching a resistor in an integrated one Circuit and device for performing this Procedure.

Die Erfindung betrifft ein Verfahren zum Abgleichen eines Widerstandes in einer integrierten Schaltung nach dem Oberbegriff des Anspruchs 1. Die Erfindung betrifft auch eine Vorrichtung zur Durchführung dieses Verfahrens.The invention relates to a method for adjusting a resistance in an integrated circuit according to the generic term of claim 1. The invention also relates to a device to carry out this procedure.

Widerstände in integrierten Schaltungen, insbesondere in MOS-Technologie, weisen in der Regel einen Toleranzbereich von bis zu ±30% ihres Nennwertes auf. Genauere Widerstandswerte konnten bisher nur in aufwendigen Abgleichverfahren durch Lasereinschnitte in die Widerstandsfläche erreicht werden. Nachteilig an diesen Verfahren ist, daß solche Widerstände materialbedingt temperaturabhängig sind.Resistors in integrated circuits, especially in MOS technology, usually have a tolerance range of up to ± 30% of their nominal value. More precise resistance values So far, only in complex adjustment procedures using laser incisions be reached in the resistance area. The disadvantage of this method is that such resistors are temperature-dependent due to the material.

Aus DE 19520735 A1 ist eine Schaltungsanordnung zum Erfassen des Laststroms eines Leistungs-Halbleiterbauelements bekannt, welche eine Reihenschaltung eines an Masse liegenden Meßwiderstandes und eines steuerbaren Widerstandes aufweist, der so eingestellt wird, daß der Meßstrom dem Laststrom proportional wird.DE 19520735 A1 describes a circuit arrangement for detection the load current of a power semiconductor component is known, which is a series connection of a measuring resistor connected to ground and a controllable resistor that is set so that the measuring current is proportional to the load current becomes.

Aus DE 4101492 A1 ist eine Schaltungsanordnung zum Erfassen des durch einen Verbraucher und eine Endstufe fließenden Laststroms bekannt, bei welcher in einem mit dem Laststromkreis verbundenen Schaltungszweig mittels eines steuerbaren Widerstandes dessen Strom so gesteuert wird, daß dieser an einem Widerstand eine zum Laststrom proportionale Spannung erzeugt. DE 4101492 A1 describes a circuit arrangement for detection of flowing through a consumer and an output stage Load current known, in which in one with the load circuit connected circuit branch by means of a controllable Resistance whose current is controlled so that this on a resistor a voltage proportional to the load current generated.

Der vorliegenden Erfindung liegt daher die Aufgabe zugrunde, ein Verfahren anzugeben, welches in der Lage ist, einen Widerstand in einer integrierten Schaltung auf wesentlich engere Toleranzwerte abzugleichen und dessen Temperaturabhängigkeit zu eliminieren. Aufgabe der Erfindung ist es auch, eine Vorrichtung zur Durchführung dieses Verfahrens zu schaffen.The present invention is therefore based on the object specify a method that is capable of providing resistance in an integrated circuit to much tighter Adjust tolerance values and its temperature dependency to eliminate. The object of the invention is also a To provide an apparatus for performing this method.

Diese Aufgabe wird bezüglich des Verfahrens durch die Merkmale des Anspruchs 1 und bezüglich der Vorrichtung durch die Merkmale des Anspruchs 3 gelöst. Weitere vorteilhafte Ausgestaltungen der Erfindung sind den Unteransprüchen zu entnehmen.This task is related to the method by the features of claim 1 and with respect to the device by the Features of claim 3 solved. Further advantageous configurations the invention can be found in the subclaims.

Das erfindungsgemäße Verfahren hat den Vorteil, daß zum Abgleich des Widerstandes lediglich eine am abzugleichenden Widerstand abfallende Istspannung mittels einer externen Regelschaltung einer vorgegebenen Sollspannung anzugleichen ist. Ein weiteren Vorteil des erfindungsgemäßen Verfahrens ist, daß auf diese Weise abgeglichene Widerstände temperaturunabhängig sind, weil der Abgleichvorgang kurz vor Verwendung des Widerstandes bei der jeweiligen Temperatur stattfindet. Mit dem erfindungsgemäßen Verfahren sind Toleranzwerte um den Sollwert von bis zu ca. ±4% erzielbar.The inventive method has the advantage that for comparison of resistance only one at the resistance to be adjusted falling actual voltage by means of an external control circuit a predetermined target voltage is to be adjusted. Another advantage of the method according to the invention is that in this way balanced resistors independent of temperature are because the adjustment process shortly before using the Resistance takes place at the respective temperature. With the method according to the invention has tolerance values around the Target value of up to approx. ± 4% can be achieved.

Ein schematisches Ausführungsbeispiel einer erfindunggemäßen Vorrichtung zur Durchführung des Verfahrens ist in der Zeichnung dargestellt. Es zeigen:

  • Figur 1 ein Schaltbild einer erfindungsgemäßen Vorrichtung,
  • Figur 2 den Verlauf der Gate-Spannung Ug über der Zeit, und
  • Figur 3 den Verlauf des Widerstandwertes RM über der Zeit.
    • A schematic embodiment of an inventive device for performing the method is shown in the drawing. Show it:
  • FIG. 1 shows a circuit diagram of a device according to the invention,
  • 2 shows the course of the gate voltage Ug over time, and
  • Figure 3 shows the course of the resistance value RM over time.

    • Figur 1 zeigt einen in einer nicht dargestellten integrierten Schaltung IS angeordneten Feldeffekttransistor M1, dessen Drain-Source-Strecke als steuerbarer Widerstand in Reihe mit einem ebenfalls integrierten Widerstand R1 angeordnet ist. Der Source-Anschluß des Feldeffekttransistors M1 ist in diesem Ausführungsbeispiel mit dem Masseanschluß GND der Schaltung IS verbunden. Die Reihenschaltung aus Drain-Source-Strecke des Feldeffekttransistors M1 und Widerstand R1 stellt in diesem Ausführungsbeispiel den abzugleichenden, d.h., möglichst genau auf einen vorgegebenen Wert einzustellenden Widerstand RM dar.Figure 1 shows an integrated in a not shown Circuit IS arranged field effect transistor M1, the Drain-source path as a controllable resistor in series with a resistor R1 is also integrated. The source connection of the field effect transistor M1 is in this Embodiment with the ground connection GND of the circuit IS connected. The series connection from drain-source path of the field effect transistor M1 and resistor R1 in this embodiment, the one to be compared, i.e., if possible resistance to be set precisely to a predetermined value RM represents.

    Zwischen dem Gateanschluß G des Feldeffekttransistors M1 und dem Masseanschluß GND ist ein Kondensator C1 angeordnet. Der Gateanschluß G ist über einen (Ein-AUS-)Schalter S2 und einen mit ihm in Reihe liegenden ersten Umschalter S1 entweder über einen Ladewiderstand R3 mit einer Spannungsquelle V1 oder über einen Entladewiderstand R2 mit dem Masseanschluß GND verbunden. (Das Laden und Entladen des Kondensators C1 kann jedoch auch auf andere Weise erfolgen, beispielsweise über aufladende und entladende Stromquellen.) Der erste Umschalter S1 wird vom Ausgangssignal VOP eines als Komparator geschalteten Operationsverstärkers OP angesteuert, dessen invertierendem Eingang "-" eine vorgegebene Referenzspannung Vref, wie nachstehend erläutert, zugeführt wird.A capacitor C1 is arranged between the gate terminal G of the field effect transistor M1 and the ground terminal GND. The gate connection G is connected via a (on-off) switch S2 and a first changeover switch S1 in series with it, either via a charging resistor R3 to a voltage source V1 or via a discharging resistor R2 to the ground connection GND. (The charging and discharging of the capacitor C1 can, however, also take place in another way, for example via charging and discharging current sources.) The first changeover switch S1 is controlled by the output signal V OP of an operational amplifier OP connected as a comparator, the inverting input "-" of which is a predetermined reference voltage V ref , as explained below.

    Der Widerstand RM (in diesem Ausführungsbeispiel also R1, der jedoch auch zwischen Sourceanschluß und Massebezugspotential GND liegen kann) ist mit dem nichtinvertierenden Eingang "+" des Operationsverstärkers OP sowie über einen zweiten Umschalter S3 in der gezeichneten Stellung mit einer Referenzstromquelle Iref, und in der anderen Stellung mit der nicht dargestellten integrierten Schaltung IS, in welcher der abgeglichene Widerstand RM verwendet werden soll, verbunden.. The resistor RM (in this exemplary embodiment, therefore, R1, which, however, can also lie between the source connection and ground reference potential GND) is connected to the non-inverting input "+" of the operational amplifier OP and via a second switch S3 in the position shown with a reference current source I ref , and in the other position with the integrated circuit IS, not shown, in which the trimmed resistor RM is to be used.

    Von der Referenzstromquelle Iref fließt ein Konstantstrom IM, beispielsweise 300µA, durch RM = R1 + M1 nach GND. Wenn der Widerstand RM einen Wert von beispielsweise 10kΩ aufweisen soll, so muß an ihn bei einem Strom IM = 300µA eine Spannung VRM = RM * IM = 10kΩ * 300µA = 3V abfallen. Dazu wird der Istwert der Spannung VRM im Komparator (Operationsverstärker OP) mit einer vorgegebenen Referenzspannung (als Sollwert) Vref = 3V verglichen. In der gezeichneten Abgleich-Stellung der Schalter S2 und S3, die von außen synchron gesteuert werden, sei angenommen, daß der Widerstand RN (hier R1 + M1) zu groß und dementsprechend auch die Spannung VRM größer als die Referenzspannung Vref ist. Da der Widerstand R1 sich nur mit der Temperatur ändern kann, muß der Widerstand der Drain-Source-Strecke des Feldeffekttransistors M1 verkleinert werden, wozu seine Gatespannung VG vergrößert werden muß.A constant current I M , for example 300 μA, flows through from the reference current source I ref RM = R1 + M1 according to GND . If the resistance RM is to have a value of, for example, 10 kΩ, then a voltage must be applied to it at a current I M = 300 μA V RM = RM * I M = 10kΩ * 300µA = 3V fall off. For this purpose, the actual value of the voltage V RM in the comparator (operational amplifier OP) is compared with a predetermined reference voltage (as setpoint) V ref = 3V. In the drawn adjustment position of the switches S2 and S3, which are controlled synchronously from the outside, it is assumed that the resistance RN (here R1 + M1) is too large and, accordingly, the voltage V RM is greater than the reference voltage V ref . Since the resistance R1 can only change with the temperature, the resistance of the drain-source path of the field effect transistor M1 must be reduced, for which purpose its gate voltage V G must be increased.

    Dies geschieht dadurch, daß, vom Ausgangssignal VOP des Operationsverstärkers OP gesteuert, der erste Umschalter S1 in die gezeichnete Stellung gebracht wird, wodurch der Kondensator C1 von der Spannungsquelle V1 über den Ladewiderstand R3 aufgeladen wird. Dadurch wird der Widerstand der Drain-Source-Strecke des Feldeffekttransistors M1 und damit die Spannung VRM verkleinert.This is done in that, controlled by the output signal V OP of the operational amplifier OP, the first changeover switch S1 is brought into the position shown, whereby the capacitor C1 is charged by the voltage source V1 via the charging resistor R3. This reduces the resistance of the drain-source path of the field effect transistor M1 and thus the voltage V RM .

    Wird anschließend der Istwert der Spannung VRM kleiner als der Sollwert der Referenzspannung Vref, so wird der erste Umschalter S1 vom Ausgangssignal VOP des Operationsverstärkers OP in die andere Stellung gebracht, wodurch der Kondensator C1 über den Entladewiderstand R2 entladen wird. Dadurch wird der Widerstand über der Drain-Source-Strecke des Feldeffekttransistors M1 und mit ihn der Istwert der Spannung VRM wieder größer. If the actual value of the voltage V RM subsequently becomes smaller than the target value of the reference voltage V ref , the first changeover switch S1 is brought into the other position by the output signal V OP of the operational amplifier OP, as a result of which the capacitor C1 is discharged via the discharge resistor R2. As a result, the resistance across the drain-source path of the field effect transistor M1, and with it the actual value of the voltage V RM , increases again.

    Der Istwert der Spannung VRM pendelt dann um den vorgegebenen Sollwert der Referenzspannung Vref. Die Bauelemente OP, V1, C1, S1, R2 und R3 stellen demnach einen Zweipunktregler dar. Wenn der erste Umschalter S1 zwischen seinen beiden Schaltstellungen hin- und herpendelt, hat der Widerstand RM seinen Sollwert von etwa RM ±4% erreicht.The actual value of the voltage V RM then oscillates around the predetermined setpoint of the reference voltage V ref . The components OP, V1, C1, S1, R2 and R3 therefore represent a two-point controller. When the first changeover switch S1 oscillates back and forth between its two switching positions, the resistance RM has reached its target value of approximately RM ± 4%.

    Eng tolerierte Widerstandswerte können auf die gleiche Weise auch ohne integrierten Widerstand R1 erzeugt werden, indem lediglich die Drain-Source-Strecke des Feldeffekttransistors M1 als Widerstandswert RM dient.Tightly tolerated resistance values can be done in the same way can also be generated without an integrated resistor R1 by only the drain-source path of the field effect transistor M1 serves as a resistance value RM.

    Nach Beendigung des Abgleichvorgangs wird die Regelschaltung samt der Referenzstromquelle Iref abgeschaltet, d.h., es werden (durch einen Befehl der integrierten Schaltung IS oder von außerhalb) der Schalter S2 geöffnet und der zweite Umschalter in seine andere Stellung umgeschaltet. Dadurch wird der Widerstand RM mit der integrierten Schaltung IS verbunden und die Gatespannung VG für eine bestimmte Dauer, die von der Güte des Kondensators C1 abhängt,

    Figure 00050001
    eingefroren". Der Widerstand RM bleibt für eine bestimmte Zeit konstant und kann durch wiederholte Abgleichvorgänge aufgefrischt werden.After the adjustment process has ended, the control circuit including the reference current source I ref is switched off, ie switch S2 is opened (by a command from the integrated circuit IS or from outside) and the second switch is switched to its other position. Thereby, the resistor RM is connected to the integrated circuit IS and the gate voltage V G for a certain period, which depends on the quality of the capacitor C1,
    Figure 00050001
    frozen ". The resistance RM remains constant for a certain time and can be refreshed by repeated trimming processes.

    Insbesondere bei ASIC's, auf denen üblicherweise ohnehin eine Referenzspannungsquelle sowie ein daraus mit Hilfe eines externen Referenzwiderstandes abgeleiteter Referenzstrom bereits vorhanden sind, ermöglicht das erfindungsgemäße Verfahren auf einfache Weise, integrierte Widerstände dynamisch im Betrieb abzugleichen. Teure und zeitaufwendige Testschritte zum nachträglichen Lasertrimmen des Widerstandes können dadurch entfallen. Außerdem wird der Temperaturgang des integrierten Widerstandes dynamisch gleich mitabgeglichen. Especially with ASICs, which usually have one anyway Reference voltage source and one of them with the help of an external Reference resistance derived reference current already are present, the inventive method enables in a simple way, integrated resistors dynamically in the Match operation. Expensive and time-consuming test steps for subsequent laser trimming of the resistor omitted. In addition, the temperature response of the integrated Resistance dynamically compared.

    Figur 2 zeigt den Verlauf der Gate-Spannung über der Zeit während des Abgleichvorgangs und danach und Figur 3 zeigt die Größe des Widerstandes RM als Quotient VRM/IM über der Zeit, ebenfalls während des Abgleichvorgangs und danach.FIG. 2 shows the course of the gate voltage over time during the adjustment process and thereafter and FIG. 3 shows the size of the resistance RM as a quotient V RM / I M over time, likewise during the adjustment process and afterwards.

    Claims (7)

    Verfahren zum Abgleichen eines Widerstandes (RM) in einer integrierten Schaltung (IS), insbesondere in einem ASIC, welcher eine Reihenschaltung eines Widerstandes (R1) und eines steuerbaren Widerstandes (M1) enthält,
    dadurch gekennzeichnet, daß dem abzugleichenden Widerstand (RM) ein Konstantstrom (IM) vorgegebener Stärke eingeprägt wird, daß der Istwert der durch den Konstantstrom (IM) am abzugleichenden Widerstand (RM) verursachten Spannung (VRM) mit einer als Sollwert vorgegebenen Referenzspannung (Vref) verglichen wird, und daß der steuerbare Widerstand (M1) solange verändert wird, bis der Istwert der am Widerstand (RM) abfallenden Spannung (VRM) mit dem Sollwert der Referenzspannung (Vref) übereinstimmt.     Method for matching a resistor (RM) in an integrated circuit (IS), in particular in an ASIC, which contains a series connection of a resistor (R1) and a controllable resistor (M1),
    characterized by that a constant current (I M ) of predetermined strength is impressed on the resistor (RM) to be calibrated, that the actual value of the voltage (V RM ) caused by the constant current (I M ) at the resistor (RM) to be calibrated is compared with a reference voltage (V ref ) given as the desired value, and that the controllable resistor (M1) is changed until the actual value of the voltage (V RM ) dropping across the resistor (RM) matches the target value of the reference voltage (V ref ).     Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß der Wert des Widerstandes (RM) durch wiederholte Abgleichvorgänge aufgefrischt wird.A method according to claim 1, characterized in that the Value of resistance (RM) through repeated trimming processes is refreshed. Vorrichtung zur Durchführung des Verfahrens nach Anspruch 1, bei welcher der abzugleichende Widerstand (RM) auf der einen Seite mit dem Masseanschluß (GND) der integrierten Schaltung verbunden ist,
    dadurch gekennzeichnet, daß der abzugleichende Widerstand (RM) auf der anderen Seite einerseits mit dem nichtinvertierenden Eingang (+) eines als Komparator geschalteten Operationsverstärkers (OP) und andererseits über einen zweiten Umschalter (S3) entweder mit einer Referenzstromquelle (Iref) oder mit der integrierten Schaltung (IS) verbunden ist, daß zwischen dem Steueranschluß (G) des steuerbaren Widerstandes (M1) und dem Masseanschluß (GND) ein Kondensator (C1) angeordnet ist, daß der Steueranschluß (G) über einen Schalter (S2) und einen mit ihm in Reihe liegenden ersten Umschalter (S1) entweder über einen Ladewiderstand (R3) mit einer Spannungsquelle (V1) oder über einen Entladewiderstand (R2) mit dem Masseanschluß(GND) verbunden ist, und daß der erste Umschalter (S1) vom Ausgangssignal (VOP) des Operationsverstärkers (OP) angesteuert wird, dessen invertierendem Eingang (-) eine vorgegebene Referenzspannung (Vref) zugeführt wird.     Device for carrying out the method according to Claim 1, in which the resistor (RM) to be adjusted is connected on one side to the ground connection (GND) of the integrated circuit,
    characterized by that the resistor to be calibrated (RM) on the other hand with the non-inverting input (+) of an operational amplifier (OP) connected as a comparator and on the other hand with a second changeover switch (S3) either with a reference current source (I ref ) or with the integrated circuit ( IS) is connected, that a capacitor (C1) is arranged between the control connection (G) of the controllable resistor (M1) and the ground connection (GND), that the control connection (G) via a switch (S2) and a first changeover switch (S1) in series with it, either via a charging resistor (R3) with a voltage source (V1) or via a discharge resistor (R2) with the ground connection (GND) is connected, and that the first switch (S1) is driven by the output signal (V OP ) of the operational amplifier (OP), the inverting input (-) of which is supplied with a predetermined reference voltage (Vref).     Vorrichtung nach Anspruch 3, dadurch gekennzeichnet, daß der steuerbare Widerstand (M1) ein Feldeffekttransistor ist.Device according to claim 3, characterized in that the controllable resistor (M1) is a field effect transistor. Vorrichtung nach Anspruch 3, dadurch gekennzeichnet, daß nach erfolgten Abgleich der Widerstand (RM) über den zweiten Umschalter (S3) mit der integrierten Schaltung (IS) verbunden wird, und Schalter (S2) geöffnet wird. Device according to claim 3, characterized in that after the adjustment has taken place the resistor (RM) is connected to the integrated circuit (IS) via the second changeover switch (S3), and Switch (S2) is opened. Vorrichtung nach Anspruch 5, dadurch gekennzeichnet, daß die Ansteuerung des Schalters (S2) und des zweiten Umschalters (S3) von der integrierten Schaltung (IS) oder von außerhalb derselben erfolgt.Apparatus according to claim 5, characterized in that the control of the switch (S2) and the second switch (S3) from the integrated circuit (IS) or from outside the same takes place. Vorrichtung nach Anspruch 3, dadurch gekennzeichnet, daß die Spannungsquelle (V1) und der Ladewiderstand (R3) durch eine den Kondensator (C1) ladende Stromquelle und der Entladewiderstand (R2) durch eine den Kondensator (C1) entladende Stromquelle gebildet sind.Device according to claim 3, characterized in that the voltage source (V1) and the charging resistor (R3) a current source charging the capacitor (C1) and the discharge resistor (R2) by a capacitor (C1) discharging Power source are formed.
    EP19990113054 1998-07-07 1999-07-01 Calibrating method of a resistor in an integrated circuit and apparatus for executing this method Expired - Lifetime EP0971279B1 (en)

    Applications Claiming Priority (2)

    Application Number Priority Date Filing Date Title
    DE1998130356 DE19830356C1 (en) 1998-07-07 1998-07-07 Variable resistor balancing and adjuster circuit for AUC circuit
    DE19830356 1998-07-07

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    EP0971279A1 true EP0971279A1 (en) 2000-01-12
    EP0971279B1 EP0971279B1 (en) 2003-09-24

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    Cited By (1)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    US7888952B2 (en) 2007-11-16 2011-02-15 Atmel Automotive Gmbh Circuit arrangement for balancing a resistance circuit

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    EP0499921A2 (en) * 1991-02-18 1992-08-26 STMicroelectronics S.r.l. Current control device particularly for power circuits in mos technology
    US5488328A (en) * 1993-10-20 1996-01-30 Deutsche Aerospace Ag Constant current source

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    DE4101452C2 (en) * 1991-01-16 1994-06-09 Gerd Schulte Multiple slide projector
    DE19520735C2 (en) * 1995-06-07 1999-07-01 Siemens Ag Circuit arrangement for detecting the load current of a power semiconductor component with a load on the source side

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    Publication number Priority date Publication date Assignee Title
    EP0499921A2 (en) * 1991-02-18 1992-08-26 STMicroelectronics S.r.l. Current control device particularly for power circuits in mos technology
    US5488328A (en) * 1993-10-20 1996-01-30 Deutsche Aerospace Ag Constant current source

    Cited By (1)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    US7888952B2 (en) 2007-11-16 2011-02-15 Atmel Automotive Gmbh Circuit arrangement for balancing a resistance circuit

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    DE19830356C1 (en) 1999-11-11
    EP0971279B1 (en) 2003-09-24

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