EP0962869B1 - Zwei-Standard-Schnittstellenschaltung für serielle Verbindung - Google Patents

Zwei-Standard-Schnittstellenschaltung für serielle Verbindung Download PDF

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Publication number
EP0962869B1
EP0962869B1 EP19990401203 EP99401203A EP0962869B1 EP 0962869 B1 EP0962869 B1 EP 0962869B1 EP 19990401203 EP19990401203 EP 19990401203 EP 99401203 A EP99401203 A EP 99401203A EP 0962869 B1 EP0962869 B1 EP 0962869B1
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EP
European Patent Office
Prior art keywords
transceiver
interface circuit
input
output
connector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19990401203
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English (en)
French (fr)
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EP0962869A1 (de
Inventor
Marc Jaffrnnou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB Control SA
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ABB Control SA
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Filing date
Publication date
Application filed by ABB Control SA filed Critical ABB Control SA
Publication of EP0962869A1 publication Critical patent/EP0962869A1/de
Application granted granted Critical
Publication of EP0962869B1 publication Critical patent/EP0962869B1/de
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H03K19/017572—Coupling arrangements; Impedance matching circuits using opto-electronic devices

Definitions

  • the present invention relates to an interface circuit making it possible to receive and send information over a serial link, and it generally applies to any system that can communicate with another system, machine or peripheral device by through a serial link.
  • Such an interface circuit is inserted between a transceiver universal asynchronous (well known as UART) of a host system and a connector of a multicore cable of a serial link, and is often designed to provide insulation galvanic between said transceiver and the connector.
  • UART transceiver universal asynchronous
  • the known interface circuit described above therefore allows the host system in which it is incorporated, to communicate with another system, machine or peripheral device via a serial link isolated type RS485.
  • the object of the present invention is therefore to provide an interface circuit for the type described above, originally designed to operate with a RS485 type serial link, which is also capable of operating with a serial link of the RS232 type, with the addition of a few very simple components.
  • the circuit interface according to the invention is characterized in that the first electrode of said light emitter of the third opto-electronic coupler is connected by a fourth resistor to said source of direct voltage, and in that the second electrode of said transmitter light is connected to a first end of a fifth resistor the second end of which is intended to be connected directly to a third connector pin, whereby, taking as potential reference the first input / output of the converter circuit, the interface circuit is capable of transmitting on the second input / output of the circuit converting logical data signals conforming to standard RS232 and to receive on the second end of the fifth resistance, standard logical data signals RS232.
  • the data is transmitted on the driver of the second cable which is connected to the aforementioned second pin of the connector, itself connected to the second input / output of said circuit converter, while for reception in RS232, the data is received on the conductor of the second cable which is connected to the third aforementioned pin of said connector, itself connected to the second end of the fifth resistor, the reference potential for signals in transmission and reception being, in both cases, carried by the conductor of the second cable which is connected to the first pin above of the connector, itself connected to the first input / output of the converter circuit.
  • the reference number 1 designates the interface circuit according to the invention, which is interposed between the asynchronous transceiver universal (UART) 2 of a host system (not shown), for example a computer, and connector 3 of a multicore cable 4.
  • the circuit interface 1 is connected to the transceiver 2 by conductors 5, 6 and 7 which respectively carry the TX signal (data in transmission in from transceiver 2), the RTS signal (signal command from the transceiver 2) and the RX signal (data in reception towards the transceiver).
  • the circuit interface 1 is connected to connector 3 by two conductors 8 and 9 for an RS485 serial link and, in addition to conductors 8 and 9, by a third conductor 11 for an RS232 serial link.
  • both data sent towards the cable 4 that the data received from cable 4 is routed by the two conductors 8 and 9 on the form of differential signals.
  • the data sent sent to cable 4 are routed by driver 9, while data received through the cable 4 are routed by the conductor 11 and, in transmission as in reception, the potential present on the conductor 8 is taken as reference potential.
  • FIG 2 shows a known interface circuit 10, which is designed to an RS485 serial link and which can be inserted between a transceiver universal asynchronous and a connector in a similar way to that shown in Figure 1, with the exception of conductor 11, which in this case, does not exist.
  • the interface circuit 10 includes essentially, as the main component, a converter circuit 12 able to convert logic signals into differential signals in accordance with EIA485 (RS485) standard.
  • the converter circuit 12 has a data entry D, a command entry DE ⁇ RE a data output R, a first input / output A and a second input / output B.
  • Data input D is connected, via a first opto-electronic coupler OP1, on line 5 carrying the TX data emitted by the transceiver 2.
  • the command input DE ⁇ RE is connected, via a second opto-electronic coupler OP2, on line 6 carrying the RTS control signals sent by transceiver 2.
  • the data output R is connected, by via a third opto-electronic coupler OP3, to the line 7 routing to the transceiver 2 the RX data received through the cable 4.
  • Input / output A is connected by conductor 8 to a first pin of connector 3, while the other input / output B is connected by the conductor 8 to a second pin of the connector 3.
  • the resistors R 1 to R 8 are polarization resistors. Resistors R 1 , R 3 and R 5 are connected to a first DC voltage source Vcc1, while resistors R 2 , R 4 , R 6 and R 7 are connected to a second DC voltage source Vcc, and the resistance R 8 to ground
  • the converter circuit 12 is a standard circuit on the electronics market, for example a circuit of the type 75176 manufactured in particular by the company TEXAS INSTRUMENTS. Such a circuit operates in accordance with the following truth tables:
  • the interface circuit 10 of FIG. 2 then operates in the manner illustrated by the timing diagram of figure 3.
  • the signals illustrated in this chronogram are designated by the same reference symbols than those of the points where they appear in the interface circuit 10 of the figure 2, and they are represented by taking the mass as reference of potential (0V), as shown for the RTS signal in the figure 3.
  • the system When the RTS control signal from the transceiver 2 in Figure 1 is at logic level "0", the system is receiving (see the left part of the timing diagram of figure 3). That is to say, the differential signal arriving via data bus 8, 9 to the input pair A and B is transmitted as the RX logic signal to the transceiver 2. Conversely, when the RTS control signal is at logic level "1", the system is in transmission (see the right part of the timing diagram of figure 3). That is, the TX logic signal sent by the transceiver is transmitted as a signal differential at outputs A and B and from there to data bus 8.9.
  • FIG. 4 shows the interface circuit 1 according to the invention.
  • the interface circuit 1 in FIG. 4 differs from the interface circuit 10 in FIG. 2 in that it comprises two additional resistors R 9 and R 10 .
  • the resistor R 9 connects to the DC voltage source Vcc one of the electrodes (the cathode) of the light emitter EL (for example a emitting diode) of the third opto-electronic coupler OP3, which is connected to the output R of the converter 12.
  • resistor R 10 One end of the resistor R 10 is connected to the other electrode of the light emitting diode EL of the optoelectronic coupler OP3, which is connected to the DC voltage source Vcc by the resistor R 6 .
  • the other end of the resistor R 10 can be connected by the conductor 11 to one of the pins of the connector 3 ( Figure 1).
  • a protection diode D1 is mounted head to tail across the terminals of the light emitting diode EL of the optoelectronic coupler OP3.
  • the conductors 8, 9 and 11 are connected respectively to the pin # 7 , to pin 2 and to pin 3 of this connector.
  • the pin numbers shown above correspond to the actual numbers of the connector pins. If the connector 3 is a standardized connector of the DB9 type, the conductors 8, 9 and 11 will be connected respectively to pin # 5, to pin # 3 and to pin # 2 of said connector.
  • FIG 6 is a timing diagram illustrating the operation of the circuit interface 1 in Figure 4 for an RS232 serial link.
  • the signals RTS, DE ⁇ RE, TX, D, R and RX are represented by taking ground as a potential reference (0V), while the signals B and C which appear respectively in B and C in the interface circuit 1 in Figure 4, are referenced relative to the pin of the connector 3 which is connected to conductor 8 (input / output A of the converter circuit 12).
  • the transmission in RS232 takes place on the output B of the converter circuit 12 which is referenced relative to input / output A.
  • signal B when the TX signal emitted by transceiver 2 is active (ground or 0V), signal B will be active (positive voltage in RS232 transmission) while, when the signal TX is inactive (Vcc), signal B will be inactive (negative voltage in RS232 transmission), as shown in the right part of the timing diagram in Figure 6.
  • Reception in RS232 is carried out on the conductor 11 (signal C), while being referenced with respect to the connector pin 3 which is connected to the conductor 8 (input / output A). More precisely, when the signal C arriving on conductor 11 at a passive or inactive level (voltage negative in RS232 reception), it will block the opto-electronic coupler OP3, so that the RX signal takes a logic level "1". Conversely, when signal C has an active level (positive voltage in RS232 reception), it will drive the opto-electronic coupler OP3, from so that the RX signal takes a logic level "0" as shown in the left part of the timing diagram of figure 6.
  • the interface circuit 1 according to the invention obtained by simply adding two resistors (R 9 and R 10 ) to the known interface circuit 10 in FIG. 2, can be used to transmit and receive data in accordance with the RS485 standard or in accordance with the RS232 standard simply by changing the wiring of the connector 3.
  • a first cable 4 provided with a connector 3 two of the pins of which are connected respectively to the conductors 8 and 9 for a transmission according to the RS485 standard
  • a second cable 4 provided with a connector 3 three of whose pins are connected respectively to conductors 8, 9 and 11 for a transmission according to the RS232 standard.
  • the interface circuit according to the invention can be connected to machines or devices designed to communicate according to the RS485 standard using the first cable, or to machines or devices designed to communicate according to the RS232 standard using the second cable .
  • This is a great advantage since it is no longer necessary to change a card in the host system, in which the interface circuit according to the invention is incorporated, so that this host system can communicate with machines or apparatuses. external or remote according to the RS485 standard or the RS232 standard.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Claims (2)

  1. Schnittstellenschaltung, mit der sich Informationen zwischen einem universellen asynchronen Sender-Empfänger (2) und einem Mehrleiterkabel für serielle Verbindungen (4) in zwei Richtungen übertragen lassen, auf der Sender-Empfänger-Seite umfassend einen ersten, zweiten und dritten optoelektronischen Koppler (OP1-OP3) und auf der Verbindungskabelseite umfassend eine Wandlerschaltung (12) für die Umwandlung von Logiksignalen (TX), die von einem Sender-Empfänger (2) stammen, in differentielle Logiksignale (A - B) für ein Leitungspaar (4) des Verbindungskabels und umgekehrt von differentiellen Logiksignalen (A - B), die von diesem Leitungspaar (4) des Verbindungskabels stammen, in Logiksignale (RX) für den Sender-Empfänger (2) gemäß RS485-Standard, wobei die Wandlerschaltung (12) folgendes aufweist:
    a) einen Dateneingang (D) zum Empfangen der logischen Datensignale (TX), die vom Sender-Empfänger (2) stammen, über den ersten optoelektronischen Koppler (OP1);
    b) einen Steuereingang (DE\RE) zum Empfangen von Steuersignalen (RTS), die vom Sender-Empfänger stammen, über den zweiten optoelektronischen Koppler (OP2);
    c) einen Datenausgang (R) zum Senden der Datensignale (RX) über den dritten optoelektronischen Koppler (OP3) an den Sender-Empfänger (2), wobei der Ausgang (R) an eine erste Elektrode eines Lichtsenders (LE) des dritten optoelektronischen Kopplers (OP3) angeschlossen ist, wobei eine zweite Elektrode des Lichtsenders über einen ersten Widerstand (R6) mit einer Gleichstromquelle (Vdc) verbunden ist;
    d) einen ersten Eingang/Ausgang (A), der über einen zweiten Widerstand (R7) mit der Gleichstromquelle (Vdc) verbunden ist und dazu bestimmt ist, direkt an eine ersten Klemme eines Verbindungselements (3) angeschlossen zu werden, das die Schnittstellenschaltung (1) mit dem Verbindungskabel (4) verbindet; und
    e) einen zweiten Eingang/Ausgang (B), der über einen dritten Widerstand (R8) mit einer elektrischen Masse verbunden ist und dazu bestimmt ist, direkt an eine zweite Klemme des Verbindungselements (3) angeschlossen zu werden;
       dadurch gekennzeichnet, dass die erste Elektrode des Lichtsenders (LE) des dritten optoelektronischen Kopplers (OP3) über einen vierten Widerstand (R9) an die Gleichstromquelle (Vdc) angeschlossen ist, und dass die zweite Elektrode des Lichtsenders (LE) mit einem ersten Ende eines fünften Widerstands (R10) verbunden ist, dessen zweites Ende (C) dazu bestimmt ist, direkt an eine dritte Klemme des Verbindungselements (3) angeschlossen zu werden, wodurch, wenn der erste Eingang/Ausgang (A) der Wandlerschaltung (12) als Potentialreferenz gewählt wird, die Schnittstellenschaltung (1) in der Lage ist, am zweiten Eingang/Ausgang (B) der Wandlerschaltung (12) logische Datensignale gemäß RS232-Standard zu senden und an dem zweiten Ende (C) des fünften Widerstands (R10) logische Datensignale gemäß RS232-Standard zu empfangen.
  2. Schnittstellenschaltung entsprechend Anspruch 1, dadurch gekennzeichnet, dass der Lichtsender (LE) eine Senderdiode ist, und dass eine Schutzdiode (D1) an den Klemmen der Senderdiode in entgegengesetzter Richtung montiert ist.
EP19990401203 1998-06-02 1999-05-19 Zwei-Standard-Schnittstellenschaltung für serielle Verbindung Expired - Lifetime EP0962869B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9806878A FR2779250B1 (fr) 1998-06-02 1998-06-02 Circuit d'interface bistandard pour liaison serie
FR9806878 1998-06-02

Publications (2)

Publication Number Publication Date
EP0962869A1 EP0962869A1 (de) 1999-12-08
EP0962869B1 true EP0962869B1 (de) 2004-03-10

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EP (1) EP0962869B1 (de)
DE (1) DE69915410T2 (de)
FR (1) FR2779250B1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102915291A (zh) * 2012-09-29 2013-02-06 无锡华润矽科微电子有限公司 一种具有自动换向功能的rs485接口电路

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DE10046806A1 (de) * 2000-09-21 2002-05-23 Infineon Technologies Ag Tri-State-Treiberanordnung
CN101895289A (zh) * 2010-07-05 2010-11-24 艾默生网络能源有限公司 一种信号接口电路
CN103701452A (zh) * 2012-09-27 2014-04-02 深圳市朗驰欣创科技有限公司 一种多功能通讯接口信号转换器
CN103227636B (zh) * 2013-03-27 2016-07-13 武汉新慧电气科技有限公司 一种用于多控制器互连的高隔离直接并接半双工通信接口模块
CN103633985A (zh) * 2013-12-11 2014-03-12 济南诺辉节能技术开发有限公司 Rs485通信电路
CN105159194A (zh) * 2015-08-25 2015-12-16 天津市英贝特航天科技有限公司 Rs-485串口接收发送数据切换电路及切换方法
CN111630780B (zh) * 2018-10-26 2022-08-16 深圳配天智能技术研究院有限公司 转换电路、转接板以及控制***
CN114326465B (zh) * 2021-11-22 2023-11-21 江苏科技大学 一种共用485电路与控制方法
CN114925006B (zh) * 2022-05-06 2024-03-05 青岛艾诺仪器有限公司 一种半无源rs232转rs232通信方法
CN116340238B (zh) * 2023-03-28 2024-01-30 怀化建南机器厂有限公司 一种mcu串口与rs485转换器的接口电路

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DE4113920A1 (de) * 1991-04-29 1992-11-05 Ulrich Karstein Datentechnik Vorrichtung zum austauschen von daten zwischen einem personalcomputer und einem speicherprogrammierbaren geraet, einer steuerung o. dgl.
DE4133636A1 (de) * 1991-10-11 1993-04-15 Lawrenz Wolfhard Steuerungsbaustein

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102915291A (zh) * 2012-09-29 2013-02-06 无锡华润矽科微电子有限公司 一种具有自动换向功能的rs485接口电路

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Publication number Publication date
DE69915410D1 (de) 2004-04-15
FR2779250A1 (fr) 1999-12-03
EP0962869A1 (de) 1999-12-08
FR2779250B1 (fr) 2001-09-07
DE69915410T2 (de) 2005-02-17

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