EP0944919A1 - Transistor mis a grille metallique auto-alignee et son procede de fabrication - Google Patents
Transistor mis a grille metallique auto-alignee et son procede de fabricationInfo
- Publication number
- EP0944919A1 EP0944919A1 EP97952059A EP97952059A EP0944919A1 EP 0944919 A1 EP0944919 A1 EP 0944919A1 EP 97952059 A EP97952059 A EP 97952059A EP 97952059 A EP97952059 A EP 97952059A EP 0944919 A1 EP0944919 A1 EP 0944919A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- grid
- silicon
- dummy grid
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 title abstract description 13
- 239000002184 metal Substances 0.000 title abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 241
- 229910052710 silicon Inorganic materials 0.000 claims description 73
- 239000010703 silicon Substances 0.000 claims description 73
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 72
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 46
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 41
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 41
- 230000015572 biosynthetic process Effects 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 32
- 238000004519 manufacturing process Methods 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 238000002513 implantation Methods 0.000 claims description 25
- 125000006850 spacer group Chemical group 0.000 claims description 23
- 230000008030 elimination Effects 0.000 claims description 21
- 238000003379 elimination reaction Methods 0.000 claims description 21
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 17
- 238000005498 polishing Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000007493 shaping process Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims description 2
- 239000011247 coating layer Substances 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- 238000010301 surface-oxidation reaction Methods 0.000 claims 1
- 239000012777 electrically insulating material Substances 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 239000005380 borophosphosilicate glass Substances 0.000 description 7
- 230000010354 integration Effects 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 238000010405 reoxidation reaction Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- the present invention relates to an MIS transistor with a self-aligned gate and to its manufacturing process.
- MIS transistor is understood to mean a transistor having a Metal-Insulator-Semiconductor structure such as, for example MOS (Metal-Oxide-Semiconductor) transistors.
- MOS Metal-Oxide-Semiconductor
- the invention relates more particularly to the manufacture on a silicon substrate of such transistors, capable of operating in the microwave domain.
- the invention finds applications in microelectronics for the manufacture of microwave and / or power circuits, for example for the production of circuits usable in the telecommunications field.
- the components and circuits of the microwave type are usually produced on gallium arsenide (AsGa) substrates or on silicon (Si) substrates.
- the circuits formed on one substrate of gallium arsenide are generally not very complex and does not have a high integration density.
- the architecture of these circuits is therefore not optimized from the point of view of their compactness.
- a microwave component in this case a MOS transistor (Metal Oxide Semiconductor), produced on a silicon substrate.
- the transistor of FIG. 1 comprises a source region 10, a channel region 12 and a drain region 14 defined in a silicon substrate 16.
- the source and the drain are, for example, formed by implantation of n-type or p-type doping impurities and constitute regions of lower resistivity.
- An insulating layer of silicon oxide 18 is formed on the surface of the substrate 16 and covers the source, channel and drain regions.
- a non-through opening 20 is formed by etching in the oxide layer 18, substantially perpendicular to the channel region 12. At the bottom of the opening 20, a thin oxide layer 22 forms a grid insulation. A gate 24 is finally formed in the opening 20.
- the material forming the gate in this case a metal, has a low resistivity and thus allows high frequency operation of the transistor produced.
- the integration density of the devices produced in accordance with FIG. 1 depends on the precision with which the opening 20, and hence the grid 24, are aligned with respect to the channel 12 and with respect to the source and source regions 10, 14 drain. This accuracy depends directly on the quality of the manufacturing tools (especially alignment) of the semiconductor devices.
- a solution for increasing the compactness and the integration density of the circuits consists in self-aligning the grid with respect to the source zones and of drain. It is considered that the grid is self-aligned with respect to the source and drain zones when the relative position of the grid and of the source and drain zones does not result from an alignment of the means used (masks for example) to make these parts, but when the position of the source and drain zones is directly defined by the position of the grid itself.
- the self-alignment of the grid with respect to the source and drain regions results from a method of forming the source and drain regions in which these regions are formed by implantation of impurities in the substrate. using the grid, made previously, as an implantation mask. The location of the grid thus precisely and automatically fixes the position of the source of the channel and the drain.
- the processes for forming transistors with a grid self-aligned with respect to the source and drain zones generally involve heat treatments carried out at high temperature.
- heat treatment at a temperature of the order of 750 ° C or more is carried out after the implantation of impurities, in order to activate the source and drain zones.
- the gate material used to make the transistors should preferably have a resistivity of between approximately 1 and 10 ⁇ .cm.
- the materials having a resistivity situated in the indicated range are not capable of withstanding the temperatures of the heat treatments used in the indicated methods of manufacturing transistors with a self-aligned grid. In particular, these materials are not capable of withstanding temperatures greater than or equal to 750 ° C.
- a material frequently used for producing the grid of the transistors with a self-aligned grid is polycrystalline silicon (Si poly).
- Polycrystalline silicon is in fact capable of withstanding the temperature of the heat treatments used during the formation of these transistors.
- the resistivity of polycrystalline silicon is not compatible with the envisaged applications of transistors in the microwave domain. Furthermore, it is not known how to sufficiently decrease the resistivity of polycrystalline silicon to obtain operation of the transistors at microwave frequency.
- An object of the present invention is, therefore, to propose a method of manufacturing an MIS transistor with gate, source and drain self-aligned and capable of operating in the microwave range.
- An object of the invention is also to propose a method for manufacturing a compact transistor with interconnections allowing the reduction of the contact guard with respect to the edge of the gate conductors or interconnections.
- An object of the invention is also to increase the integration density of the interconnections in a circuit comprising transistors with gate, source and drain self-aligned.
- Another object of the invention is to propose a transistor designed so as to have a very high cut-off frequency.
- An object of the invention is finally to provide transistors compatible with the production of CMOS circuits (complementary MOS) with a high integration density.
- the subject of the invention is more precisely a method of manufacturing on a semiconductor substrate MIS (Metal-Insulator-Semiconductor) transistors.
- the method is defined by claim 1.
- the invention also relates to a MOS transistor as defined by claim 23.
- the dummy grid produced during the process, has a double function: it allows, at first, to define the location of the source and drain regions during step b), then to define the location of the final gate of the transistor made of low resistivity material. Indeed, the coating of the dummy grid on its lateral flanks forms, after the elimination of this dummy grid, a "mold" for the final grid.
- the final grid is formed from one or more materials. These materials are each chosen so as to have a low resistivity. For example, the resistivity of the materials can be chosen in a range from 1 to 10 ⁇ .cm.
- step a) may include:
- the formation on the substrate of a stack comprising in order an oxide layer called the pedestal layer, a layer of polycrystalline silicon and a layer of silicon nitride, and
- the dummy grid consists, in order from the substrate, of a layer of thin silicon oxide, of a layer of polycrystalline or amorphous silicon and then a layer of silicon nitride.
- the silicon nitride layer can be used to form the lateral coating of the dummy grid.
- step c) comprises:
- the silicon nitride layer provided in the stack forming the dummy grid can advantageously be used to serve as a polishing stop layer.
- step b) can comprise:
- the lateral spacers on the sides of the dummy grid can, for example, be formed by:
- the deposit is considered to be in conformity when it matches the shape of the surface of the support on which it is made. Thanks to the conformal deposition of the phosphorus-doped silicon oxide layer, it covers and is in contact not only on the side faces of the dummy grid, but also on the top of this grid.
- the anisotropic etching of the phosphorus-doped silicon oxide layer makes it possible to completely eliminate it on top of the dummy grid while preserving the parts of the layer intended to form the lateral spacers.
- step b) of the method can also comprise siliciding the source and drain regions.
- the siliciding is also self-aligned with respect to the dummy grid: it contains a metal deposit which reacts by forming an alloy (silicide) selectively on the exposed areas of silicon.
- step d) of the method comprises the elimination by etching of the layers of silicon nitride and of polycrystalline silicon from the dummy grid, the pedestal layer forming during this etching a layer d 'etching stop.
- the pedestal layer can also be removed during step d). In this case, a new grid insulator layer is formed before the final grid is made.
- step d) further comprises, before the formation of the final grid, a partial attack of the first and second oxide layers to form a flare after the elimination of the dummy grid .
- the flare extends from the surface of the substrate and widens toward the upper surface of the first and second oxide layers.
- the difference in the materials used to form the first and second layers is used to obtain a difference in attack speed of these layers.
- This measurement makes it possible to configure the flare according to a particular shape.
- the flare, and leaving the final grid may have, for example, a section in a T shape.
- step d) may additionally comprise a partial elimination of the lateral spacers of the dummy grid. This elimination, which can be carried out concomitantly with the attack materials of the first and second oxide layers, then contributes to the shaping of the flare.
- the realization of the final grid may include, in a particular example, a successive and substantially conformal deposition of a layer of titanium nitride (TiN) and a layer of tungsten (W) then a planarization of these layers with stopping on the electrical insulating material. Thanks to the first layer of titanium nitride (TiN), good adhesion of the tungsten layer (W) to an underlying layer of gate insulator is guaranteed.
- the grid insulator layer for example made of silicon oxide, is preferably formed just before the final grid is produced. More generally, the material of the final gate can advantageously be chosen with an extraction potential such that the Fermi level at equilibrium at the gate / gate insulator interface of the transistor is located in the middle of the band gap. of the semiconductor.
- the material of the grid may have a resistivity comprised, according to an advantageous example of embodiment, between l ⁇ .cm and lO ⁇ .cm.
- the method of the invention can also comprise, before step a), the formation by doping, in the substrate, of a channel region; the dummy grid being formed above the channel region.
- the process can also be completed after step d) by the following steps: e) formation of contact points on the source and drain regions and on the grid, f) metallization of the contact points.
- the contact points formed on the grid and the source and drain regions are advantageously formed through a layer of insulating material deposited on the free surface of the structure obtained after polishing the first and second layers of silicon oxide (or BPSG).
- the method of manufacturing a transistor with an insulated gate made of a material of low resistivity, described above, can further comprise the formation of a transistor with a silicon gate known as a gate-silicon.
- Step a) comprises the formation, on the substrate, of a stack comprising in order, in at least one first region, an oxide layer known as a pedestal layer, a layer of polycrystalline or amorphous silicon and a layer of silicon nitride, and comprising in at least a second region, the oxide layer called the pedestal layer, the polycrystalline or amorphous silicon layer, a layer of silicon oxide called the intermediate layer, and the silicon nitride layer; and shaping the stack by etching in order to produce the dummy grid with lateral flanks in the first region and at least one grid called the silicon grid in the second region,
- step b) comprises the formation in the substrate of source and drain regions self-aligned on the dummy grid and on the silicon grid respectively
- step c) comprises the lateral coating of the dummy grid and of the silicon grid with at least one electrical insulating material
- step c) is preceded by the elimination of the layer of silicon nitride on the silicon grid in the second region, the elimination of the pedestal layer around the dummy grid and the silicon grid, and l elimination of the intermediate layer of silicon oxide
- step d) comprises the formation in the second region of a protective layer, covering the silicon grid during the elimination of the dummy grid.
- layers or common parts of the low-resistivity gate transistors and of the silicon gate transistor are produced simultaneously in the first and second regions.
- a self-aligned siliciding of the source and drain regions and of the layer of polycrystalline or amorphous silicon of the silicon grid is possible to carry out, after the elimination of the pedestal layer and of the intermediate layer and before step c), a self-aligned siliciding of the source and drain regions and of the layer of polycrystalline or amorphous silicon of the silicon grid.
- the siliciding makes it possible to improve the contact making on the source, drain and gate regions.
- a thin layer of silicon nitride can be deposited on these regions.
- the lateral coating of the dummy gate and of the silicon gate during step c) can comprise: deposit, already mentioned, of a first electrical insulating layer of phosphorus-doped silicon oxide and then of a second electrical insulating layer of unintentionally doped silicon oxide, the first and second layers coating the dummy grid and the grid silicon, and
- the function of the thin doped silicon oxide layer preserved on the silicon layer Polycrystalline or amorphous of the silicon grid is mainly to protect the silicon grid when removing the layer of silicon nitride on the dummy grid and when removing the dummy grid itself.
- - Figure 1 already described, is a schematic section of a microwave MOS transistor of a known type.
- - Figures 2 and 3 are schematic sections of a transistor during manufacture according to the method of the invention. They illustrate the formation of a dummy grid and source and drain regions.
- - Figures 4 and 5 are schematic sections of the transistor of Figure 3 after coating of the dummy gate.
- FIGS. 6 and 7 are schematic sections of the transistor of Figure 5 and illustrate in particular a step of eliminating the dummy gate.
- FIG. 10 is a diagrammatic section of two interconnections produced in accordance with the invention at the same time as transistors, and illustrates a step of manufacturing grid interconnects.
- FIGS 11 to 19 are schematic sections of structures illustrating successive stages of a method of manufacturing a first gate transistor made of low resistivity material and a second silicon gate transistor, in accordance with an improvement of the invention.
- FIGS. 20 to 23 are schematic sections of a gate transistor of low resistivity material during manufacture, according to a variant of the method of the invention.
- FIG. 24 is a schematic section of a gate transistor of low resistivity material and a silicon gate transistor obtained according to the variant of the method of the invention.
- the transistor is produced on a silicon substrate 100 whose surface has been oxidized in order to form an oxide layer 102 of silicon known as the pedestal layer.
- a layer of polycrystalline or amorphous silicon 104 On the layer 102 are successively deposited a layer of polycrystalline or amorphous silicon 104 then a layer of silicon nitride 106. All of these layers form a stack 110.
- the total thickness of the layers 104 and 106 is, for example, on the order of 100 to 500 nm and corresponds substantially to the thickness of the gate of the transistor which will ultimately be obtained at the end of the manufacturing process.
- An etching mask 108 shown in broken lines, such as a photosensitive resin mask, is formed on the layer 106 of silicon nitride. This mask defines the location, the size and the shape of a dummy grid which it is desired to produce in the stack 110.
- the layers 102, 104 and 106 of the stack 110 are eliminated by etching with the exception of a portion protected by the mask 108. This portion of the stack forms the body of the dummy grid, identified with the reference 112 on Figure 3.
- the side or sides of the dummy grid 112, and more precisely the sides corresponding to the polycrystalline silicon layer 104 are subjected to thermal oxidation which leads to the formation of a so-called thermal oxide layer 114 indicated in FIG. 3.
- thermal oxide layer 114 indicated in FIG. 3.
- the top of the layer 104 of polycrystalline silicon is protected by the layer 106 of silicon nitride.
- the pedestal layer 102 of silicon oxide makes it possible to absorb or limit the stresses appearing during the thermal oxidation of the sides of the dummy grid.
- the formation of the dummy grid is followed by a first implantation of ions at low dose.
- the ions are chosen so as to produce areas of a type of conductivity p or n.
- boron ions are implanted with a dose of 10 13 to 10 14 cm “2 at an energy of 3 to 25 keV for PMOS.
- phosphorus or arsenic in the same dose and energy range.
- the first implantation is followed by the formation on the side (s) of the dummy grid of lateral spacers 116 visible in FIG. 3.
- the lateral spacers made of phosphorus-doped silicon oxide, are preferably formed by the conformal deposition of a layer of this material, then by anisotropic etching of this layer.
- the first and second implantations thus make it possible to form, on either side of the dummy grid, gradual source and drain regions. These regions are identified in FIG. 3 with the references 118 and 120.
- the source and drain regions 118 and 120 are subjected to high temperature siliciding of the order of 500 ° C to 750 ° C in order to improve future contact with these regions.
- the silicide layer, formed in the source and drain regions, is indicated with the references 119 and 121 respectively.
- the layers 124 and 126 are polished with a stop on the silicon nitride layer 106 of the dummy grid 112. This operation makes it possible to form, as shown in FIG. 5, a flat surface to which the top of the dummy grid is flush.
- the thickness of the oxide layers 124 and 126, as well as the height of the dummy grid, is adjusted as a function of the height of the final grid which it is desired to produce as well as the size of a flare practiced in these layers and described in the following text.
- the thickness of 124 is chosen to be greater than or equal to the positioning tolerance of the lithography.
- the thickness 126 is chosen equal to or greater than the height of the dummy grid to allow good planarization.
- the process is continued by eliminating the dummy grid.
- the layer 106 of silicon nitride and the layer 104 of polycrystalline silicon are removed by etching. During this etching, the pedestal layer 102 can serve as an etching stop layer.
- the elimination of the dummy grid defines an opening 130 whose location, dimensions and shape condition the production of the final grid.
- the opening 130 can be flared upwards, that is to say away from the substrate, as shown in FIG. 7.
- a partial attack of the first and second oxide layers 124, 126 as well as lateral spacers 116 and the layer of thermal oxide 114 is operated. This is for example an attack with hydrofluoric acid.
- the acid attack more or less rapid depending on the materials, makes it possible to flare the opening 130 according to a particular profile chosen.
- a T-profile In the case of the example described, it is, seen in section, a T-profile.
- the attack speed of the layer of lateral spacers 114 in PSG is 5 times greater than the attack speed of the thermal oxide and 3 times greater than the attack speed of the intrinsic oxide of layer 126. If layer 126 is made of borophosphosilicate (BPSG), it is noted that the attack speed of PSG is 6 times that of BPSG.
- BPSG borophosphosilicate
- Figure 8 shows the establishment of a gate insulator layer 132.
- This layer is intended to electrically isolate the final gate, which will be produced, from the transistor channel.
- Layer 132 is advantageously a layer of silicon oxide obtained by oxidation. It can be noted that part of the source and drain regions were exposed during the prior chemical attack ( Figure 7). A differential oxidation rate effect tends to cause stronger oxidation in these doped regions, during the formation of the gate insulator layer 132.
- FIG. 9 shows the formation of the final grid 133.
- a material of the "mid-gap" type that is to say a material such that its Fermi level coincides with roughly with the intrinsic Fermi level of the semiconductor.
- the "mid-gap" material can be chosen from the following materials TiN, Ti, Cu, W and Al.
- the grid 133 comprises a TiN / W bilayer system in which the layer of titanium nitride forms a bonding layer for the tungsten.
- the layers 134 of titanium nitride and 136 of tungsten are deposited using a low-pressure chemical vapor deposition technique, called LPCVD, making it possible to obtain a conformal deposit.
- LPCVD low-pressure chemical vapor deposition technique
- the TiN / W bilayer system can be replaced, for example by a TiN / Al bilayer system.
- the layers 134 and 136 are then subjected to a chemical mechanical polishing or an anisotropic etching with stopping on the oxide layer 126. This treatment makes it possible to obtain a smooth and flat upper surface 138. It can be noted that when using an anisotropic etching process, beforehand, a layer of resin is deposited to allow planarization.
- FIG. 9 clearly shows the flared shape of the final gate of the transistor thus obtained.
- the cross-sectional shape of the gate is a T-shape. This shape has both advantages as to the operation of the transistor and as to the interconnection of transistors according to the invention to form a circuit.
- the T-shape of the gate makes it possible in particular to reduce the resistance of the gate, and thus contributes to increasing the cut-off frequency of the transistor in the microwave operating mode.
- Figure 10 shows the advantages of the particular shape of the grid for interconnection.
- metal lines 99 and 99a produced in accordance with the invention.
- the metallic lines can be either transistor gates or interconnection lines on field oxide.
- An interconnection metal layer is subsequently deposited on the oxide layer 140 and in the openings 142, 142a. This layer is then shaped to form other interconnection lines. As shown in the figure, thanks to the widening of the grids and their T-shape, greater misalignment between the location of the openings 142, 142a and the grids 133, 133a is authorized. The metal of the grid is always present under the contact even if a clearance with respect to the interconnection lines (openings 142, 142a) is zero.
- Figures 11 and following show a variant of the method of the invention in which two types of transistors are produced.
- One or more transistors are produced on the one hand with a grid made of a material with low resistivity, for example made of TiN / W as described above, and on the other hand, one or more transistors with a silicon grid called the silicon grid.
- the figures only show the manufacture of a single transistor of each type.
- FIG. 11 we start from a structure comprising a silicon substrate 100, a pedestal layer 102 of silicon oxide, a layer of amorphous or polycrystalline silicon 104 and a layer of silicon nitride 106. refer to this subject in Figure 2 and the corresponding description.
- the structure comprises two regions designated respectively by first region and second region and identified by the references 200 and 200a. It can be noted in FIG. 11 that in the second region 200a a layer of silicon oxide 105 is interposed between the layer of polycrystalline or amorphous silicon 104 and the layer of silicon nitride 106. Preferably, before the formation of the silicon nitride layer 106, the free surface of the silicon layer 104 can be oxidized to form over its entire surface an oxide layer. The oxide layer is then removed by wet etching in the region 200 before the formation of the layer 106 of silicon nitride. It may be noted in this regard that it is possible to form a structure having a plurality of regions equivalent to the first region 200 and a plurality of regions equivalent to the second region.
- a dummy grid 112 in the first region 200 and a grid 112a are then produced in the structure of FIG. 11, a dummy grid 112 in the first region 200 and a grid 112a, called in a simplified manner "silicon grid" in the second region 200a.
- the dummy grid 112 of FIG. 12 is identical to the dummy grid 112 of FIG. 3.
- the silicon grid 112a is simply distinguished by the layer 105 of additional silicon oxide between the layer of silicon 104 and the layer of nitride. silicon 106.
- the grids 112 and 112a have flanks on which a thermal oxide layer 114 and lateral spacers 116 are formed.
- the grids 112, 112a of the thermal oxide layer 114 and spacers 116 are formed according to methods identical to those exposed on the subject of the formation of the grid 112, of the layer 114 and of the spacers 116 of FIG. 3. We can therefore refer to this subject in the description above.
- the spacers are etched, the pedestal oxide is eliminated from the source and drain regions. We then carry out a reoxidation before the step implantation at high dose (n + , p + ), to form a layer 117 called "reoxidation".
- a second etching of the silicon 104 is then carried out, this second etching being selective with respect to with silicon oxide.
- FIG. 12 also shows the formation of source and drain regions 118a, 120a, 118, 120 on either side of the grids 112a and 112.
- the source and drain regions 120a and 118 form a single doped region common to the two transistors.
- the silicon nitride layer of the silicon grid 112a is removed by etching with stop on the layer 105 of silicon oxide. During this etching, the substrate is protected by the reoxidation layer 117. After this operation, a possible implantation of doping impurities can take place in the layer 104 of the silicon grid 112a.
- This implantation can take place, for example, if the gate material has not been previously doped, during its deposition.
- the entire first region 200 is protected by a resin layer 202.
- the resin layer preserves the entire region 202 and the dummy grid of the treatments carried out in the second region 200a.
- an etching is carried out making it possible to eliminate the reoxidation layer 117 and the layer 105 of the silicon grid 112a.
- This operation makes it possible, as shown in FIG. 14, to expose the substrate in the source and drain regions, and to expose the layer 104 of polycrystalline silicon of the gate 112a.
- Siliconization of the exposed silicon makes it possible to form silicided zones 119a, 121a, 119, 121 on the source and drain regions 118a, 120a, 118, 120.
- a layer of silicide 107 is also formed on the layer of silicon 104 of the silicon grid 112a as shown in Figure 15.
- the process continues with the successive conformal deposition of a first layer 124 of phosphorus-doped silicon oxide and then of a second layer 126 of unintentionally doped intrinsic silicon oxide, or borophosphosilicate (BPSG).
- the layers 124 and 126 coat the dummy grid 112 and the silicon grid 112a, as shown in FIG. 16.
- a planarization polishing with stopping on the silicon nitride layer 106 of the dummy grid makes it possible to obtain the structure shown in FIG. 17. It can be noted that part of the oxide layer 124 is preserved on the grid. silicon 112a during this polishing.
- the operations of depositing the oxide layers 124 and 126, as well as the polishing are operations similar to those illustrated in FIGS. 4 and 5. can therefore refer on this subject to the corresponding description of FIGS. 4 and 5.
- a following operation consists in eliminating the dummy grid 112.
- the part of the oxide layer 124 preserved on the silicon grid 112a makes it possible to protect it during the etching of the layers of silicon nitride 106 and silicon 104 of the grid dummy 112.
- deoxidation After the removal of the silicon nitride and silicon layers from the dummy grid, deoxidation also makes it possible to remove the layer of pedestal oxide 102 thus exposed. An opening 130 is thus obtained. During this deoxidation the part of the oxide layer 124 preserved on the silicon grid risks being partly eliminated.
- a next operation involves the production of a final grid 133 in the opening 130, after a possible flaring of the opening 130.
- a thin layer of silicon nitride 123 is deposited on the structure.
- the layer of silicon nitride 123 is deposited before the formation of the first and second layers of silicon oxide (or BPSG) 124 and 126, in order to obtain the structure illustrated in FIG. 20.
- the layer 123 of silicon nitride covers the layers 119 and 121 of silicide formed on the source and drain regions 118, 120, the lateral spacers 116, and the layer of silicon nitride 106 at the top of the dummy grid. 112.
- the structure illustrated in FIG. 21 is obtained. It can be seen in this figure that the layer of silicon nitride 123 may be partly started above the layer of silicon nitride 106.
- FIG. 22 shows the elimination of the dummy grid and the formation of an opening 130 having a flared shape. These operations are described in more detail with reference to FIGS. 6 to 8. It can be seen that a portion of the layer of silicon nitride remains above the source and drain regions and between the remaining parts of the lateral spacers 116 and of the first oxide layer 124.
- FIG. 23 shows the production of a final grid 133. It is a bilayer type grid as described with reference to FIG. 9.
- the layer 123 of silicon nitride protects the layers of silicide 119 and 121 in the source and drain regions. This protection prevents partial oxidation of these regions during the process and thus guarantees excellent source and drain contact.
- the improvement described above is also applicable to the process leading to the concomitant production of silicon grids and metal grids (material of low resistivity).
- the formation of the silicon nitride layer 123 also takes place after the formation of the silicide layers 119, 121, 119a, 121a illustrated in FIG. 15, and before the formation of the oxide layers 124 and 126, illustrated in figure 16.
- the silicon nitride layer covers the silicon layers 119a, 121a, 119, 121 and extends between the lateral spacers 116 and the oxide layer 124, on the sides of the silicon grid 112a and of the final grid 133.
- the layer of silicon nitride 123 is also found in the silicon grid 112 finally obtained, between the layer of silicide 107 and the part of the oxide layer 124 preserved on the silicon grid 112 during polishing of layers 124 and 126.
- TMT Two Mode Channel FET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9615436 | 1996-12-16 | ||
FR9615436A FR2757312B1 (fr) | 1996-12-16 | 1996-12-16 | Transistor mis a grille metallique auto-alignee et son procede de fabrication |
PCT/FR1997/002300 WO1998027582A1 (fr) | 1996-12-16 | 1997-12-15 | Transistor mis a grille metallique auto-alignee et son procede de fabrication |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0944919A1 true EP0944919A1 (fr) | 1999-09-29 |
Family
ID=9498708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP97952059A Withdrawn EP0944919A1 (fr) | 1996-12-16 | 1997-12-15 | Transistor mis a grille metallique auto-alignee et son procede de fabrication |
Country Status (5)
Country | Link |
---|---|
US (1) | US6346450B1 (fr) |
EP (1) | EP0944919A1 (fr) |
JP (1) | JP4560600B2 (fr) |
FR (1) | FR2757312B1 (fr) |
WO (1) | WO1998027582A1 (fr) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4564467B2 (ja) * | 1998-06-29 | 2010-10-20 | 株式会社東芝 | Mis型トランジスタおよびその製造方法 |
US6177303B1 (en) * | 1998-09-28 | 2001-01-23 | U.S. Philips Corporation | Method of manufacturing a semiconductor device with a field effect transistor |
FR2788629B1 (fr) | 1999-01-15 | 2003-06-20 | Commissariat Energie Atomique | Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur |
KR20010025030A (ko) | 1999-03-17 | 2001-03-26 | 롤페스 요하네스 게라투스 알베르투스 | 반도체 디바이스 제조 방법 |
US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
EP1134798A1 (fr) * | 2000-03-15 | 2001-09-19 | Infineon Technologies AG | Dispositif semiconducteur, sa méthode de fabrication et méthode de fabrication de contacts électriques sur un substrat semiconducteur |
EP1137059A1 (fr) * | 2000-03-24 | 2001-09-26 | Infineon Technologies AG | Dispositif semiconducteur, sa méthode de fabrication et méthode de fabrication de contacts électriques entre des éléments de circuit séparés |
FR2810161B1 (fr) * | 2000-06-09 | 2005-03-11 | Commissariat Energie Atomique | Memoire electronique a architecture damascene et procede de realisation d'une telle memoire |
FR2810157B1 (fr) * | 2000-06-09 | 2002-08-16 | Commissariat Energie Atomique | Procede de realisation d'un composant electronique a source, drain et grille auto-allignes, en architecture damascene |
US6593193B2 (en) * | 2001-02-27 | 2003-07-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
DE10231965B4 (de) * | 2002-07-15 | 2006-06-14 | Infineon Technologies Ag | Verfahren zur Herstellung einer T-Gate-Struktur sowie eines zugehörigen Feldeffekttransistors |
FR2848726B1 (fr) * | 2002-12-16 | 2005-11-04 | Commissariat Energie Atomique | Transistor mis a grille auto-alignee et son procede de fabrication |
US20050269644A1 (en) * | 2004-06-08 | 2005-12-08 | Brask Justin K | Forming integrated circuits with replacement metal gate electrodes |
US7718479B2 (en) * | 2004-08-25 | 2010-05-18 | Intel Corporation | Forming integrated circuits with replacement metal gate electrodes |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7271045B2 (en) * | 2005-09-30 | 2007-09-18 | Intel Corporation | Etch stop and hard mask film property matching to enable improved replacement metal gate process |
JP4967313B2 (ja) * | 2005-11-09 | 2012-07-04 | ソニー株式会社 | 半導体装置の製造方法 |
US7595248B2 (en) * | 2005-12-01 | 2009-09-29 | Intel Corporation | Angled implantation for removal of thin film layers |
JP2007294945A (ja) * | 2007-04-02 | 2007-11-08 | Toshiba Corp | 半導体装置の製造方法 |
JP5253797B2 (ja) * | 2007-12-07 | 2013-07-31 | 株式会社東芝 | 半導体装置 |
US8735235B2 (en) | 2008-08-20 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit metal gate structure and method of fabrication |
FR2943832B1 (fr) | 2009-03-27 | 2011-04-22 | Commissariat Energie Atomique | Procede de realisation d'un dispositif memoire a nanoparticules conductrices |
FR2943850B1 (fr) | 2009-03-27 | 2011-06-10 | Commissariat Energie Atomique | Procede de realisation d'interconnexions electriques a nanotubes de carbone |
KR101815527B1 (ko) | 2010-10-07 | 2018-01-05 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
KR101784324B1 (ko) * | 2011-04-18 | 2017-11-06 | 삼성전자 주식회사 | 반도체 장치의 제조 방법 |
JP5390654B2 (ja) * | 2012-03-08 | 2014-01-15 | 株式会社東芝 | 半導体装置の製造方法 |
US20150118836A1 (en) * | 2013-10-28 | 2015-04-30 | United Microelectronics Corp. | Method of fabricating semiconductor device |
US9349817B2 (en) * | 2014-02-03 | 2016-05-24 | Taiwan Semiconductor Manufacturing Co., Ltd | Semiconductor device including spacers having different dimensions |
US9954112B2 (en) | 2015-01-26 | 2018-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6254960A (ja) * | 1985-09-04 | 1987-03-10 | Nec Corp | Mis形電界効果トランジスタ |
JPH023244A (ja) * | 1988-06-20 | 1990-01-08 | Fujitsu Ltd | 半導体装置の製造方法 |
US5168072A (en) * | 1990-10-12 | 1992-12-01 | Texas Instruments Incorporated | Method of fabricating an high-performance insulated-gate field-effect transistor |
US5391510A (en) * | 1992-02-28 | 1995-02-21 | International Business Machines Corporation | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps |
JPH065852A (ja) * | 1992-06-23 | 1994-01-14 | Oki Electric Ind Co Ltd | Mosfet及びその製造方法 |
US5268330A (en) * | 1992-12-11 | 1993-12-07 | International Business Machines Corporation | Process for improving sheet resistance of an integrated circuit device gate |
JPH06232152A (ja) * | 1993-01-29 | 1994-08-19 | Mitsubishi Electric Corp | 電界効果トランジスタ及びその製造方法 |
JPH08162634A (ja) * | 1994-12-08 | 1996-06-21 | Citizen Watch Co Ltd | 半導体装置の製造方法 |
US5960270A (en) * | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
-
1996
- 1996-12-16 FR FR9615436A patent/FR2757312B1/fr not_active Expired - Fee Related
-
1997
- 1997-12-15 EP EP97952059A patent/EP0944919A1/fr not_active Withdrawn
- 1997-12-15 JP JP52738898A patent/JP4560600B2/ja not_active Expired - Fee Related
- 1997-12-15 WO PCT/FR1997/002300 patent/WO1998027582A1/fr active Application Filing
- 1997-12-15 US US09/319,915 patent/US6346450B1/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
---|
See references of WO9827582A1 * |
Also Published As
Publication number | Publication date |
---|---|
JP4560600B2 (ja) | 2010-10-13 |
FR2757312B1 (fr) | 1999-01-08 |
WO1998027582A1 (fr) | 1998-06-25 |
FR2757312A1 (fr) | 1998-06-19 |
JP2001506807A (ja) | 2001-05-22 |
US6346450B1 (en) | 2002-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0944919A1 (fr) | Transistor mis a grille metallique auto-alignee et son procede de fabrication | |
EP0258141B1 (fr) | Circuit intégré MIS tel qu'une cellule de mémoire EPROM et son procédé de fabrication | |
EP1292974B1 (fr) | Procede de realisation d'un composant electronique a source, drain et grille auto-alignes, en architecture damascene. | |
EP1145300B1 (fr) | Procede de fabrication d'un transistor mis sur un substrat semi-conducteur | |
EP0420748B1 (fr) | Procédé de fabrication d'un circuit intégré MIS haute tension | |
FR2658951A1 (fr) | Procede de fabrication d'un circuit integre pour filiere analogique rapide utilisant des lignes d'interconnexions locales en siliciure. | |
FR2860920A1 (fr) | Procede de realisation de connexions conductrices de circuits integres, et circuit integre mettant en oeuvre des telles connexions | |
EP2323160A1 (fr) | Procédé de réalisation de transistors à effet de champs avec une contre-électrode et dispositif semi-conducteur | |
FR2823010A1 (fr) | Procede de fabrication d'un transistor vertical a grille isolee a quadruple canal de conduction, et circuit integre comportant un tel transistor | |
FR2823009A1 (fr) | Procede de fabrication d'un transistor vertical a grille isolee a faible recouvrement de la grille sur la source et sur le drain, et circuit integre comportant un tel transistor | |
EP3531444B1 (fr) | Circuit intégré comprenant un substrat équipé d'une région riche en pièges, et procédé de fabrication | |
EP0463972A1 (fr) | Procédé de fabrication d'un contact électrique sur un élément actif d'un circuit intégré MIS | |
FR2990295A1 (fr) | Procede de formation de contacts de grille, de source et de drain sur un transistor mos | |
EP1346405B1 (fr) | Procede de fabrication d'un ilot de matiere confine entre des electrodes, et applications aux transistors | |
EP0825641B1 (fr) | Procédé de réalistation d'un transistor à contacts auto-alignés | |
EP2120258B1 (fr) | Procédé de réalisation d'un transistor à source et drain métalliques | |
EP0190243B1 (fr) | Procede de fabrication d'un circuit integre de type mis | |
EP1463102A2 (fr) | Procédé de fabrication d'un transistor à grille métallique, et transistor correspondant | |
EP0990266A1 (fr) | Transistor hyperfrequence a structure quasi-autoalignee et son procede de fabrication | |
FR3000840A1 (fr) | Procede de realisation de contacts metalliques au sein d'un circuit integre, et circuit integre correspondant | |
WO1997050118A1 (fr) | Transistor et procede de realisation d'un transistor a contacts et a isolation de champ auto-alignes | |
FR3036846A1 (fr) | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant | |
EP3961689A1 (fr) | Procédé de fabrication de composants microélectroniques | |
WO2004057658A2 (fr) | Transistor mis a grille auto-alignee et son procede de fabrication | |
EP2259304B1 (fr) | Procédé de formation d'un niveau d'un circuit intégré par intégration tridimensionnelle séquentielle |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19990608 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE GB IT |
|
17Q | First examination report despatched |
Effective date: 20030423 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE |
|
17Q | First examination report despatched |
Effective date: 20030423 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20130702 |