Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
  • G05F3/02—Regulating voltage or current
  • G05F3/08—Regulating voltage or current wherein the variable is dc
  • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
  • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
  • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
  • G05F3/26—Current mirrors
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
  • G05F3/02—Regulating voltage or current
  • G05F3/08—Regulating voltage or current wherein the variable is dc
  • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
  • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
  • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
  • G05F3/26—Current mirrors
  • G05F3/265—Current mirrors using bipolar transistors only

Definitions

• the invention relates to a reference voltage source comprising: a first common terminal, a second common terminal, a first connection terminal, a second connection terminal, and an output terminal; a first resistor and a first transistor having a base and having a collector- emitter path connected in series between the first connection terminal and the second common terminal; a second resistor connected between the first common terminal and the second connection terminal; a diode-connected second transistor having a collector-emitter path connected between the second connection terminal and the second common terminal and having a base coupled to the base of the first transistor; a third resistor connected between the first common terminal and the first connection terminal; a fourth resistor connected between the first common terminal and the output terminal; a third transistor having a base, emitter and collector, which are coupled to the first connection terminal, the second common terminal, and the output terminal, respectively.
• Such a reference voltage source is known from International Application published under the Patent Cooperation Treaty WO 95/27938, particularly from Figure 11 of said publication.
• This known reference voltage source has a semiconductor junction arranged in series with the third resistor.
• the third transistor operates as a differential amplifier which makes the voltage difference between the first and the second connection terminal substantially zero.
• the second connection terminal may be regarded as the input terminal of a first current mirror which is formed by the first transistor, the second resistor and the second transistor, and whose output terminal is formed by the first connection terminal.
• the first current mirror has a current transfer with a positive TC caused by the voltage difference between the base-emitter junctions of the first and the second transistor, which voltage difference appears across the first resistor.
• the configuration with the differential amplifier, the second resistor and the semiconductor junction imposes a given ratio between the currents through the first and the second transistor.
• This configuration operates as a second current mirror whose current transfer has a negative TC.
• the combination of the two current mirrors results in a multiplication of two opposite temperature coefficients, the sum of the currents in the first or the second common terminal having a TC whose sign and value can be adjusted by a suitable choice of the first and the second resistor and of the ratio between the current densities in the first and the second transistor.
• the sum of the currents also flows through the fourth resistor.
• the reference voltage source of the type defined in the opening paragraph is characterized in that the reference voltage source further comprises a fourth transistor having a base, emitter and collector, the third transistor having its base coupled to the emitter of the fourth transistor, the fourth transistor having its base connected to the first connection terminal, and the fourth transistor having its collector coupled to the output terminal.
• the base-emitter junction of the fourth transistor performs the function of the semiconductor junction arranged in series with the third resistor in the known reference voltage source. This does not affect the basic operation of the configuration.
• the fourth transistor together with the third transistor forms a Darlington arrangement with a high current gain.
• the high current gain contributes to a lower output impedance of the reference voltage source.
• the reduced load of the first connection terminal leads to a more accurate result as regards the envisaged reference voltage and TC.
• An embodiment of the reference voltage source is characterized in that the fourth transistor has its emitter coupled to the second common terminal via a current-carrying element.
• the current-carrying element can be a current source or a resistor, by means of which bias current is supplied to the fourth transistor.
• the current-carrying element comprises a fifth transistor having a collector-emitter path connected between the emitter of the fourth transistor and the second common terminal, and having a base connected to the base of the second transistor.
• the fifth transistor operates as a current source with a current whose intensity is related to the currents through the second transistor.
• the base current of the fourth transistor is related to the sum of the base currents of the first and the second transistor, which results in an even further reduction of the spread in the generated reference voltage.
• Figure 1 shows a basic diagram of a prior-art reference voltage source
• Figure 2 shows a basic diagram of a prior-art reference voltage source
• Figure 3 shows a prior-art reference voltage source
• Figure 4 shows a prior-art reference voltage source
• Figure 5 shows an embodiment of a reference voltage source in accordance with the invention
• Figure 6 shows an embodiment of a reference voltage source in accordance with the invention.
• Figure 1 shows the general circuit diagram of a prior-art reference voltage source on which the invention is based.
• a first common terminal 2 There are provided a first common terminal 2, a second common terminal 4, a first connection terminal 6 and a second connection terminal 8.
• a first semiconductor junction 10 and a first resistor 12 are connected in series between the first connection terminal 6 and the second common terminal 4.
• a second semiconductor junction 14 is connected between the second connection terminal 8 and the second common terminal 4.
• a second resistor 16 is connected between the second connection terminal 8 and the first common terminal 2.
• a third semiconductor junction 18 in series with a third resistor 30 is connected between the first connection terminal 6 and the first common terminal 2.
• a differential amplifier 20 having a non-inverting input 22 and an inverting input 24, one of these inputs being coupled to the first connection terminal 6 and the other input being coupled to the second connection terminal 8, and having a output 26 coupled to the first common terminal 2.
• the second common terminal 4 is connected to a first supply terminal 32, which is grounded.
• a first current I flows from the first common terminal 2 to the second common terminal 4 via the second connection terminal 8.
• a second current I 2 flows from the first common terminal 2 to the second common terminal 4 via the first connection terminal 6.
• the sum current I, + I 2 is supplied to the first common terminal 2 by the output 26 of the differential amplifier 20 and flows to the first supply terminal 32 via the second common terminal 4.
• the input current to the non-inverting input 22 and the inverting input 24 may be ignored.
• the differential amplifier 20 makes the voltage difference between the first connection terminal 6 and the second connection terminal 8 very small.
• the value of the third resistor 30 is zero ohms.
• the voltage across the second resistor 16 is then equal to the junction voltage Vbej across the third semiconductor junction 18.
• the current I, through the second resistor 16 consequently complies with the equation:
• R 2 is the resistance value of the second resistor 16.
• the current I 2 complies with the following equation:
• Equation (2) is known per se. For further details reference is made to, for example, IEEE Journal of Solid States Circuits, Vol. SC-8, No. 3, June 1973, pp. 222-226, "A Precision Reference Voltage Source". Equation (1) may be regarded to express the effect of a first current mirror having a current transfer with a negative temperature coefficient (TC), since the junction voltage Vbe,, as is known, has a negative TC. Equation (2) represents the operation of a second current mirror having a positive TC.
• TC temperature coefficient
• the ratio I 2 /I has a positive TC. If the temperature T now increases the junction voltage Vbe, and hence the first current I, will decrease. However, the decrease of the first current I, is compensated by an increase in the second current I 2 owing to the positive TC in the ratio I 2 /I,. Thus, the sum current I, +I 2 can have a TC which is positive, or negative, or substantially zero.
• the second current I 2 with a positive TC flows through the third resistor 30 and produces across the third resistor 30 a voltage drop which also has a positive TC.
• the positive TC of this voltage drop reduces the negative TC of the junction voltage Vbe j .
• the third semiconductor junction 18 provides an additional degree of freedom, which can be used to realize a reference voltage source having a TC which can be chosen freely, within certain limits, and with a nominal voltage which can be chosen freely.
• the first semiconductor junction 10, the second semiconductor junction 14 and the third semiconductor junction 18 are shown as diodes but they may also be formed by transistors each having an interconnected collector and base.
• the effect of the first semiconductor junction 10, the first resistor 12 and the second semiconductor junction 14 can also be obtained in an alternative manner.
• Figure 2 shows such an alternative for the arrangement of Figure 1.
• the first semiconductor junction 10 is the base-emitter junction of a first transistor 34 whose collector is coupled to the first connection terminal 6 and whose emitter is connected to the first resistor 12;
• the second semiconductor junction 14 is the base-emitter junction of a diode-connected second transistor 36 whose base is connected to the base of the first transistor 34 and whose collector is coupled to the second connection terminal 8.
• the voltage on the output 26 is now found to be equal to the sum of the junction voltage Vbe, 4 of the second semiconductor junction 14, the voltage drop Ur 30 across the third resistor 30, the junction voltage Vbe lft of the third semiconductor junction 18 and the voltage drop Ur 58 across the fourth resistor 58.
• the current I 2 which as already stated has a positive TC, flows through the third resistor 30.
• the sum current I ⁇ +I 2 which also has a positive TC, flows through the fourth resistor 58.
• the sum voltage across the third resistor 30 and the fourth resistor 58 can thus have a positive TC, which compensates for the negative TC of the two semiconductor junctions.
• a voltage is available on the output 26 with a TC which is substantially zero and with a magnitude which can be determined by the choice of the resistors 12, 16, 30 and 58.
• the differential amplifier 20 in Figure 3 can be simplified considerably when it is based on the variant shown in Figure 2.
• the result is shown in Figure 4.
• the differential amplifier 20 now comprises a third transistor 70, whose emitter, base and collector are connected to the first supply terminal 32, the first connection terminal 6 and the non-inverting output 26, respectively.
• the output 26 is connected to a second supply terminal 54 via a fifth resistor 72.
• a fifth resistor 72 instead of a fifth resistor it is also possible to use a current source.
• the base of the third transistor 70 functions as the inverting input.
• the emitter of the third transistor 70 functions as the non-inverting input, which is coupled to the second connection terminal 8 via the base-emitter junction of the second transistor 36 in order to compensate for the base-emitter offset voltage of the third transistor 70.
• FIG. 5 shows a reference voltage source in accordance with the invention.
• the function of the semiconductor junction 18 is now performed by the base- emitter junction of a fourth transistor 80 having its base connected to the first connection terminal 6, having its emitter connected to the base of the third transistor 70, and having its collector connected to the output 26.
• the semiconductor junction 18 is dispensed with and the third resistor 30 is connected directly between the first connection terminal 6 and the first common terminal 2.
• the voltage on the emitter of the fourth transistor 80 is equal to the voltage on the second connection terminal 8. Therefore, the above analysis based on two non-linear current mirrors remains valid.
• the third transistor 70 and the fourth transistor 80 together form a Darlington transistor having a high current gain.
• the load on the first connection terminal 6 is reduced substantially, so that the accuracy of the generated reference voltage increases.
• the output impedance on the output terminal 26 is reduced, as a result of which the reference voltage V z is less dependent on variations in the current I 2 which flows in the output 26.
• the reference voltage V z can be chosen freely by a suitable choice of the resistances.
• the lower limit is approximately 2.7 V, in which case the value of the fourth resistor 58 may approximate to zero.
• the upper limit is dictated by the maximum permissible collector-emitter voltage of the third transistor 70.
• the quiescent current of the fourth transistor 80 can be fixed by means of an optional current source 82 connected between the emitter of the fourth transistor 80 and the first supply terminal 32. It is to be noted that for this purpose a resistor can be used instead of a current source.
• Figure 6 shows an embodiment in which the current source comprises a fifth transistor 84, having its base, emitter and collector respectively connected to the base of the second transistor 36, the first supply terminal 32 and the emitter of the fourth transistor 80. This results in a well-defined bias current through the fourth transistor 80.
• the TC is approximately zero at the reference temperature T ref . It is obvious that the reference temperature at which the TC is approximately zero can be given another value, for example 27 °C.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Nonlinear Science (AREA)
• Electromagnetism (AREA)
• General Physics & Mathematics (AREA)
• Radar, Positioning & Navigation (AREA)
• Automation & Control Theory (AREA)
• Control Of Electrical Variables (AREA)
• Amplifiers (AREA)

Priority Applications (1)

Applications Claiming Priority (4)

Publications (1)

Family

ID=8223725

Family Applications (1)

Country Status (5)

Families Citing this family (9)

Family Cites Families (9)

• 1997
  • 1997-01-31 WO PCT/IB1997/000064 patent/WO1997032245A1/en not_active Application Discontinuation
  • 1997-01-31 EP EP97900705A patent/EP0856168A1/en not_active Ceased
  • 1997-01-31 KR KR1019970707725A patent/KR19990008200A/ko not_active Application Discontinuation
  • 1997-01-31 JP JP53074097A patent/JP4031043B2/ja not_active Expired - Fee Related
  • 1997-02-28 US US08/808,592 patent/US5808507A/en not_active Expired - Lifetime

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events