EP0743586B1 - Circuit intégré dans lequel certains composants fonctionnels sont amenés à travailler avec une même caractéristique de fonctionnement - Google Patents
Circuit intégré dans lequel certains composants fonctionnels sont amenés à travailler avec une même caractéristique de fonctionnement Download PDFInfo
- Publication number
- EP0743586B1 EP0743586B1 EP96401074A EP96401074A EP0743586B1 EP 0743586 B1 EP0743586 B1 EP 0743586B1 EP 96401074 A EP96401074 A EP 96401074A EP 96401074 A EP96401074 A EP 96401074A EP 0743586 B1 EP0743586 B1 EP 0743586B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- integrated circuit
- ref
- current
- transistors
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
Definitions
- the present invention relates to integrated circuits in which some or all of the components or groups of functional components must work in the same conditions to ensure the proper functioning of the circuit in general.
- a technique currently used to impose identical operating characteristics to transistors distant from an integrated circuit consists of their impose a parameter (for example a current) and we set a quantity determining the characteristic (for example the grid voltage).
- This method has the disadvantage that the control current cannot be used simultaneously by the two transistors and then you have to order alternately. Therefore the transistors do not are available to perform their function assigned in the circuit only when they are not in regulatory regime.
- the number of transistors that we can thus work under the same conditions is necessarily limited, because otherwise the frequency with which control current is distributed sequentially will become too high vis-à-vis that of the useful signal to treat.
- the invention aims to provide an integrated circuit comprising means for imposing on a plurality of its components or groups of components the same characteristic of operation, this circuit being devoid of disadvantages of the prior art briefly described above.
- FIG. 1 a general diagram is shown very simplified of an integrated circuit comprising a system according to the invention.
- the integrated circuit symbolized by rectangle 1 has a plurality of functional units 2-1 to 2-n distributed on the integrated circuit and which one supposes that they must all work with the same characteristic of operation.
- any functional assembly which may include one or more chips, the functional units being able to be components or groups of components of any kind such as transistors, diodes, groups of transistors, diode groups, circuit parts composed of assemblies of such components etc.
- Figure 1 shows a distribution of its functional units, this is not a limiting element of the concept of the invention, these units can be installed in the circuit only in according to the specific needs and tasks that the integrated circuit must accomplish.
- the integrated circuit includes a central setpoint generator 3 located at a location suitable for this circuit and intended to develop a signal setpoint according to which the characteristic of functioning of the functional units will be developed.
- This generator has n outputs connected to as many lines 4-1 to 4-n which are respectively connected to cells adjustment local 5-1 to 5-n. These cells are respectively associated with functional units 2-1 to 2-n by being placed near their respective unit.
- the setpoint information generated in the generator central 3 can be applied simultaneously to cells adjustment 5-1 to 5-n, but according to a characteristic particular of the invention, it can also be sent sequentially to these cells, in which case the central generator 3 includes a sequencer 6 shown in dotted in the rectangle which symbolizes the generator instruction 3.
- This variant of the invention is especially useful when the setpoint information cannot be used without be altered by several adjustment cells at the same time.
- threshold voltages of the transistors of an MOS integrated circuit are not the same throughout the circuit.
- the first example described therefore aims to impose on all the transistors of the circuit the same so-called threshold voltage "related".
- the characteristic to be imposed on the transistors of the circuit is this apparent threshold voltage.
- the adjustment of the tensions of threshold of all the transistors at the same value allows simplified exchange of analog information between different parts of the integrated circuit, this information thus being interpreted in the same way all over the circuit.
- I D k (( V G - V YOUR ) 2 in which I D is the drain current of the transistor, V G its gate voltage and V TA its apparent threshold voltage as long as V G >> V TA , that is to say when the transistor works in strong inversion .
- C D is the depletion capacity of the transistor and C i its oxide capacity.
- this figure does not represent that the setpoint generator 3, as well as a single transistor useful 2-n with its associated local 5-n adjustment cell.
- the setpoint generator 3 shown in FIG. 2 is intended for n-type transistors. It comprises two transistors MG1 and MG2, the sources of which are connected to a negative supply conductor of voltage V GM . Their drains are connected to their respective grids, and to the drains of two respective transistors MG3 and MG4 mounted in current mirror. The boxes of the transistors MG1 and MG2 are connected to a supply terminal V GW . The gates of the transistors MG3 and MG4 are connected to a bias voltage terminal V GI , while their sources are connected to a positive supply voltage V GP .
- the voltages V G1 and V G2 can constitute setpoint information which can be used in the local adjustment cell 5-n to determine, for the useful transistor 2-n which is associated with it, an apparent threshold voltage V Identical TA using the box voltage V W as an adjustment parameter, the actual threshold voltages of all the useful transistors being able to be different from one cell to another.
- the local adjustment cell 5-n comprises a current mirror formed by the transistors MC3 and MC4 whose widths are in a ratio K M. This is relatively easy to achieve even if the distance separating the setpoint generator 3 from this local cell is relatively large.
- the sources of these transistors MC3 and MC4 are connected to a supply voltage V UP , while their drains are respectively connected to the drains of two transistors MC1 and MC2, the sources of which are connected to a voltage V UM .
- the gate of transistor MC3 is connected to its drain.
- the gates of the transistors MC1 and MC2 are connected respectively to the voltages V G1 and V G2 coming from the setpoint generator 3.
- the common point of the transistors MC2 and MC4 is connected at the input of an amplifier A and at a terminal of a capacitor C.
- the output of amplifier A is connected to the boxes of transistors MC1, MC2 and MU.
- the transistors MC1 and MC2 operate in strong inversion and generate respective currents determined by relation (1) above.
- the current mirror formed by the transistors MC3 and MC4 makes a copy of the current generated by the transistor MC1 by multiplying it by the constant K M.
- the capacitor C integrates the difference between the current passing through the transistor MC4 and the current passing through MC2.
- the amplifier transmits the corresponding value on the wells of the transistors MC1 and MC2 and also on that of the useful transistor MU. The regime stabilizes when the difference in these currents is zero. Under these conditions, the transistor MU has an apparent threshold voltage which is identical to that of the transistors MG1 and MG2 of the reference generator.
- FIG. 3 a central reference generator 3A has been shown which, in this case, produces a reference voltage V ref and a reference current I ref as a reference. As it is a question here of transmitting a current setpoint, it is necessary to distribute this reference current I ref sequentially.
- the setpoint generator 3A comprises a voltage source ST which is connected to the gate of a transistor MG5 and to an output of the generator delivering the reference voltage V ref .
- the drain of transistor MG5 is connected to a current mirror formed by transistors MG6 and MG7, the latter delivering the reference current I ref .
- the local adjustment cell 5A-n comprises a transistor MC5 whose gate receives the voltage V ref . Its drain is connected to two switches S1 and S2 controlled by the sequencer 6.
- the switch S1 receives the reference current I ref from the reference generator 3A.
- Switch S2 is connected to the common point of an AC capacitor and an AA amplifier. The output of the latter is connected to the wells of the transistors MC5 and MU (2A-n).
- the transistor useful can continue to function whether it is in operation adjustment or not.
- the useful components do not are not transistors, but diodes or photodiodes, the latter being, for example, part a network of detectors or the like. It can then be important that all these diodes have the same current of flight. However, we know that the leakage current of a diode is strongly dependent on temperature.
- the central reference generator 3B generates, for example by means of the assembly shown in FIG. 3 at 3A, a reference current I ref which is distributed to the local adjustment cells such as cell 5B-n, by means of the sequencer 6 .
- the local adjustment cell 5B-n comprises a diode P1 which is connected to the switches S1 and S2, these being closed in adjustment mode.
- Switch S2 is also connected to the common point of a capacitor CB and the input of an amplifier AB.
- the output of the latter is connected to a heat dissipation resistor RT placed near the diode P1 and the useful diode P2 (2B-n).
- a current I C is therefore sent as an adjustment value in this dissipating resistor RT.
- Diode P2 (and possibly other diodes located nearby) will thus receive (have) a caloric intake which determines the same leakage current for all the diodes.
- the current flows through the dissipating resistor RT as long as the current in the diode P1 is not equal to the reference current I ref .
- the sequencer 6 makes it possible to serve other similar heating assemblies distributed in the array of photodiodes.
- the local adjustment units must be thermally isolated from each other.
- the CB capacitor acts as memory and retains the setpoint between two addresses made by the sequencer 6.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
- des moyens formant un générateur de référence central destiné à élaborer au moins une information de consigne qui détermine la caractéristique de fonctionnement devant être commune à tous les composants fonctionnels du circuit;
- des moyens pour distribuer l'information de consigne parmi une pluralité d'unités du circuit comprenant chacune au moins un desdits composants fonctionnels;
- chacune desdites unités comprenant des moyens locaux d'ajustement connectés pour recevoir ladite information de consigne et pour élaborer une valeur d'ajustement;
- des moyens de correction dans chaque unité pour ajuster la caractéristique de fonctionnement d'un dispositif prévu dans lesdits moyens locaux d'ajustement, en fonction de ladite valeur d'ajustement, ledit dispositif étant placé à proximité du ou des composant(s) fonctionnel(s) et configuré de telle sorte que la caractéristique de fonctionnement qui lui est ainsi imposée, s'impose également au(x)dit(s) composant(s) fonctionnel(s);
- des moyens de correction dans chaque unité pour ajuster la caractéristique de fonctionnement de son ou ses composant(s) fonctionnel(s) en fonction de ladite valeur d'ajustement.
- la figure 1 est un schéma très simplifié d'un circuit intégré pour mettre en évidence les caractéristiques essentielles de l'invention; et
- les figures 2 à 4 montrent trois exemples d'application de l'invention.
Claims (12)
- Circuit intégré caractérisé en ce qu'il comprend:des moyens formant un générateur central de référence (3, 3A, 3B) destiné à élaborer au moins une information de consigne (VG1, VG2; Iref, Vref; Iref) qui détermine la caractéristique de fonctionnement devant être commune à au moins une pluralité des composants fonctionnels du circuit;des moyens (4-1 à 4-n; 6) pour distribuer l'information de consigne parmi au moins une pluralité d'unités du circuit, comprenant chacune au moins un desdits composants fonctionnels (2-n; 2A-n; 2B-n);chacune desdites unités comprenant des moyens locaux d'ajustement (5-n; 5A-n; 5B-n) connectés pour recevoir ladite information de consigne (VG1, VG2; Iref, Vref; Iref) et pour élaborer une valeur d'ajustement (VW, IC);des moyens de correction (C, A; CA, AA; CB, AB) dans chaque unité pour ajuster la caractéristique de fonctionnement d'un dispositif (MC1, MC2; MC5; P1) prévu dans lesdits moyens locaux d'ajustement (5-n; 5A-n; 5B-n), en fonction de ladite valeur d'ajustement, ledit dispositif étant placé à proximité du ou des composant(s) fonctionnel(s) et configuré de telle sorte que la caractéristique de fonctionnement qui lui est ainsi imposée, s'impose également au(x)dit(s) composant(s) fonctionnel(s) (2-n; 2A-n; 2B-n).
- Circuit intégré suivant la revendication 1, comportant des transistors MOS caractérisé en ce que ladite caractéristique de fonctionnement est la tension de seuil apparente (VTA) d'au moins certains de ses transistors MOS (2-1 à 2-n; figure 2).
- Circuit intégré suivant la revendication 1, comportant des transistors MOS, caractérisé en ce que ladite caractéristique de fonctionnement est un point de travail prédéterminé de la courbe courant de drain/tension de grille d'au moins certains de ces transistors MOS (2A-n; figure 3).
- Circuit intégré suivant la revendication 2, comportant des diodes ou des photodiodes, caractérisé en ce que ladite caractéristique de fonctionnement est le courant de fuite desdites diodes (P2; figure 4).
- Circuit intégré suivant l'une quelconque des revendications 2 et 3 prises ensemble, caractérisé en ce que ladite valeur d'ajustement est la tension de caisson (VW) d'au moins certains desdits transistors MOS (2-1 à 2-n).
- Circuit intégré suivant les revendications 2 et 5 prises ensemble, caractérisé en ce que ledit générateur central de référence (3) comporte des moyens (MG2, MG4) pour établir un premier rapport de deux courants (KM) représentatif de la valeur de ladite tension de seuil apparente (VTA) souhaitée et des moyens (MG1, MG2) pour, en fonction d'une valeur de tension de caisson prédéterminée (VGW), convertir ce premier rapport de courants en une paire de tensions (VG1, VG2) formant ladite information de consigne, et en ce que lesdits moyens locaux d'ajustement (5-1 à 5-n) comprennent des moyens (MC3, MC4) pour établir localement un second rapport de courants et des moyens (MC1, MC2, C, A) pour engendrer en fonction de ladite information de consigne, un signal de modification de la tension de caisson (VUW) du ou desdits composants fonctionnels (2-1 à 2-n) associés auxdits moyens d'ajustement local considérés (5-1 à 5-n), pour ajuster ledit second rapport de courants audit premier rapport de courants.
- Circuit intégré suivant la revendication 6, caractérisé en ce queledit générateur central de référence (3) comporte un miroir de courant formé de deux transistors MOS (MG3, MG4) dont les largeurs ont ledit premier rapport de courants et deux autres transistors MOS (MC1, MC2) montés respectivement en série avec les transistors du miroir de courant et dont la tension de caisson (VGW) présente ladite valeur prédéterminée de tension de caisson, lesdits deux autres transistors (MG1, MG2) étant agencés pour fonctionner en forte inversion et fournir ladite information de consigne (VG1, VG2) sur leurs grilles, et en ce quelesdits moyens locaux d'ajustement (5-1 à 5-n) comprennent un montage identique à celui dudit générateur central de référence (3), le point de jonction entre l'un (MC4) des transistors de leur miroir de courant et ledit autre transistor (MC2) correspondant étant raccordé à un amplificateur (A) fournissant ladite valeur d'ajustement (VUW), la sortie de cet amplificateur étant raccordée aux caissons desdits autres transistors (MC1, MC2) de ces moyens locaux d'ajustement et à celui du composant fonctionnel (MU) associé à ces moyens.
- Circuit intégré suivant la revendication 3 et 5 prises ensemble, caractérisé en ce que ledit générateur central de référence (3A) comporte une source de tension (ST) délivrant une tension de référence (Vref) et une source de courant (MG5, MG6 et MG7) délivrant un courant de référence (Iref), en ce que lesdits moyens locaux d'ajustement (5A-n) comprennent un transistor (MC5) connecté pour recevoir ladite tension de référence sur sa grille, et un amplificateur (AA) connecté pour amplifier la différence entre ledit courant de référence et le courant traversant ce transistor (MC5), la sortie dudit amplificateur (AA) étant connectée au caisson de ce dernier et celui dudit composant fonctionnel (MU) pour leur fournir ladite valeur d'ajustement (VW).
- Circuit intégré suivant la revendication 8, caractérisé en ce qu'il comprend un séquenceur (6) pour envoyer ledit courant de référence (Iref) tour à tour vers lesdits moyens locaux d'ajustement, et en ce que lesdits moyens locaux d'ajustement comprennent des moyens de mémoire (CA) pour conserver ladite valeur d'ajustement (VW) entre deux envois dudit courant de référence à ces moyens.
- Circuit intégré suivant la revendication 4, caractérisé en ce que ladite valeur d'ajustement est la température (T) dudit circuit.
- Circuit intégré suivant la revendication 10, caractérisé en ce que ledit générateur central de référence (3B) comprend une source de courant de référence (Iref), et en ce que lesdits moyens locaux d'ajustement comprennent une diode de référence (P1), ainsi qu'un amplificateur (AB) pour amplifier la différence entre le courant de référence et le courant circulant dans ladite diode (P1), la sortie dudit amplificateur (AB) étant connectée à un composant dissipateur de chaleur (RT) placé près de ladite diode (P1) et de la diode (P2)) qui forme ledit composant fonctionnel.
- Circuit intégré suivant la revendication 11, caractérisé en ce qu'il comporte un séquenceur (6) pour envoyer ledit courant de référence (Iref) tour à tour auxdits moyens locaux d'ajustement (5B-n).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9505920A FR2734378B1 (fr) | 1995-05-17 | 1995-05-17 | Circuit integre dans lequel certains composants fonctionnels sont amenes a travailler avec une meme caracteristique de fonctionnement |
FR9505920 | 1995-05-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0743586A1 EP0743586A1 (fr) | 1996-11-20 |
EP0743586B1 true EP0743586B1 (fr) | 2000-08-02 |
Family
ID=9479129
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96401074A Expired - Lifetime EP0743586B1 (fr) | 1995-05-17 | 1996-05-15 | Circuit intégré dans lequel certains composants fonctionnels sont amenés à travailler avec une même caractéristique de fonctionnement |
Country Status (4)
Country | Link |
---|---|
US (1) | US5739718A (fr) |
EP (1) | EP0743586B1 (fr) |
DE (1) | DE69609563D1 (fr) |
FR (1) | FR2734378B1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3635768B2 (ja) * | 1996-03-05 | 2005-04-06 | ヤマハ株式会社 | 半導体集積回路 |
JPH10135756A (ja) * | 1996-10-31 | 1998-05-22 | Mitsumi Electric Co Ltd | 回路体における回路特性の調整方法 |
US20040217934A1 (en) * | 2003-04-30 | 2004-11-04 | Jin-Seok Yang | Driving circuit of flat panel display device |
US6972989B2 (en) * | 2003-10-10 | 2005-12-06 | Infincon Technologies Ag | Reference current distribution in MRAM devices |
FR2957161B1 (fr) * | 2010-03-02 | 2012-11-16 | St Microelectronics Rousset | Circuit interne de tension d'alimentation d'un circuit integre |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL8001558A (nl) * | 1980-03-17 | 1981-10-16 | Philips Nv | Stroomstabilisator opgebouwd met veldeffekttransistor van het verrijkingstype. |
US4471292A (en) * | 1982-11-10 | 1984-09-11 | Texas Instruments Incorporated | MOS Current mirror with high impedance output |
US4814644A (en) * | 1985-01-29 | 1989-03-21 | K. Ushiku & Co. | Basic circuitry particularly for construction of multivalued logic systems |
EP0342814B1 (fr) * | 1988-05-20 | 1995-02-08 | Mitsubishi Denki Kabushiki Kaisha | Circuit intégré MOS pour commande de diodes électroluminescentes |
NL9001018A (nl) * | 1990-04-27 | 1991-11-18 | Philips Nv | Referentiegenerator. |
US5117130A (en) * | 1990-06-01 | 1992-05-26 | At&T Bell Laboratories | Integrated circuits which compensate for local conditions |
US5157285A (en) * | 1991-08-30 | 1992-10-20 | Allen Michael J | Low noise, temperature-compensated, and process-compensated current and voltage control circuits |
US5461338A (en) * | 1992-04-17 | 1995-10-24 | Nec Corporation | Semiconductor integrated circuit incorporated with substrate bias control circuit |
US5397934A (en) * | 1993-04-05 | 1995-03-14 | National Semiconductor Corporation | Apparatus and method for adjusting the threshold voltage of MOS transistors |
GB9320991D0 (en) * | 1993-10-12 | 1993-12-01 | Philips Electronics Uk Ltd | A circuit for providing a current source |
FR2717918B1 (fr) * | 1994-03-25 | 1996-05-24 | Suisse Electronique Microtech | Circuit pour contrôler les tensions entre caisson et sources des transistors mos et système d'asservissement du rapport entre les courants dynamique et statique d'un circuit logique mos. |
-
1995
- 1995-05-17 FR FR9505920A patent/FR2734378B1/fr not_active Expired - Lifetime
-
1996
- 1996-05-15 EP EP96401074A patent/EP0743586B1/fr not_active Expired - Lifetime
- 1996-05-15 DE DE69609563T patent/DE69609563D1/de not_active Expired - Lifetime
- 1996-05-17 US US08/649,478 patent/US5739718A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2734378B1 (fr) | 1997-07-04 |
DE69609563D1 (de) | 2000-09-07 |
EP0743586A1 (fr) | 1996-11-20 |
FR2734378A1 (fr) | 1996-11-22 |
US5739718A (en) | 1998-04-14 |
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