EP0739552A1 - RECEPTEUR ET EXCITATEUR DE MODE COURANT BiCMOS - Google Patents

RECEPTEUR ET EXCITATEUR DE MODE COURANT BiCMOS

Info

Publication number
EP0739552A1
EP0739552A1 EP94915426A EP94915426A EP0739552A1 EP 0739552 A1 EP0739552 A1 EP 0739552A1 EP 94915426 A EP94915426 A EP 94915426A EP 94915426 A EP94915426 A EP 94915426A EP 0739552 A1 EP0739552 A1 EP 0739552A1
Authority
EP
European Patent Office
Prior art keywords
peak
differential signal
coupled
pair
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94915426A
Other languages
German (de)
English (en)
Inventor
Ban Pak Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microunity Systems Engineering Inc
Original Assignee
Microunity Systems Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microunity Systems Engineering Inc filed Critical Microunity Systems Engineering Inc
Publication of EP0739552A1 publication Critical patent/EP0739552A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H03K19/017554—Coupling arrangements; Impedance matching circuits using a combination of bipolar and field effect transistors [BIFET]
    • H03K19/017563—Coupling arrangements; Impedance matching circuits using a combination of bipolar and field effect transistors [BIFET] with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01825—Coupling arrangements, impedance matching circuits
    • H03K19/01831—Coupling arrangements, impedance matching circuits with at least one differential stage

Definitions

  • the present invention relates to the field of circuit design, and specifically to transmission of differential signals within an integrated circuit.
  • a digital signal In digital logic circuits information in the form of digital signals is processed so as to cause the logic circuit to perform a specific task or function.
  • a digital signal generally has two states; a high level state and a low level state. Each logic state corresponds to some voltage potential. In other words the high logic state corresponds to a first voltage potential and the low state corresponds to a second voltage potential. The voltage potentials are determined by the design of the logic circuit.
  • a digital signal is also characterized by its peak-to-peak voltage.
  • the peak-to-peak voltage of a given digital signal is equal to its maximum signal voltage (i.e., the voltage potential corresponding to the high logic state) minus its minimum signal voltage (i.e., the voltage potential corresponding to the low logic state).
  • a digital signal and the inverse of that digital signal (referred to as a differential signal) to be utilized.
  • a differential signal typically, to transmit a differential signal from one part of an integrated circuit (IC) to another you need a transmitter to drive two interconnect lines with the differential signal and a receiver to detect the signals on these lines.
  • the traditional method for differential signal transmission utilizes high power buffers for driving the interconnect lines.
  • the buffers (also referred to as line drivers), are differential amplifiers comprising two emitter-coupled transistors each having a resistive load coupled between their collector and a supply voltage. Their emitters are coupled to a current source.
  • a signal and its inverse is coupled to each of the bases of the emitter-coupled transistors.
  • the differential amplifier compares the two input base signals. Depending on whether one of the base signals is less than or greater than the other, the differential amplifier steers the current established by the current source through one of the emitter-coupled transistors. This current flow causes a corresponding voltage drop across only one of the load resistors.
  • the collector of that transistor remains at approximately ground potential.
  • the output of the differential amplifier is typically taken at the collector of each of the emitter- coupled transistors.
  • one collector is always at a voltage potential corresponding to a low logic level and the other collector is at a voltage potential corresponding to a high logic level.
  • the differential voltage signal outputted by the collectors is coupled to a pair of interconnect lines for transmission to receivers in other parts of the IC.
  • the receivers comprise a pair of emitter coupled transistors each having a resistive load coupled between their collector and a supply voltage.
  • a current source is coupled to their common emitters.
  • the transmitted differential signal is coupled between the bases of the emitter-coupled pair and the output of the receiver is taken at their collectors.
  • the receiver in response to voltage changes on the interconnect lines, outputs a corresponding differential signal. Since this type of transmission system functions such that it detects changes in voltage in the transmitted signal, it is referred to as a voltage mode transmission system.
  • the amount of delay of a transmitted signal due to line capacitance is also determined by the signals peak-to-peak voltage. For a given line having a specific associate line capacitance and resistive loading, longer delays occur for transmitted signals having relatively high peak-to-peak voltages than for lower voltages. For instance, a longer transition delay occurs on a specific interconnect line for a 700 mV peak-to-peak signal than a 20 mV peak-to-peak signal having the same current. The reason for this is because it takes a longer time for a signal to reach a 700 mV peak voltage as opposed to a 20 mV peak voltage. Thus, transmitting signals having low peak-to-peak voltages equates to reduced delay times.
  • One type of transmission system that reduces delays by reducing peak-to-peak voltages operates in a manner in which differential current changes on the interconnect lines are detected instead of differential voltage changes.
  • the signals are referred to as current mode signals; (as opposed to a system that detects voltage changes in voltage mode signals).
  • current mode signals instead of driving interconnect lines with differential voltage mode signals having relatively large changes in voltage, interconnect lines are driven with current mode signals having relatively large differential changes in current and small peak-to-peak voltage changes. Since peak voltages are reduced, so are the associated transmission delays.
  • the current mode driver is basically the same as the voltage mode line driver except that the load resistors coupled to the collectors of the emitter-coupled transistors are eliminated. Specifically, the collectors of the emitter-coupled pair are coupled directly to the interconnect lines. Thus, instead of a differential voltage being developed across the interconnect lines, a reference current is routed through either one or the other interconnect line. This causes a differential current signal to be developed across the interconnect lines. This differential current signal is detected by the current mode receiver.
  • One prior art current mode receiver converts current mode signals into differential voltage mode signals while clamping the interconnect lines to a voltage of approximately 60 mV.
  • the cascode clamp comprises two transistors each having their bases coupled to a reference voltage, VDD.
  • a resistor is also coupled between each of their collectors and VDD.
  • Each of the differential interconnect lines are coupled to one of the emitters of the cascoded pair.
  • the present invention is a circuit design for transmitting current mode signals.
  • the current mode transmission system of the present invention utilizes a differential amplifier feedback circuit to clamp peak-to-peak voltages on interconnect lines while providing output signals peak voltage swings compatible with ECL logic. As a result, transmission delays associated with line capacitance are significantly reduced.
  • the present invention is a current mode signal transmission circuit.
  • the transmission circuit includes a current mode driver and receiver.
  • the receiver utilizes feedback to clamp peak-to-peak voltages of signals on differential interconnect lines while outputting signals having peak-to-peak swings compatible with ECL circuit design.
  • the current mode driver of the present invention includes first pair of emitter-coupled transistors.
  • the emitters of this first pair of transistors are coupled to a current source.
  • the current source is an n-type metal oxide silicon (NMOS) device having its gate coupled to a reference voltage.
  • NMOS n-type metal oxide silicon
  • the input differential signal to be transmitted is coupled to the bases of the emitter-coupled pair which causes a current mode differential signal to be established across the collectors of the emitter coupled pair.
  • the collectors are coupled to a pair of interconnect lines.
  • This current mode differential signal is transmitted along the interconnect lines to the current mode receiver of the present invention.
  • the receiver converts the current mode signal to a voltage mode signal having a greater peak-to-peak voltage swing than the current mode signal.
  • the receiver includes a second pair of transistors. Each of the emitters of the second pair of transistors are coupled to one of the interconnect lines.
  • One embodiment of the present invention also includes MOS current sources coupled to each of the emitters of the second pair of transistors to bias them in their low resistance operating range.
  • the bases of the third and fourth transistors are coupled to a feedback circuit.
  • the feedback circuit is a differential amplifier having a third pair of emitter-coupled transistors, a current source, and a pair of load resistors.
  • the differential amplifier's function is to drive the bases of the second pair of transistors in the opposite direction from which their corresponding emitters are moving. In this way, the interconnect lines are clamped to a voltage swing that is much less than the swing the receiver is trying to achieve.
  • a single current mode driver is coupled to a single current mode receiver.
  • the output of the receiver is taken at the collectors of the second pair of transistors.
  • multiple drivers are coupled to a single receiver.
  • the output of the receiver is at the collectors of the third pair of emitter-coupled transistors.
  • Figure 1 is a circuit schematic diagram which illustrates the current mode driver and receiver of the present invention.
  • Figure 2 is another embodiment of the present invention having multiple drivers coupled to a single receiver.
  • FIG. 1 shows a circuit schematic diagram of one embodiment of the present invention.
  • Matched NPN bipolar transistors Ql and Q2 and NMOS transistor Ml comprise the current mode line driver portion of the present invention.
  • the emitters of Ql and Q2 are coupled to the drain of Ml.
  • the source of Ml is coupled to a first supply voltage referred to as VSS.
  • VSS is equal to -3 volts, however a 5 volt VSS is also acceptable.
  • the gate of Ml is coupled to reference voltage VREF. VREF biases Ml to function as a constant current source such that Ml supplies a current equal to IREF.
  • An input differential signal comprising IN and IN/ is coupled to the bases of Ql and Q2. It should be noted that IN/ is the inverse signal of IN.
  • the input differential signal causes either Ql or Q2 to be biased on and the other to be biased off.
  • the current supplied by current source Ml is routed through either Ql or Q2 to either interconnect line 10 or 11.
  • the current through one of the interconnect lines is zero and the current through the other interconnect line is IREF.
  • Interconnect lines 10 and 11 are coupled to the current mode receiver of the present invention. It should be noted that although interconnect lines 10 and 11 are represented as relatively short lines they can be any length.
  • the current mode receiver comprises a cascode clamp portion and a feedback portion.
  • the cascode clamp portion of the receiver includes matched NPN transistors Q5 and Q6, their resistive loads R3 and R4, and current source biased NMOS devices M2 and M4.
  • the feedback portion includes matched transistors Q3 and Q4, their resistive loads Rl and R2, and current source biased NMOS device M3.
  • VREF provides the bias voltage to the gates of M2, M3 and M4. These transistors are sized so they each provide the desired current.
  • the differential amplifier portion of the receiver functions such that when the base-to-emitter voltages of Q3 and Q4 are equal, the current supplied by M3, i.e., 13, is split equally between Q3 and Q4.
  • the base-to- emitter voltage for one of the transistors is greater than the other, more current will be flowing through the transistor with the higher base-to-emitter voltage. Since more current is flowing in one branch and less current is flowing through the other, the voltage at one of the collectors of the emitter-coupled transistors will begin to fall while the other rises. In other words, a differential voltage signal is developed across the collectors of Q3 and Q4.
  • Node 1 increases and node 3 decreases, as node 2 decreases until the delta ⁇ of Q6 and Q5 is such that the above equation is satisfied.
  • node 2 (the emitter of Q5) tries to approach a voltage potential equal to [(VT) x In(I5/I6)] below node 4 (the emitter of Q6).
  • node 2 never reaches that potential.
  • the potentials on node 1 and 3 contribute to part of the delta(vbe) between Q5 and Q6.
  • Resistors Rl and R2 are chosen so that they supply the appropriate potential to the bases Q5 and Q6 to achieve the minimum stable differential voltage at nodes 2 and 4.
  • the peak-to-peak voltage of interconnect line 10 is clamped to a voltage potential less than (VT) x In(I5/I6), (i.e., less than 60 mV at 25 degrees Celsius for an NPN cascode pair clamp).
  • the magnitude of the voltage swing on nodes 1 and 3 is much higher than that of nodes 2 and 4.
  • nodes 1 and 3 are generally low capacitance short interconnect lines relative to interconnect lines 10 and 11, signal delays on these lines are minimal.
  • the present invention reduces delays by reducing the voltage swing of the differential signals sent along logic circuit interconnect lines 10 and 11.
  • the outputs of the receiver, OUT and OUT/ are taken at the collectors of Q5 and Q6.
  • OUT/ is equal to VDD - (R3 x IREF) and OUT is VDD-(R4 x 14). Since IREF is much greater than 14, OUT is high and OUT/ is low.
  • Resistors R3 and R4 are chosen so that the receiver outputs the desired peak-to-peak voltage.
  • the output of the receiver needs to have a peak-to-peak swing that interfaces with subsequent logic gates. Consequently, the selected magnitude of the peak-to-peak voltages, (and R3 and R4) depend on the type of logic design to be utilized. For instance, for emitter-coupled logic (ECL) the typical peak-to-peak voltage is 750 mV. In general, logical output peak-to-peak voltages range from 250 mV - 750 mV.
  • Node 4 (the emitter of Q6) tries to approach a voltage potential equal to [(VT) x In(I6/I5)] below node 2 (the emitter of Q5).
  • node 4 never reaches that potential.
  • the peak-to-peak voltage of interconnect line 11 is clamped to a voltage potential less than [(VT) x In(I6/I5)], (i.e., less than the 60 mV at 25 degrees Celsius for an NPN cascode pair clamp).
  • OUT is equal to VDD - (R4 x IREF + 14) and OUT/ is equal to VDD - (R3 x 12). Since IREF is much greater than 12, OUT is low and OUT/ is high.
  • FIG. 2 shows another embodiment of the present invention.
  • multiple current mode drivers are coupled to a pair of interconnect lines and a single current mode receiver.
  • current mode drivers 1 and 2 are shown in close proximity, however they may be located anywhere within the IC.
  • more than two drivers may be coupled to interconnect lines 10 and 11.
  • Current mode driver 1 includes NPN transistors Ql and Q2 and current mode driver 2 includes Q8 and Q9.
  • NMOS device Ml is biased to function as a current source by VREF. Ml supplies IREF to either of the drivers depending on control signals SI and S2.
  • Select transistors Q7 and Q10 are controlled by signals SI and S2.
  • Control signals SI and S2 determine which current mode driver transmits its corresponding data to the current mode receiver. For example when SI is high and S2 is low, IREF flows through Q7 and current mode driver 1. When this occurs, the data on the input of current mode driver 1, i.e., INI and INI/, is transmitted to the current mode receiver in the form of a current mode signal.
  • Current mode driver 2 has no effect on lines 10 and 11 since Q10 is off and no current flows through Q8 or Q9.
  • IREF flows through Q10 and current mode driver 2.
  • current mode driver 2 i.e. IN2 and IN2/
  • the current mode receiver converts the current mode signal from the selected driver into a differential voltage mode signal.
  • the current mode receiver in Figure 2 includes cascode clamp transistors Q5 and Q6 and their corresponding NMOS biasing current sources M2 and M4.
  • M2 and M4 are biased by VREF and are sized so as to provide a selected biasing current.
  • Devices M2 and M4 function to bias Q5 and Q6 in their low resistance regions to ensure quick recovery from transients.
  • the cascode clamp portion of the receiver includes matched load resistors R5 and R6. These resistors are the loads of the feedback amplifier which help reduce the voltage excursion at nodes 2 and 3. Under certain circumstances during the switching between the drivers, the total current injection into the transmission lines is greater than IREF. This may result in saturating the cascode amplifier. Therefore, the output is not taken from the collectors of the cascode amplifier, but rather at the collectors of the feedback amplifier Q3 and Q4. R7 and R8 are added to increase the gain to produce the required swing.
  • the current mode receiver in Figure 2 functions in the same manner as the previously described current mode receiver shown in Figure 1.
  • smaller voltage swings are seen on the interconnect lines (nodes 2 and 4) while relatively larger voltage swing occur on internal nodes 1 and 3 of the receiver. Consequently, transmission delays are reduced since the peak-to-peak voltage swing on the interconnect lines is reduced.
  • the range of output swing of the present invention's receiver is more versatile.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)

Abstract

Appareil permettant de réduire les temps d'attente de transmission lors de l'émission de signaux différentiels qui circulent dans un circuti intégré le long de longues lignes d'interconnexion (10, 11), ledit appareil comprenant un excitateur de ligne en mode courant qui convertit le signal différentiel à envoyer en un signal ayant une tension crête-à-crête relativement faible et de grandes variations du courant différentiel. Un récepteur qui réagit aux variations du courant différentiel reconvertit le signal en un signal différentiel de sortie dont les tensions crête-à-crête peuvent s'adapter à des états logiques subséquents. Un circuit de retour (Q5, Q6) couplé aux lignes d'interconnexion (10, 11) et au récepteur assure le verrouillage des lignes d'interconnexion (10, 11) à une tension prédéterminée, tout en autorisant le signal différentiel de sortie à avoir des tensions crête-à-crête supérieures à la tension prédéterminée.
EP94915426A 1993-08-10 1994-04-28 RECEPTEUR ET EXCITATEUR DE MODE COURANT BiCMOS Withdrawn EP0739552A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10477593A 1993-08-10 1993-08-10
US104775 1993-08-10
PCT/US1994/004613 WO1995005033A1 (fr) 1993-08-10 1994-04-28 RECEPTEUR ET EXCITATEUR DE MODE COURANT BiCMOS

Publications (1)

Publication Number Publication Date
EP0739552A1 true EP0739552A1 (fr) 1996-10-30

Family

ID=22302306

Family Applications (1)

Application Number Title Priority Date Filing Date
EP94915426A Withdrawn EP0739552A1 (fr) 1993-08-10 1994-04-28 RECEPTEUR ET EXCITATEUR DE MODE COURANT BiCMOS

Country Status (6)

Country Link
EP (1) EP0739552A1 (fr)
JP (1) JPH09501552A (fr)
AU (1) AU6669194A (fr)
CA (1) CA2164523A1 (fr)
IL (1) IL109757A0 (fr)
WO (1) WO1995005033A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105429624A (zh) * 2014-09-15 2016-03-23 美国亚德诺半导体公司 信号隔离器***中的开关键调制信号的解调
US10536309B2 (en) 2014-09-15 2020-01-14 Analog Devices, Inc. Demodulation of on-off-key modulated signals in signal isolator systems

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002073805A1 (fr) * 2001-03-14 2002-09-19 Koninklijke Philips Electronics N.V. Dispositif a mode de courant et agencement de communication comprenant des dispositifs a mode de courant
US9024603B2 (en) * 2012-02-01 2015-05-05 Conexant Systems, Inc. Low power current comparator for switched mode regulator
US9660848B2 (en) 2014-09-15 2017-05-23 Analog Devices Global Methods and structures to generate on/off keyed carrier signals for signal isolators
US9998301B2 (en) 2014-11-03 2018-06-12 Analog Devices, Inc. Signal isolator system with protection for common mode transients
KR102295708B1 (ko) * 2020-06-05 2021-08-30 한양대학교 산학협력단 전류 모드 로직 회로

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9505033A1 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105429624A (zh) * 2014-09-15 2016-03-23 美国亚德诺半导体公司 信号隔离器***中的开关键调制信号的解调
CN105429624B (zh) * 2014-09-15 2019-07-26 美国亚德诺半导体公司 信号隔离器***中的开关键调制信号的解调
US10536309B2 (en) 2014-09-15 2020-01-14 Analog Devices, Inc. Demodulation of on-off-key modulated signals in signal isolator systems

Also Published As

Publication number Publication date
WO1995005033A1 (fr) 1995-02-16
IL109757A0 (en) 1994-08-26
JPH09501552A (ja) 1997-02-10
CA2164523A1 (fr) 1995-02-16
AU6669194A (en) 1995-02-28

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