EP0639847B1 - Structure de cathode à émission de champ et méthode de fabrication - Google Patents

Structure de cathode à émission de champ et méthode de fabrication Download PDF

Info

Publication number
EP0639847B1
EP0639847B1 EP19940306076 EP94306076A EP0639847B1 EP 0639847 B1 EP0639847 B1 EP 0639847B1 EP 19940306076 EP19940306076 EP 19940306076 EP 94306076 A EP94306076 A EP 94306076A EP 0639847 B1 EP0639847 B1 EP 0639847B1
Authority
EP
European Patent Office
Prior art keywords
layer
hole
supporting substrate
field emission
emitter material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19940306076
Other languages
German (de)
English (en)
Other versions
EP0639847A1 (fr
Inventor
Masayuki C/O Intellectual Prop. Div. Nakamoto
Tomio C/O Intellectual Property Div. Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0639847A1 publication Critical patent/EP0639847A1/fr
Application granted granted Critical
Publication of EP0639847B1 publication Critical patent/EP0639847B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type

Definitions

  • This invention relates to a field emission cathode for use as in flat panel displays and a method for the production thereof.
  • the method of this kind proceeds sequentially through the steps of manufacture shown with a model in Fig. 6A, Fig. 6B, and Fig. 6C, for example.
  • a SiO 2 layer 3 is superposed on a silicon (Si) single crystal substrate 1
  • a gate electrode material layer 9 and a separating layer 6 are sequentially superposed further thereon, and then pin holes 4 of a diameter of about 1.5 ⁇ m are bored through the superposed layers.
  • an emitter material 8 destined to effect field emission is formed in the form of a conical body 8a as by the vacuum deposition method on the substrate 1 as shown in Fig. 6B.
  • the SiO 2 layer 3 is superposed as by the CVD method and the Mo layer 9 and the Al layer 6 are further superposed sequentially as by the sputtering method on the Si single crystal substrate 1.
  • the SiO 2 layer 3 mentioned above, the Mo layer 9 as a gate electrode layer, and the Al layer 6 as a separating layer are selectively etched to bore a pin hole having a diameter of about 1.5 ⁇ m as shown in Fig. 6A.
  • the Si single crystal substrate 1 is disposed substantially horizontally and rotated and, in the meanwhile, a material such as, for example, Mo which has the function of an emitter is vacuum deposited on the surface of the substrate from a direction perpendicular thereto as shown in Fig. 6B.
  • a material such as, for example, Mo which has the function of an emitter is vacuum deposited on the surface of the substrate from a direction perpendicular thereto as shown in Fig. 6B.
  • the Mo is accumulated inside the pin hole and on the Al layer 6. Since the mouth of the pin hole 4 is gradually closed with the progress of the accumulation, the Mo is deposited in the shape of a sharply pointed cone on the substrate 1 inside the pin hole 4.
  • a conical body 8a of Mo is obtained.
  • the Mo layer 8 deposited on a gate electrode layer 9a is selectively removed and the Al layer 6 is subsequently removed to give rise to such a field emission cathode as shown in Fig. 6C.
  • the field emission cathode of the construction described above obtains the conical body 8 of an emitter material inside the pin hole 4 bored in the SiO 2 layer by the rotary vacuum deposition of the emitter material which makes use of the phenomenon that the mouth of the pin hole 4 gradually dwindles.
  • the conical body 8a of the emitter material finished in the shape of a cone having a sharply pointed tip is at a disadvantage in being deficient in uniformity of field emission because the height of the conical body 8a and the shape of the tip thereof tend to be dispersed by such factors as the material and thickness of the gate electrode layer 9a, the shape and state of the pin hole 4 bored, and the conditions set for the rotary vacuum deposition.
  • the SiO 2 layer as a separate layer 3 is formed in a relatively large thickness as by the CVD method, the distance between the gate and the emitter greatly affects the efficiency of field emission and is not easily controlled with high accuracy.
  • the SiO 2 layer 3 is deficient in uniformity of field emission and consequently susceptible of dispersion of the field emission.
  • the field emission cathode (element) can be driven at a low voltage by closely approximating the gate and the emitter to each other. Actually, however, the efficiency of field emission is markedly dispersed and- the theoretically attainable effect is not obtained because the distance between the gate and the emitter cannot be controlled with high accuracy as described above.
  • An object of this invention is to provide a field emission cathode which has an emitter formed uniformly in shape and has a gate separated by an accurately controlled distance from the emitter and which, therefore, generates uniform field emission, drives effectively at a low voltage, effects the field emission efficiently, and permits further integration easily.
  • Another object of this invention is to provide a method for producing the field emission cathode mentioned above with high efficiency enough to warrant satisfactory productivity.
  • the field emission cathode structure of this invention is defined in claim 1.
  • a first method of this invention for the production of a field emission cathode structure is defined in claim 9.
  • a second method of this invention is defined in claim 16.
  • the invention further comprises a third method for the production of a field emission cathode structure as defined in claim 17.
  • the field emission cathode of this invention has originated in the interest drawn to the fact that a pyramidal or conically hole having a sharp pointed tip can be formed on the surface of a supporting substrate such as, for example, a Si single crystal substrate by harnessing the anisotropy of etching, the fact that a layer having an impurity diffused therein functions as an etching stopper layer, the fact that the impurity diffusion layer also functions as a gate electrode layer depending on the magnitude of resistance thereof, and the fact that an oxide layer (insulator layer) having a sharp pointed tip part is formed along a prescribed surface by the use of the thermal oxidation method.
  • the first supporting substrate may be made of any material which satisfies the condition that it should permit a hole of a sharp pointed tip to be selectively formed therein and exhibit a selective etching property with respect to an insulating layer and a high-concentration impurity diffusion layer to be integrally joined thereto. It is, however, desired to be a Si or Ge single crystal substrate in due respect of the ease with which the high-concentration impurity diffusion layer is formed and the ease with which the formation of an insulator layer rich in accuracy of film thickness and shape is controlled.
  • Silicon (Si) containing boron (B) as a p-type impurity at a concentration of not less than 3 x 10 19 cm -3 may be cited as one example of the material for the high-concentration impurity diffusion layer.
  • the concentration of this impurity is as high as about 10 20 to 10 21 cm -3
  • the high-concentration impurity diffusion layer can be used concurrently as a gate electrode layer because the electric resistance is as low as about 10 -4 ⁇ .cm.
  • the material for the impurity diffusion layer does not need to be limited to the particular substance mentioned above. It is only required to be such that the impurity diffusion layer may function as an etching stopper layer when the first supporting substrate is removed by etching. It may be an n-type material or an i-type material instead of the p-type material mentioned above.
  • the insulator layer may be formed by depositing SiO 2 on the surface of the impurity diffusion layer mentioned above by the use of the CVD method, for example.
  • the insulator layer is desired to be formed by subjecting the surface of the impurity diffusion layer mentioned above to the process of thermal oxidation because this process imparts a dense texture to the produced layer and permits easy control of the thickness of the layer and allows the insulator layer having a sharp pointed tip to be formed along the wall surfaces of a pyramidal hole, for example.
  • the thermally oxidized insulation layer can be formed as easily controlled and, therefore, the distance between the gate and the emitter can be controlled with high accuracy.
  • the supporting substrate can be removed by etching without exposing the insulator layer and the emitter material layer to the possibility of corrosion because the impurity diffusion layer functions as an etching stopper layer. Since the thermally oxidized insulation layer and the emitter material layer are protected against the corrosion by the etching liquid as described above and also since the distance between the gate and the emitter is decreased, the field emission efficiency and the uniformity of the field emission cathode are improved to a great extent.
  • the emitter material is disposed as embedded (filled) in the hole formed in the supporting substrate and the hole is formed with high accuracy as well, the emitter which is uniform in height, shape, and sharpness of sharp pointed tip is manufactured with high repeatability.
  • the tip of the hole gains in sharpness because the growth of the thermally oxidized insulation layer on the inner wall surfaces of the hole advances toward the interior of the hole.
  • the tip part of the emitter formed by filling the emitter material in the hole becomes sharp (refer to Fig. 2B).
  • the high-concentration impurity diffusion layer primarily functions as an etching stopper layer.
  • it has a high p-type impurity concentration and enjoys high electric conductivity, it can be used directly as a gate electrode layer.
  • this layer and the insulator layer which has been formed as ideally controlled cooperate to permit accurate control of the distance between the gate and the emitter and the mutual approximation thereof and, at the same time, obviates the necessity of the step for the formation of the gate electrode layer. The omission of this step naturally results in reducing the labor, man-hour, and material cost involved in the production of the field emission cathode of this invention.
  • Fig. 1 is a partially sectioned perspective view showing the construction of the essential part of a field emission cathode as one embodiment of this invention.
  • Figs. 2A, B, C, D, E, F, G, and H are a series of model explanatory diagrams showing the first embodiment of the method for the production of a field emission cathode according to this invention.
  • Fig. 2A is a cross section showing the state of a hole having a sharp pointed tip formed on the surface of a supporting substrate.
  • Fig. 2B is a cross section showing the state of having an impurity diffusion layer, an insulator layer, an emitter material layer, and an electroconductive layer sequentially formed on the surface of the supporting substrate containing the hole.
  • Fig. 2C is a cross section showing the state of having an insulating supporting substrate joined in place.
  • Fig. 2D is a cross section showing the state of having the surface of the substrate layer removed by etching until the projection corresponding to the hole is exposed.
  • Fig. 2E is a cross section showing the state of having the surface including the exposed projection masked.
  • Fig. 2F is a cross section showing the state of having the tip of the gate electrode layer of the projection exposed.
  • Fig. 2G is a cross section showing the state of having the exposed tip part of the gate electrode layer removed to form an opening.
  • Fig. 2H is a cross section showing the state of having the tip parts of the impurity diffusion layer and the insulator layer showing through the opening of the gate electrode layer removed to expose the tip of the projection of the emitter material layer.
  • Figs. 3A, B, C, D, E, and F are a series of model explanatory diagrams showing the second embodiment of the method for the production of the field emission cathode according to this invention.
  • Figs. 4A, B, C, D, E, and F are a series of model explanatory diagrams showing the third embodiment of the method for the production of the field emission cathode according to this invention.
  • Figs. 5A, B, C, D, E, and F are a series of model explanatory diagrams showing the fourth embodiment of the method for the production of the field emission cathode according to this invention.
  • Figs. 6A, B, and C are a series of model explanatory diagrams showing the procedure for the production of a conventional field emission cathode.
  • Fig. 6A is a cross section showing the state of having an insulator layer incorporating therein a pin hole for the deposition of an emitter material and a gate electrode layer sequentially superposed on the surface of a Si substrate.
  • Fig. 6B is a cross section showing the state of having the emitter material superposed by sputtering.
  • Fig. 6C is a cross section showing the construction of the field emission cathode.
  • Fig. 1 is a partly sectioned perspective view schematically showing an example of the construction of a field emission cathode according to this invention.
  • 17 stands for an insulating supporting substrate such as, for example, a Pyrex glass sheet
  • 18 for an emitter material layer superposed on the surface of the insulating supporting substrate 17 and provided integrally with a projection (main body part of the emitter) 18a pointed sharply in the tip thereof and made of an emitter material such as, for example, an emitter material layer made of such a metallic material as W, Mo, or Ta and provided with a pyramidal projection 18a having a sharp pointed tip
  • 13 for an insulator layer such as, for example, a SiO 2 layer covering the projection 18a of the main body of the emitter while exposing the tip part thereof.
  • 12 stands for a high-concentration impurity diffusion layer such as, for example, a boron (B) doped Si layer covering the surface of the insulator layer 13 while exposing the tip part of the projection 18a of the main body of the emitter and 19a for a gate electrode layer covering the surface of the impurity diffusion layer 12 while exposing the tip part of the projection 18a of the main body of the emitter.
  • a high-concentration impurity diffusion layer such as, for example, a boron (B) doped Si layer covering the surface of the insulator layer 13 while exposing the tip part of the projection 18a of the main body of the emitter and 19a for a gate electrode layer covering the surface of the impurity diffusion layer 12 while exposing the tip part of the projection 18a of the main body of the emitter.
  • B boron
  • the field emission cathode of this invention is essentially constructed by forming as the main body part of an emitter the projection 18a of an emitter material in the shape of a pyramid, for example, as superposed on the surface of the insulating supporting substrate (structural substrate) 17, then exposing the tip part of the pyramidal projection 18a in such a manner as to effect required emission of electrons in a direction substantially perpendicular to the surface of the insulating supporting substrate 17, and further disposing the electrode layer capable of functioning as a gate electrode so as to be opposed across a gap to the tip part of the projection 18a of the main body of the emitter.
  • the field emission cathode constructed as described above can be easily manufactured by the steps shown with a model in Figs. 2A, B, C, D, E, F, G, and H, for example.
  • a Si single crystal substrate (first supporting substrate) 11 is prepared.
  • One main surface of this supporting substrate 11 is anisotropically etched to form a hole 11a (in the shape of an inverted pyramid) having a tip part pointed at a prescribed angle as shown in Fig. 2A.
  • a thermally oxidized film (SiO 2 film) about 0.1 ⁇ m in thickness is formed as by the dry oxidation method on the main surface of a p-type Si single crystal substrate 11 having a crystal face orientation of (100) and a resist is applied by the spin coating method to the surface of the thermally oxidized film.
  • the resist is patterned so as to obtain an opening of the shape of the square of 0.8 ⁇ m, for example, through the treatments of exposure and development with the aid of a stepper, the exposed area of the oxide film (SiO 2 film) is selectively etched with a mixed solution of NH 4 F ⁇ HF, the resist is removed, and the anisotropic etching is carried out with an aqueous 30% KOH solution to give rise to the hole 11a of the shape of an inverted pyramid 0.56 ⁇ m in depth on the main surface of the Si single crystal substrate 11.
  • the thermally oxidized film which has served as the mask is removed with the mixed solution of NH 4 ⁇ HF and the Si layer 12 containing a P-type impurity at a concentration of not less than 3 x 10 19 cm -3 such as, for example, a B-diffused Si Layer 12 having a thickness of 0.3 ⁇ m, is superposed in a substantially uniform thickness on the surface of the Si single crystal substrate 11 containing the hole 11a of the shape of an inverted pyramid.
  • the B-diffused Si layer 12 in this case functions as an etching stopper layer (sacrifice layer) during the removal of the Si single crystal substrate 11.
  • This layer 12 can be used in its unmodified form as a gate electrode layer when the concentration of the p-type impurity is so high as to fall in the range of from 10 20 to 10 21 cm -3 and the electric resistance is so low as to fall in the neighborhood of 10 -4 ⁇ cm. In this case, the number of man-hours can be decreased and the distance between the gate and the emitter can be shortened to permit desirable mutual approximation.
  • the Si single crystal substrate 11 provided with the p-type impurity diffusion Si layer 12 is subjected to a treatment of thermal oxidation to effect thermal oxidation of the surface of the p-type impurity diffusion Si layer 12 and give rise to the insulator layer 13 having a thickness of 0.2 ⁇ m.
  • an emitter material such as, for example, W, Mo, or Ta is sputtered on the surface of the insulator layer 13 so as to fill the pyramidal hole covering the p-type impurity diffusion Si Layer 12 and the insulator layer 13, form the emitter projection 18a conforming to the hole mentioned above, and also form the emitter material layer 18 having a smoothly finished surface and a thickness of about 0.8 ⁇ m.
  • an electroconductive layer 15 such as, for example, an ITO (indium-tin type oxide) layer 15 having a thickness of about 1 ⁇ m, is superposed as by sputtering to produce such a laminate as shown in Fig. 2B.
  • the ITO layer 15 may be omitted, depending on the material used for the emitter material layer 18. When this omission is made, the emitter material layer 18 goes to play the part of a cathode electrode layer concurrently.
  • the second supporting substrate such as, for example, a Pyrex glass sheet 17 having the rear surface (back surface) thereof coated with an Al layer 16 destined to serve as an electrostatic bonding electrode and having a thickness of about 0.4 ⁇ m is superposed on the laminate mentioned above.
  • the ITO layer 15 and the Al layer 16 are interjoined by the so-called electrostatic bonding method which resides in applying a voltage of the order of some hundreds of V between the layers (Fig. 2C). Though this union of the two layers may be accomplished by the use of an adhesive agent, the electrostatic bonding method proves more advantageous from the viewpoint of providing the produced field emission cathode with greater reduction in weight and thickness.
  • the rear coat (Al) layer 16 of the Pyrex glass sheet 17 is removed by etching as with a mixed acid solution of HNO 3 ⁇ CH 3 COOH ⁇ HF, for example.
  • the Si single crystal substrate 11 as the first supporting substrate is removed by etching by the use of an aqueous solution containing the mixture of ethylene diamine, pyrocatechol, and pyrazine (mixing ratio 75 cc : 12 g : 3 mg : 10 cc) to give rise to a laminate composed of the insulator layer 13 and the emitter layer 18 provided with the pyramidal projection 18a (conforming to the aforementioned pyramidal hole 11a) and covered by the p-type impurity diffusion Si layer 12 as shown in Fig. 2D.
  • the p-type impurity diffusion Si layer 12 functions as an etching stopper layer for the Si single crystal substrate 11 and discharges the role of protecting the insulator layer 13 having a small film thickness and the pyramidal projection 18a of the main body of the emitter having a sharp pointed tip against corrosion by the etching solution mentioned above.
  • W is deposited in the form of a coat in a thickness of about 0.5 ⁇ m as by the sputtering method, for example.
  • a photoresist layer 20 is applied as by the spin coating method in a thickness such as, for example, about 0.9 ⁇ m which is enough to conceal a tip part 19t of the projection on the surface of the W coat layer 19 embracing therein the pyramidal projection 18a of the emitter as shown in Fig. 2E.
  • part of the photoresist layer 20 is removed so that the tip part 19t of the projection of the W coat layer containing the projection 18a of the emitter may be exposed in a thickness of about 0.7 ⁇ m through the surface as shown in Fig. 2F.
  • the tip part 19t of the projection of the W coat layer 19 which has been exposed by the removal by etching of part of the photoresist layer 20 is selectively removed to form the gate electrode layer 19a provided with an opening 19b exposing the tip part of the projection covering the impurity diffusion layer 12 and the insulator layer 13 as shown in Fig. 2G.
  • the field emission cathode is obtained which is so constructed as to expose the tip part 18t of the pyramidal projection 18a of the main body of the emitter through the opening 19b of the gate electrode layer 19a as shown in Fig. 2H.
  • the high-concentration impurity diffusion layer 12 doped with an impurity is formed on the surface of the supporting substrate 11 provided with the hole formed by anisotropic etching and pointed sharply in the tip (bottom surface side) thereof, the insulator layer 13 is further formed thereon by the thermal oxidizing method, and subsequently the emitter material layer 18 is formed in such a manner as to fill the hole mentioned above.
  • the hole having a sharply pointed tip is formed in a prescribed shape with high repeatability by the anisotropic etching.
  • the emitter function part is formed which possesses a sharp pointed tip part uniform in height and shape and also excels in uniformity of quality.
  • the provision of field emission cathodes with stabilized quality can be realized. Further, since the insulator layer 13 can be formed in a fully accurately controlled thickness by the thermal oxidizing method, the distance between the emitter function part mentioned above and the gate electrode layer 19a (emitter-gate distance) is controlled with high accuracy. Thus, the field emission cathode is capable of operating at a relatively low voltage to effect highly efficient emission.
  • the embodiment described above represents a case of having the gate electrode layer 19a superposed on the surface of the impurity diffusion layer 12.
  • the operation and effect of the embodiment under consideration are similarly attained by causing the impurity diffusion layer 12 to function as a gate electrode layer when this impurity diffusion layer 12 has a high impurity concentration and a high electric resistance or by removing the impurity diffusion layer 12 participating mainly in the selective etching of the supporting substrate 11 thereby exposing the insulator layer 13 and superposing the gate electrode layer 19a on the surface of the exposed insulator layer 13.
  • the effect manifested by the embodiment is invariable when the impurity mentioned above is a p-type B, Al, Ga, or In, an n-type P, As, or Ti, or an i-type Ge or Sn.
  • the material for the first supporting substrate such substance as GaAs in the place of Si single crystal and as the emitter material Mo, Ta, Si, or other substance having a low work function in the place of W.
  • the operation and effect of the present embodiment are obtained invariably when a soda glass plate is used in the place of the Pyrex glass plate as the second supporting substrate (structural substrate).
  • the embodiment described above represents a case of handing the field emission cathode as a unitary article.
  • a group of such field emission cathodes may be arrayed in the form of a matrix, for example, on one Si single crystal sheet to produce a planar field emission cathode.
  • the field emission cathode of the first embodiment of this invention has originated in the interest drawn to the fact that a pyramidal or conical hole having a pointed tip can be formed on the surface of a supporting substrate by utilizing the anisotropy of etching, the fact that a region converted into an impurity diffusion layer functions as an etching stopper layer, the fact that the impurity diffusion layer functions concurrently as a gate electrode layer when it has low resistance, and the fact that an acute oxide layer (insulator layer) is formed in a highly accurately controlled shape along a prescribed surface by the use of the thermal oxidation method.
  • the field emission cathode of the present invention always enjoys excellent qualities of constantly displaying ideal uniformity of field emission, providing an effective operation at a low voltage, and obtaining high field emission efficiency.
  • the field emission cathode which is endowed with such functional characteristics as mentioned above and is easily adapted for high integration can be manufactured with highly satisfactory yield and productivity (ability of quantity production).
  • the method of production contemplated by this invention may well be rated as contributing greatly to the utilization of field emission cathodes of this type in practical applications.
  • Figs. 3A, B, C, D, E, and F are a series of diagrams showing a process for the production of a field emission cathode as the second embodiment of this invention.
  • the method of production according to the second embodiment will be described below with reference to these diagrams.
  • like parts found in the first embodiment are denoted by like reference numerals.
  • the Si single crystal substrate 11 offering low resistance and having a crystal face orientation of (100) is prepared as a first supporting substrate.
  • the hole 11a sharply pointed toward the bottom part thereof is incised on one flat surface of the Si single crystal substrate 11 (hereinafter referred to as the first main surface) as shown in Fig. 3B.
  • the method which utilizes the anisotropic etching of Si to be described hereinbelow may be adopted.
  • a thermally oxidized film of SiO 2 is superposed in a thickness of about 0.1 ⁇ m by the dry oxidizing method.
  • the photoresist is patterned so as to obtain an opening of the shape of the square of 1 ⁇ m, for example, through the treatments of exposure and development with the aid of a stepper and the thermally oxidized SiO 2 film is etched by the use of the mixed solution of NH 4 F ⁇ HF as an etchant.
  • the photoresist is removed and the first main surface of the Si single crystal substrate 11 is subjected to the anisotropic etching by the use of an aqueous 30 wt% KOH solution as an etchant.
  • the hole 11a of the shape of an inverted pyramid 0.71 ⁇ m in depth is incised on the first main surface side of the Si single crystal substrate 11.
  • the thermally oxidized SiO 2 film remaining on the surface of the Si single crystal substrate 11 is removed by the use of the mixed solution of NH 4 F ⁇ HF, for example.
  • the thermally oxidized layer 13 is formed as shown in Fig. 3C on the first main surface of the Si single crystal substrate 11 including the inner wall surfaces of the hole 11a by subjecting the surfaces mentioned above to a treatment of thermal oxidation.
  • the thermally oxidized layer 13 is formed by the wet method of thermal oxidation so as to acquire a thickness of 0.5 ⁇ m.
  • the emitter material layer 18 using W or Mo is formed on this thermally oxidized layer 13.
  • This emitter material layer 18 is so formed as to cover the upper surface of the thermally oxidized layer 13 while filling the hole 11a.
  • the emitter material layer 18 is deposited by the sputtering method so as to form a film 2 ⁇ m in thickness on the thermally oxidized layer 13 excepting the hole 11a.
  • the glass substrate 17 made of such a highly heat-resistant material as Pyrex glass and provided on the rear surface thereof with the Al layer 16 of a thickness of 0.3 ⁇ m as a coating as shown in Fig. 3D is prepared.
  • This glass substrate 17 is superposed on and joined fast to the surface of the emitter material layer 18 opposite to the surface thereof on which the projection 18a of a sharp pointed tip.
  • the electrostatic bonding method may be adopted, for example.
  • the Al layer 16 on the rear surface of the glass substrate 17 is removed with the mixed acid solution of HNO 3 ⁇ CH 3 OOH ⁇ HF.
  • EDP so-called a mixed aqueous solution of ethylene diamine, pyrocatechol, and pyrazine
  • the etching time is so controlled that the Si single crystal layer 11 may remain in a thickness allowing the tip part of the projection 18a of the emitter material layer 18 to be finally exposed and, at the same time, the lower part of the emitter material layer 18 to be coated with the Si single crystal layer 11 through the thermally oxidized layer 13 as shown in Fig. 3E.
  • the Si single crystal substrate 11 is not wholly etched evenly in the direction of thickness thereof.
  • the Si single crystal layer 11 is used as a gate electrode.
  • the thermally oxidized layer 13 covering the sharply pointed tip part of the projection 18a of the emitter material layer 18 is exposed from the Si single crystal layer 11.
  • the part of the thermally oxidized layer 13 which covers the tip part of the projection 18a of the emitter material layer 18 is removed by etching with the mixed solution of NH 4 F ⁇ HF as an etchant to expose the sharp pointed tip part of the projection 18a partly from the Si single crystal layer 11 as shown in Fig. 3F.
  • the emitter is obtained.
  • the method of production described above has the effect of enabling the field emission cathode contemplated by this invention to be formed with ease in addition to the effect manifested by the method of production of the first embodiment.
  • Figs. 4A, B, C, D, E, and F are a series of diagrams showing a process for the production of the field emission cathode of the third embodiment of this invention.
  • the method production of the third embodiment will be explained below with reference to these diagrams.
  • like parts found in the first and the second embodiment are denoted by like reference numerals.
  • the present embodiment is characterized by superposing the etching stopper layer 12 having boron (B) diffused therein at a high concentration and having a small thickness on the Si single crystal substrate 11 and causing the advance of the etching of the Si single crystal substrate 11 from the second main surface side thereof to be stopped by this etching stopper layer 12. It, therefore, finds no use for such complicate control of the etching time as is encountered in the second embodiment and facilitates the formation of the field emission cathode of this invention to a greater extent.
  • B boron
  • the etching stopper layer 12 of a small thickness is formed on the first main surface of the Si single crystal substrate 11 having a crystal face orientation of (100) by diffusing on the surface mentioned above the ions of such an impurity as boron (B) at a high concentration of not less than 10 19 cm -3 , for example.
  • This high-concentration impurity diffusion is effected by the thermal diffusion method or the ion injection method, for example.
  • the hole 11a pointed sharply toward the bottom part thereof is incised in the Si single crystal substrate 11 from the etching stopper layer 12 (first main surface) side in the same manner as in the first embodiment.
  • the method which resorts to the anisotropic etching of Si may be adopted similarly to the second embodiment.
  • the treatment of thermal oxidation by the dry method is performed on the surface of the etching stopper layer 12 to form a thermally oxidized SiO 2 film in the etching stopper layer 12 to a depth of about 0.1 ⁇ m.
  • the photoresist (not shown) is further applied to the thermally oxidized SiO 2 film by the spin coating method.
  • the photoresist is patterened as by the treatments of exposure and development by the use of a stepper, for example, so as to obtain an opening in the shape of the square of 1 ⁇ m.
  • the thermally oxidized SiO 2 film is subsequently patterned by the use of the mixed solution of NH 4 F ⁇ HF as an etchant.
  • the photoresist mentioned above is removed and the anisotropic etching is carried out with the pattern of the thermally oxidized SiO film as an etching mask and the aqueous 30 st% KOH solution as an etchant.
  • the hole 11a having the shape of an inverted pyramid is incised in a depth of 0.71 ⁇ m reaching beyond the first main surface of the Si single crystal substrate 11. Then, the thermally oxidized SiO 2 film remaining on the surface of the etching stopper layer 12 is removed by the use of the mixed solution of NH 4 F ⁇ HF, for example.
  • an ideal etching speed is obtained even when the etching stopper layer 12 is formed on the Si single crystal substrate 11 because the aqueous KOH solution manifests a practically equal etching rate on the etching stopper layer 12 having boron (B) diffused at a high concentration therein and the Si single crystal.
  • the hole 11a can be ideally incised.
  • some other etchant may be used herein on the condition that it should be capable of etching the etching stopper layer 12.
  • the treatment of thermal oxidation is performed on the wall surfaces of the etching stopper layer 12 and the Si single crystal substrate 11 which are exposed through the hole 11a and on the flat surface of the etching stopper layer 12 to form the thermally oxidized layer 13.
  • the etching stopper layer 12 gains in thickness.
  • the thickness of the etching stopper layer 12 is set preparatorily during the formation of the Si single crystal substrate 11 so that the part of the thermally oxidized layer 13 covering the tip part of the pyramidal projection 18a may protrude from the etching stopper layer 12 even after the etching stopper layer 12 is inflated as described above.
  • such a material as W or Mo which makes an ideal emitter material is deposited on the thermally oxidized layer 13 to give rise to the emitter material layer 18.
  • the glass substrate 17 made of such a highly heat-resistant material as Pyrex glass and provided on the rear surface thereof with the Al layer 16 having a thickness of 0.3 ⁇ m as a coating is prepared as shown in Fig. 4D.
  • This glass substrate 17 is superposed on and attached fast to the surface of the emitter material layer 18 opposite to the surface thereof on which the pyramidal hole 18a pointed toward the tip thereof is formed.
  • the electrostatic bonding method may be adopted similarly to the second embodiment.
  • the Al layer 16 on the rear surface of the glass substrate 17 is removed with the mixed acid solution of HNO 3 ⁇ CH 3 OOH ⁇ HF.
  • EDP i.e. a mixed aqueous solution of ethylene diamine, pyrocatechol, and pyrazine
  • the etching stopper layer 12 is formed of a Si material having boron (B) diffused at a high concentration, the etchant like EDP which is used in the second embodiment manifests a considerably lower etching rate on the etching stopper layer 12 than on the single crystal of Si.
  • the etching advancing in the Si single crystal substrate 11 from the second main surface side thereof is stopped by the etching stopper layer 12, with the result that the etching stopper layer 12 will remain practically intact.
  • the thermally oxidized layer 13 covering the sharp pointed tip part of the projection 18a of the emitter material layer 18 can be partly exposed from the etching stopper layer 12.
  • the part of the thermally oxidized layer 13 covering the tip part of the projection 18a of the emitter material layer 18 is removed by etching with the mixed solution of NH 4 F ⁇ HF as an etchant to obtain partial exposure of the sharp pointed tip part of the projection 18a through the etching stopper layer 12.
  • the emitter is obtained.
  • the etching stopper layer 12 is formed of a Si material having boron (B) diffused therein at a high concentration and consequently enjoys high electric conductivity, it may be left in its unmodified form and used as a gate electrode.
  • the method of production of the third embodiment described above obviates the necessity of ensuring complicate control of the etching depth during the etching of the Si single crystal substrate 11 from the second main surface side thereof as involved in the second embodiment. It, therefore, brings about the effect of enabling the field emission cathode to be formed with further increased ease in addition to the effects obtained by the methods of production of the first and the second embodiment.
  • Figs. 5A, B, C, D, E, and F are a series of diagrams showing a process for the production of the field emission cathode of the fourth embodiment of this invention.
  • the method of production of the fourth embodiment will be explained with reference to these diagrams.
  • like parts found in the first and the second embodiment are denoted by like reference numerals.
  • This fourth embodiment will be described below with emphasis centering on the characteristic parts thereof which differentiate this embodiment from the embodiments described above.
  • the method of production of the present embodiment is characterized by using an etching stopper layer 12a formed of an n-type Si material in the place of the etching stopper layer 12 of the third embodiment described above and causing the etching advancing in the Si single crystal substrate 11 from the second main surface to be stopped by applying a reverse voltage to the etching stopper layer 12a.
  • the Si layer 12a is formed in a small thickness as by the thermal diffusion method or the ion injection method on the Si single crystal substrate 11 made of a p-type Si single crystal having a crystal face orientation of (100) and the Si single crystal substrate 11 and the Si layer 12a are joined by the pn junction across the interface.
  • the present embodiment is then characterized by adopting the electrochemical etching method at the step of removing the Si single crystal substrate 11 shown in Fig. 5E.
  • This method resides in applying reverse voltage to the pn junction produced in the interface between the etching stopper layer 12a and the Si single crystal substrate 11 in an aqueous KOH solution, for example, thereby selectively etching the p-type Si single crystal substrate 11 exclusively and allowing the n-type Si layer 12a to remain intact in spite of the etching.
  • the Si single crystal substrate 11 is progressively etched from the second main surface side thereof until the Si single crystal substrate 11 is corroded out practically throughout the entire thickness thereof and only the tip part of the projection 18a of the emitter material layer 18 is exposed through the etching stopper layer 12a.
  • the steps which follow are identical to the corresponding steps involved in the embodiments described above. Specifically, the part of the thermally oxidized layer 13 covering the tip part of the projection 18a of the emitter material layer 18 is removed by etching with the mixed solution of NH 4 F ⁇ Hf as an etchant as shown in Fig. 5F. Thus, the sharp pointed tip part of the projection 18a is partly exposed through the Si single crystal layer 12a. The emitter is obtained as a result.
  • the fourth embodiment under consideration offers the method of production which enables the gap between the emitter and the gate electrode to be formed accurately and easily.
  • the etching stopper layer 12 having boron (B) diffused therein at a high concentration or the n-type Si layer 12a may be preparatorily formed by epitaxial growth on the first main surface of the Si single crystal substrate 11 at the step of Fig. 4A or Fig. 5A.
  • this invention has been perfected for the purpose of realizing the fact that a pyramidal or conical hole pointed toward the tip thereof can be formed in a supporting substrate by utilizing the anisotropy of etching, the fact that a region converted into an impurity diffusion layer functions as an etching stopper layer, the fact that this impurity diffusion layer functions concurrently as a gate electrode layer depending on the magnitude of resistance thereof, and the fact that an acute oxide layer (insulator layer) can be formed accurately along prescribed surfaces by utilizing the thermal oxidation method.
  • the field emission cathode according to this invention is endowed with excellent qualities of constantly manifesting ideal field emission uniformly, operating effectively even at a low voltage, and obtaining high efficiency in field emission. Then, the method of this invention for the production of a field emission cathode allows field emission cathodes which are furnished with such functional characteristics as mentioned above and are readily adapted for further integration to be manufactured in a highly satisfactory yield with an ability of quantity production (mass production).

Claims (17)

  1. Structure de cathode à émission de champ comprenant un émetteur muni d'une extrémité acérée pour l'émission d'électrons et une électrode de grille de commande, ladite structure comprenant un second substrat de support (17), une couche de matériau d'émetteur (18) réalisée en un matériau d'émetteur, munie d'une protubérance (18a) et formée sur ledit second substrat de support, une couche isolante (13) formée sur la surface de ladite couche de matériau d'émetteur (18) afin de mettre à nu une extrémité (18t) de ladite protubérance (18a) au travers.
  2. Structure de cathode à émission de champ selon la revendication 1, dans laquelle une couche de diffusion d'impureté (12) est formée sur la surface de ladite couche isolante (13) et est amenée à fonctionner en tant que couche d'arrêt de gravure lorsqu'un premier substrat de support (11) formé sur ladite couche de diffusion d'impureté est ôté par gravure, ladite couche de diffusion d'impureté (12) pouvant être une couche d'électrode de grille.
  3. Cathode à émission de champ selon la revendication 1, laquelle comprend en outre une couche d'électrode de grille (19a) formée sur la surface de ladite couche de diffusion d'impureté (12) et le long du contour de ladite protubérance (18a) de ladite couche de matériau d'émetteur (18) et munie d'une ouverture (19b) encerclant ladite extrémité de ladite protubérance (18a).
  4. Cathode à émission de champ selon la revendication 1, dans laquelle ledit substrat de support (17) est une plaque en verre.
  5. Cathode à émission de champ selon l'une quelconque des revendications 1 à 4, dans laquelle ladite couche de diffusion d'impureté (12) est une couche en silicium contenant une impureté de type P.
  6. Cathode à émission de champ selon l'une quelconque des revendications 1 à 5, dans laquelle ladite impureté de type P est du bore (B) et est diffusée selon une concentration non inférieure à 3 x 1019 cm-3.
  7. Cathode à émission de champ selon l'une quelconque des revendications 1 à 6, dans laquelle ladite couche de diffusion d'impureté (12) présente une résistivité électrique non supérieure à 10-3 Ω·cm.
  8. Cathode à émission de champ selon l'une quelconque des revendications 1 à 7, dans laquelle ladite couche isolante (13) est une couche isolante oxydée thermiquement formée en SiO2.
  9. Procédé de fabrication d'une structure de cathode à émission de champ comprenant un émetteur muni d'une pointe acérée pour l'émission d'électrons et une électrode de grille de commande, comprenant une étape de formation d'un trou (11a) comportant une extrémité acérée sur un premier substrat de support (11), une étape de formation d'une couche de diffusion d'impureté (12) sur la surface dudit premier substrat de support (11) en incluant la surface de paroi dudit trou (11a), une étape de formation d'une couche isolante (13) sur la surface de ladite couche de diffusion d'impureté (12) en incluant la surface de paroi dudit trou, une étape de dépôt d'une couche de matériau d'émetteur (18) sur la surface de ladite couche isolante (13) en incluant ledit trou tout en remplissant ledit trou avec le matériau d'émetteur, une étape de jonction d'un seul tenant d'un second substrat (17) sur la surface de ladite couche de matériau d'émetteur (18), une étape d'enlèvement par gravure dudit premier substrat (11) pour ainsi mettre à nu la surface de ladite couche de diffusion d'impureté (12) munie d'une protubérance correspondant audit trou (11a) et une étape d'enlèvement sélectif de ladite couche de diffusion d'impureté (12) et de ladite couche isolante (13) pour ainsi mettre à nu une extrémité (18t) de la protubérance (18a) de ladite couche de matériau d'émetteur (18).
  10. Procédé selon la revendication 9, dans lequel ladite couche de diffusion d'impureté (12) est formée en tant que couche d'électrode de grille.
  11. Procédé selon la revendication 9, lequel comprend en outre une étape de formation d'une couche d'électrode de grille (19a) sur la surface de ladite couche de diffusion d'impureté (19) après l'étape d'enlèvement par gravure dudit premier substrat de support (11) pour ainsi mettre à nu la surface de ladite couche de diffusion d'impureté (19) munie d'une protubérance correspondant audit premier trou (11a) et l'étape d'enlèvement sélectif de ladite couche de diffusion d'impureté (12) et de ladite couche isolante (13) pour ainsi mettre à nu l'extrémité (18t) de la protubérance (18a) de ladite couche de matériau d'émetteur (18).
  12. Procédé selon l'une quelconque des revendications 9 à 11, dans lequel l'union d'un seul tenant de ladite couche de matériau d'émetteur (18) et dudit second substrat de support (17) est mise en oeuvre au moyen du procédé de liaison électrostatique.
  13. Procédé selon l'une quelconque des revendications 9 à 12, dans lequel la formation de ladite couche isolante (13) est réalisée en oxydant thermiquement ladite couche de diffusion d'impureté (12).
  14. Procédé selon l'une quelconque des revendications 9 à 13, dans lequel ladite couche de diffusion d'impureté (12) est formée en dopant au moins un élément choisi parmi le groupe comprenant B, Al, In, P, As, Ti, Ge et Sn en tant qu'impureté dans du Si.
  15. Procédé selon la revendication 14, dans lequel la concentration de ladite impureté n'est pas inférieure à 3 x 1019 cm-3.
  16. Procédé de fabrication d'une structure de cathode à émission de champ comprenant un émetteur muni d'une pointe acérée pour l'émission d'électrons et une électrode de grille de commande, comprenant une étape de formation d'un trou (11a) comportant une pointe acérée sur un premier substrat de support (11), une étape de formation d'une couche isolante (13) sur la surface dudit premier substrat de support (11) en incluant la surface de paroi dudit trou (11a), une étape de dépôt d'une couche de matériau d'émetteur (18) sur la surface de ladite couche isolante en incluant ledit trou tout en remplissant ledit trou avec un matériau d'émetteur, une étape de jonction d'un seul tenant d'un second substrat de support (17) sur la surface de ladite couche de matériau d'émetteur (18), une étape de gravure dudit premier substrat de support (11) au travers de sa surface mise à nu jusqu'à ce que le sommet d'une extrémité (18t) de la protubérance (18a) de ladite couche de matériau d'émetteur (18) munie de la protubérance (18a) correspondant audit premier trou (11a) en vienne à affleurer la surface dudit substrat de support (11) après la fin de ladite gravure et une étape d'enlèvement sélectif de ladite couche isolante (13) pour ainsi mettre à nu l'extrémité (18t) de la protubérance (18a) de ladite couche de matériau d'émetteur (18).
  17. Procédé de fabrication d'une structure de cathode à émission de champ comprenant un émetteur muni d'une pointe acérée pour l'émission d'électrons et une électrode de grille de commande, comprenant une étape de formation d'une couche d'arrêt de gravure (12) sur la première surface principale d'un premier substrat de support (11), une étape de formation d'un trou (11a) comportant une extrémité acérée sur ledit côté de première surface principale dudit substrat de support (11) par l'intermédiaire de ladite couche d'arrêt de gravure (12) jusqu'à une profondeur atteignant le mi-chemin de l'épaisseur dudit premier substrat de support (11), une étape de formation d'une couche isolante (13) sur la surface de ladite couche d'arrêt de gravure (12) en incluant la surface de paroi dudit trou (11a), une étape de dépôt d'une couche de matériau d'émetteur (18) sur la surface de ladite couche isolante (13) en incluant le trou tout en remplissant ledit trou avec un matériau d'émetteur, une étape de jonction d'un seul tenant d'un second substrat de support (17) sur la surface de ladite couche de matériau d'émetteur (18), une étape d'enlèvement par gravure dudit premier substrat de support (11) depuis son côté de seconde surface principale jusqu'à ladite couche d'arrêt de gravure (12) pour ainsi mettre à nu une partie d'extrémité de ladite couche isolante (13) d'une partie en protubérance dudit trou correspondant (11a) et une étape d'enlèvement sélectif de ladite couche isolante pour ainsi mettre à nu une extrémité (18t) d'une protubérance (18a) dudit matériau d'émetteur (18).
EP19940306076 1993-08-17 1994-08-17 Structure de cathode à émission de champ et méthode de fabrication Expired - Lifetime EP0639847B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP20316793 1993-08-17
JP203167/93 1993-08-17
JP332043/93 1993-12-27
JP33204393A JP3231528B2 (ja) 1993-08-17 1993-12-27 電界放出型冷陰極およびその製造方法

Publications (2)

Publication Number Publication Date
EP0639847A1 EP0639847A1 (fr) 1995-02-22
EP0639847B1 true EP0639847B1 (fr) 1997-06-25

Family

ID=26513777

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19940306076 Expired - Lifetime EP0639847B1 (fr) 1993-08-17 1994-08-17 Structure de cathode à émission de champ et méthode de fabrication

Country Status (3)

Country Link
EP (1) EP0639847B1 (fr)
JP (1) JP3231528B2 (fr)
DE (1) DE69403940T2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5795208A (en) * 1994-10-11 1998-08-18 Yamaha Corporation Manufacture of electron emitter by replica technique
US5599749A (en) * 1994-10-21 1997-02-04 Yamaha Corporation Manufacture of micro electron emitter
KR100405886B1 (ko) * 1995-08-04 2004-04-03 프린터블 필드 에미터스 리미티드 전계전자방출물질과그제조방법및그물질을이용한소자
JP3079993B2 (ja) * 1996-03-27 2000-08-21 日本電気株式会社 真空マイクロデバイスおよびその製造方法
JPH10149778A (ja) * 1996-09-17 1998-06-02 Toshiba Corp 微小冷陰極管とその駆動方法
US6963160B2 (en) 2001-12-26 2005-11-08 Trepton Research Group, Inc. Gated electron emitter having supported gate
DE10236149A1 (de) * 2002-08-05 2004-02-26 Universität Kassel Verfahren zur Herstellung einer eine schmale Schneide oder Spitze aufweisenden Struktur und mit einer solchen Struktur versehener Biegebalken
FR2899572B1 (fr) * 2006-04-05 2008-09-05 Commissariat Energie Atomique Protection de cavites debouchant sur une face d'un element microstructure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2968014B2 (ja) * 1990-01-29 1999-10-25 三菱電機株式会社 微小真空管及びその製造方法
JP3253683B2 (ja) * 1992-07-14 2002-02-04 株式会社東芝 電界放出型冷陰極板の製造方法

Also Published As

Publication number Publication date
JP3231528B2 (ja) 2001-11-26
JPH07111132A (ja) 1995-04-25
DE69403940T2 (de) 1997-12-11
DE69403940D1 (de) 1997-07-31
EP0639847A1 (fr) 1995-02-22

Similar Documents

Publication Publication Date Title
US5499938A (en) Field emission cathode structure, method for production thereof, and flat panel display device using same
US5151061A (en) Method to form self-aligned tips for flat panel displays
US6417606B1 (en) Field emission cold-cathode device
CA2034481C (fr) Methode a auto-alignement pour la fabrication d'electrodes de reseaux d'emetteurs
US20060237812A1 (en) Electronic emitters with dopant gradient
EP0639847B1 (fr) Structure de cathode à émission de champ et méthode de fabrication
US5847496A (en) Field emission device including a resistive layer
JP2000500266A (ja) 電界エミッタ装置、およびそれを製作するためのベールプロセス
US5727976A (en) Method of producing micro vacuum tube having cold emitter
KR100243990B1 (ko) 전계방출 캐소드와 그 제조방법
JPH1186719A (ja) 電界放射型素子の製造方法
US20040161929A1 (en) Selective etching of a protective layer for the formation of catalyst layer suitable for electron-emitting device, and associated fabrication method
JPH06196086A (ja) 電界放出陰極及びその形成方法
JP2946706B2 (ja) 電界電子放出素子
US5516404A (en) Method for manufacturing a micro-electronic component having an electrically conductive tip of doped silicon
JP3559440B2 (ja) 電界放出型冷陰極及びその製造方法
JPH09129126A (ja) 電界放出陰極及び電界放出型素子の製造方法
Fleming et al. Fabrication and testing of vertical metal edge emitters with well defined gate to emitter separation
Higa et al. Gated Si field emitter array prepared by using anodization
JP3625297B2 (ja) 微小真空管およびその製造方法
KR100288076B1 (ko) 버티컬웨지형에미터를구비하는전계방출소자의형성방법
JP3135131B2 (ja) 電子放出素子
JPH05225895A (ja) 電界放出陰極の作製方法
JPH0887958A (ja) 電界放出型冷陰極装置及びその製造方法
KR19990043845A (ko) 전계방출표시 소자의 필드 에미터 어레이 형성방법

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19940906

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

17Q First examination report despatched

Effective date: 19960808

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 69403940

Country of ref document: DE

Date of ref document: 19970731

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20110817

Year of fee payment: 18

Ref country code: FR

Payment date: 20110818

Year of fee payment: 18

Ref country code: DE

Payment date: 20110810

Year of fee payment: 18

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20120817

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20130430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20130301

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120817

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120831

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 69403940

Country of ref document: DE

Effective date: 20130301