EP0602281B1 - Dispositif de reséquencement pour un noeud d'un système de commutation de cellules - Google Patents
Dispositif de reséquencement pour un noeud d'un système de commutation de cellules Download PDFInfo
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- EP0602281B1 EP0602281B1 EP92203694A EP92203694A EP0602281B1 EP 0602281 B1 EP0602281 B1 EP 0602281B1 EP 92203694 A EP92203694 A EP 92203694A EP 92203694 A EP92203694 A EP 92203694A EP 0602281 B1 EP0602281 B1 EP 0602281B1
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- Prior art keywords
- cell
- memory
- address
- output
- waiting
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
- H04L49/105—ATM switching elements
- H04L49/108—ATM switching elements using shared central buffer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/565—Sequence integrity
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
Definitions
- the invention relates to a resequencing device for a node of a cell switching system. It concerns more particularly switching systems in which the cells have a variable length, each cell can be consisting of a variable number of sub-cells having a length fixed.
- European patent application No. 0 438 415 (Alcatel NV) describes a resequencing method of delaying each delay cell determined so that the total delay imposed by the switching network and by the resequencing has a substantially constant value for all cells, this value generally being chosen greater than the delay maximum that the switching network can create. If the total delay is chosen less than the maximum value of the delay that the switching network, the probability of a disturbance of the order initial is not zero, and is a function of the value chosen for the total delay. This known process has two variants.
- a first variant consists in: associating with each cell entering the switching network a time tag which indicates when the cell entered the network of switching; to extract the time label from each cell leaving the switching network; to store each cell leaving the network, until the time indicated by the label generator is equal to the time indicated in the time label of the cell, plus the total delay chosen; and then allow the emission of the cell on an output of the resequencing.
- the program is actually produced as soon as the output at which the cell and intended is available.
- the initial order of the cells is reconstructed without having to measure or estimate the transit delay of each cell across the switching network.
- the time provided by the time label generator must be available in a device located at the entrance to the network for assign time tags, and must be available simultaneously in a resequencing device located at the output of the network, to authorize the emission of each cell at a time suitable.
- this known method consists to associate with each cell leaving the network a label whose value is an estimate of the delay experienced by the cell during its transit through the network; and subject each cell to a additional delay of duration equal to the difference between the value predetermined total delay and the estimated value of the delay transit in the network, the latter being read in the label associated with each cell.
- This variant has the advantage of not not require a device associating time labels with cells arriving at the inputs of the switching network.
- the link memory provides the complete suite addresses, and therefore makes it possible to read in the buffer memory all the sub-cells of all cells with the time label considered. These cells are read in an order which is that defined by the links in the link memory, but this order has no of importance since all these cells have the same label and are addressed to the same output.
- Memory links is also used to chain in the same queue the different sequences of cell sub-cells with labels successive times, which ensures their emission in good order. This linking is achieved by matching by the memory of links the end of the sub-cell address sequence of a cell with the start of the cell sub-cell address sequence at then issue.
- This device has a first drawback which is that it does not ability to re-order cells arriving at the same entrance and being intended for several outputs, in particular when the same cell must be broadcast on several outputs.
- This impossibility follows from the operating principle of this known device, because that it needs to be stored in the address memory each time location, address start address, and address end of sequence of sub-cell addresses; and that it requires link all the sub-cells which will have to be linked subsequently be issued on the same output.
- the devices resequencing associated with the different outputs of a node therefore operate independently of each other.
- Each location of the address memory corresponds to a time unit of the generator which issues time tags. This unit of time is equal to the duration of a sub-cell.
- the time label generator did not not an infinite capacity. It therefore delivers label values identical periodically.
- Each location in the address memory is read with a constant period, at most equal to the period of time label generator. When reading a location, the constitution of the list must be completed, so that an end of list address can be validly read in the location considered. The period of the label generator therefore limit the number of sub-cells corresponding to this list, and finally limits the number of sub-cells that can have each cell.
- a first object of the invention is to propose a resequencing device allowing the diffusion of a cell from one input to several predetermined outputs, from the resequencing.
- a second object of the invention is to propose a resequencing device which can be adapted more easily for that it accepts cells composed of a large number of sub-cells.
- the device thus characterized is compatible with a diffusion because it is associated with all the outputs of a node and because the pending cell memory stores identifiers which can each contain several identities of recipient output.
- the identifier of a cell in wait can be stored in this memory without waiting for all the sub-cells of this cell were actually received by the knot.
- the first sub-cells of a cell can therefore be emitted on an output even before the last sub-cells have been received.
- Claims 2 to 4 relate to a method preferential embodiment of the device according to the invention.
- Inputs IN1, ..., INM receive length cells fixed or variable, each consisting of sub-cells all having the same number of bits and the same duration, this duration being called sub-cell period.
- the device according to the invention is particularly suitable for treating cells of variable length. These cells are switched in the switching network SW in routing all the sub-cells of the same cell by the same path and maintaining the continuity of the cell, that is to say without interweave sub-cells belonging to different cells. This allows you to assign a unique time label for the set of sub-cells constituting a cell. This label temporal indicates the time interval during which the first sub-cell of the considered cell is received at one of the inputs IN1, ..., INM.
- This label allows resequencing outgoing cells of the SW switching network: the first sub-cell is authorized to leave the node when its waiting time has expired, that is to say at during the time interval where the TSG generator indicates an hour equal to the sum of the value of the time label which was assigned to the cell, and a fixed value. But there is a additional condition for the cell to be emitted: the output at which this cell is intended for, must be available. Otherwise, it the cell in question must wait again until this output is available.
- Each sub-cell begins with two bits called field sub-cell control. In the first sub-cell of each cell, these two bits have the value 11 for example. In all other sub-cells, except the last one, these two bits have the value 00 for example. In the last sub-cell, these two bits have for value 01 for example.
- the first sub-cell further includes a field called cell control header. This field contains in particular the identity of the output which must emit this cell, or of several outputs in the case of a broadcast.
- the other bits of sub-cells transmit data.
- labels IC1, ..., ICM are to insert in the cell control field, of each cell, a label time provided by the TSG generator at the time when the first sub-cell of this cell is received by the node.
- This label time TSTP indicates the time interval during which will expire the cell's waiting time. It is determined according to the contents of the TSG counter at the moment this cell arrives, and as a function of the predetermined total delay that each cell must undergo.
- the modulo TSTPmax, of the counter is chosen equal to this predetermined total delay, the value of the TSTP time label is then numerically equal to the value supplied by the meter, because of the TSTPmax modulo.
- ILM When one of the input circuits IL1, ...., ILM receives a cell, it asks the BMMU management unit for free addresses for respectively store the sub-cells of this cell in the BM buffer memory.
- the unit of BMMU management includes a WRC write control circuit and read, storing the free addresses of the buffer memory BM at the as they are released by the emission of cells, and includes an SLM link memory storing all the addresses of locations, from the BM buffer, respectively storing all sub-cells of the same cell.
- Each memory location buffer has a capacity equal to a sub-cell.
- the BM buffer memory and the link memory SLM have the same set of addresses to facilitate implementation.
- the request issued by one of the input circuits IL1, ..., ILM is transmitted by the TDM1 bus, then by the processing of HP headers up to the BMMU management unit. This last assigns to the sub-cells of the cell considered a sequence of free locations in the BM buffer memory. A series of addresses designating these free locations is provided by the WRC circuit. Of links between the addresses of this suite are formed by memorizing this sequence of addresses in the SLM link memory, at addresses consecutive.
- the BMMU management unit supplies the processing circuit of headers, HP, an FSA value which is the first address of this sequence of addresses of locations in the BM buffer memory.
- the FSA address is retransmitted on the third output of the HP circuit. This address FSA is stored in FSAM address memory in a location free whose address is provided by the output of the CU unit.
- This FSA address will allow later to find all sub-cells of this cell in the BM buffer: Using this FSA address, it is possible to read, in the SLM link memory, the address of a second sub-cell in the BM buffer. Then, with the address of this second sub-cell, it is possible to read in the memory of SLM links the address of a third sub-cell in the buffer BM. he it is therefore possible to successively obtain the addresses of all the sub-cells of the same cell from a single FSA address. These addresses then make it possible to read the sub-cells themselves, in the BM buffer.
- the extracted HP circuit in the control field of cell of the first sub-cell of each cell received, the field containing the TSTP time label and a field containing the identity the output, or outputs, OU1, ..., OUN, on which the cell must be issued. It provides the first entry to the unit CU command an identifier, called cell pending, which is made up of this information.
- the operation of the CU command is triggered by the output circuits OL1, ..., OLN when one of these output circuits is available, i.e. when it finishes emitting a cell. It sends on the RQB bus a message noted IDL containing the identity of the output which is available, and addressed to the control unit CU. The CU control unit determines then which cell will be emitted on this output. CU unit sends, to the requesting output circuit, the FSA 'address of a location, from the BM buffer, containing the first sub-cell of a cell. The output circuit then requests the buffer BM and its BMMU management unit, to provide it with the complete suite of sub-cells of this cell. Then he emits it on his exit.
- the first input of the CU control unit which receives a pending cell identifier provided by the HP circuit of processing of headers, is connected to a wd entry for writing data, from VIM memory.
- the second input of the control unit CU which receives the address FSA 'provided by the data output of the FSAM memory, is connected to the RQB bus by an interface not shown.
- the RBQ bus is also connected by this interface to a first input common queuing circuits, SNL1, ..., SNLN, to provide an IDL signal to one of these circuits when the output circuit correspondent, OL1, ..., OLN, is available to send a cell.
- the pending cell memory, VIM includes addition: an address input, ad, connected to an output of the FMM management; and a so-called comparison input, ci, connected to a first output of the transfer control circuit TC.
- VIM memory compare this binary word with the binary words contained respectively in its memory locations.
- VIM memory provides a bit of value 1 on the output corresponding to this memory location. If the comparisons give several positive results, VIM memory provides a bit of value 1 on each of the outputs corresponding to the locations memories where the result is positive.
- the function of the AC arbitration and coding circuit is to code each of these signals as a binary word.
- a first output of the circuit AC therefore provides a binary word NA whose value is the address of the memory location considered.
- the first one output of the AC arbitration and coding circuit is connected to the input of data from the DMX demultiplexer and to an input of the management circuit FMM. If the comparisons yield several positive results, the AC circuit codes them successively, in order of addresses decreasing, for example.
- AC circuit has a second output which supplies, to an input of the transfer control circuit TC, and to a second common input for the SLN1 queuing circuits, ..., SNLN, a logic signal C when there is at least one positive result, and which maintains it until the AC circuit has supplied all the addresses corresponding to these positive results. It also has a third output, connected to a third input common to all SNL1, ..., SNLN queuing circuits to provide them with a signal QR logic consisting of an impulse for each address provided by the AC circuit.
- a second output of the transfer control circuit TC is connected to the control input of the DMX demultiplexer and to a fourth common input of all SNL1 queuing circuits, ..., SNLN.
- the MUX multiplexer has a first input connected to a common output of the FFO1, ..., FFON arbitration circuits; a second input connected to the output of the address management circuit, FMM; an output constituting the output of the control unit CU, and linked to the entry ad of writing and reading address in the FSAM memory; and a control input, not shown, which is connected to an output of a not shown sequencer which provides control signals to all the elements constituting the unit of CU command.
- the DMX demultiplexer has N connected outputs respectively to the write address entries wa of the memories of queuing QC1, ..., QCN.
- Each of the queuing memories, QC1, ..., QCN has: a comparison entry, ci, and an entry writing data, wd, which are respectively connected to two outputs of the queuing circuit SNL1, ..., SNLN, which corresponds to the memory considered.
- the LWSN and LRSN counters each have an input of control and an output linked respectively to an output and a SNM circuit input.
- the SMN circuit has four inputs which constitute respectively the first, the second, the third, and the fourth input to the queuing circuit; and has two outputs which respectively constitute the two outputs of the queuing.
- the HP header processing circuit provides a pending cell identifier TSTP-OA, at entry wd writing data from VIM memory.
- This identifier includes: a field, TSTP, which is a time label indicating the time interval during which the waiting period will expire; and a field, OA, designating the recipient output of the cell.
- the FMM circuit for managing the addresses of the VIM memories and FSAM provides an available FA address at the address entry write, ad, from VIM memory, and at address entry, ad, from FSAM memory, via the MUX multiplexer.
- the TSTP-OA identifier and the address of the first sub-cell, FSA, are therefore entered respectively in the VIM and FSAM memories at the same address.
- the cell timeout is equal to an integer multiple of the sub-cell period.
- the first output of the TC transfer command provides a TSTP'-OA 'identifier, known as cell to be queued, which consists of: the TSTP 'value of time tags of all cells including timeout expires during the current sub-cell period; and of the identity OA 'of a single output of the node.
- Each cell identifier to be queued can possibly identify several cells which are to be emitted on the same exit and whose waiting times expire during the same sub-cell period.
- the expiration of its waiting period gives permission to a cell to be queued, under a symbolic form in the tail memory corresponding to the output recipient. But it is not yet authorized to be issued effectively.
- the TC circuit includes a modulo TSTPmax counter which is incremented at each sub-cell period and which is initialized by such that the TSTP 'value it provides is equal to the value of the current time label minus a predetermined delay, equal to example of the maximum transfer time of a cell in the network SW switch.
- the value of the modulo TSTPmax is taken equal to the duration maximum transfer of a cell in the switching network SW, which means that the value TSTP 'is numerically equal to the value of the current time label, TSTP, which allows to use the same counter for the TSG label generator current time and for the TSTP counter 'in the TC transfer command.
- the control circuit TC includes a second counter. For each sub-cell period, it provides N values of OA '. Thus the circuit TC determines N cell identifiers to be put at the tail, TSP'-OA ', made up of the same TSTP' value and N values the output address OA 'which is taken successively equal to 1, ..., N, for example. The value of this exit address is provided simultaneously on the second output of the TC circuit to be applied at the DMX demultiplexer control input and at the fourth input common to all SNL1, ..., SNLN queuing circuits.
- Each TSTP'-OA 'identifier is applied to the input of comparison of the VIM memory to find, if there are any, pending cell identifiers, TSTP-OA, corresponding to this cell identifier to queue. If the comparisons performed by the VIM memory between the TSTP'-OA 'identifier and the TSTP-OA identifiers it contains give results positive, there is a logic signal of value 1 on certain outputs of this memory. For example, the outputs corresponding to addresses AA1, AA2, AA3 of this memory each provide a signal which indicates that these addresses contain TSTP-OA identifiers of Pending cells with the value of the identifier TSTP'-OA 'of cells to queue.
- the AC arbitration and coding circuit receives these signals and first provides a binary word NA having the value AA1, to the DMX demultiplexer data input and at the FMM circuit input address management. It also supplies a logic signal C to the transfer control TC circuit to indicate that at least one cell was found, and it provides a logical QR signal to SNL1, ..., SNLN queuing circuits to ask them to put the cell that was found at the tail.
- OA 'address is provided simultaneously with the queuing circuits, SNL1, ..., SNLN so to validate only that corresponding to the recipient output of the cell found.
- the circuit AC supplies an address NA having the value AA2 in now signal C, and renewing the QR signal requesting a queuing.
- the AC circuit provides an address NA equal to AA3, maintaining the C signal and renewing the QR signal to request a tail bet again.
- the AC circuit removes the signal C to indicate to the TC circuit that all cells found have been queued, and therefore it is possible increment the value of the output address OA '. All of these queuing operations for N values of the output address OA 'must be carried out during the period of sub-cell, so that you can increment the value of TSTP 'at same rate as incrementing the values of the time label current TSTP.
- the FMM circuit for managing the addresses of VIM and FSAM memories receives each value from the address NA, for the store as an available address.
- the serial number SNi is written to address AA1 in the memory queue corresponding to the exit address OA '. Then these operations are repeated to process the following address: AA2. The same number SNi is written to address AA2 in the same tail memory. Then these operations are repeated to process the following address: AA3. Thus the order number SNi is written in the same memory of queue at address AA3.
- the AC circuit When there are no cells to queue, the AC circuit does not provides no C signal and no QR signal.
- the value of the address NA supplied by the AC circuit is null, but without significance. She is not taken into account since there is no signal C of positive result, no QR signal for queuing request.
- the output circuit OU1, ..., OUN whose output is available sends a message on the bus RQB.
- An IDL signal reaches the queuing circuit, SNL1, ..., SNLN corresponding to the available output.
- the IDL signal controls the number management circuit, SNM, to increment by one unit, and read, the contents of the last read number counter, LRSN.
- This content constitutes a number SN 'which will be sought in the memory queuing QC1, ..., QCN corresponding to the available output.
- the uniform incrementation of this SN 'number ensures that the cells are retrieved in the order in which they were numbered at the time of queuing, i.e. in the order defined by the values TSTP ', which is the chronological order of reception of cells by the node.
- This SN 'number is provided at the comparison entry ci of this queuing memory.
- This memory provides a logic signal on one or more of its outputs, depending on whether there are one or more locations of this memory which contains a number identical to the number searched: SN '.
- the associated FFO1, ..., FFON arbitration circuit to the considered memory provides a binary word whose value is successively equal to the rank of each of the outputs of this memory, that provide a signal.
- the values in these rows represent the NA 'addresses of the locations, from the tail memory, containing the number searched. These addresses NA 'are successively restored in the order of decreasing ranks, for example.
- the circuit arbitration successively provides the values AA1, AA2, AA3 of the address NA 'at the first input of the MUX multiplexer. This last transmits these addresses to the FSAM memory to read successively there three address values of first sub-cell, FSA '.
- Each value of address FSA ' is transmitted by the RQB bus to the output circuit OL1, ..., or OLN having sent the message containing the IDL signal indicating that an output is available.
- the output circuit retransmits these first cell address values, FSA ', via the bus TDM2, to the management unit BMMU of the buffer memory BM for reading in this buffer all the sub-cells of the three cells corresponding to the three FSA 'address values. Then these sub-cells are transmitted via the TMD2 bus to this output circuit, which transmits them on its way out.
- the operation of this exemplary embodiment can be slightly modified to allow the diffusion of a cell towards several outings.
- the single exit address OA is replaced by a binary word OM comprising a number of bits equal to the number N of outputs of the node.
- Each recipient output from the cell is indicated by a value 1 and each non-intended output is indicated by a value 0, for example.
- the pending cell memory, VIM stores pending cell identifiers TSTP-OM instead of TSTP-OA identifiers.
- VIM memory has a comparison entry ci, but it works slightly differently from the VIM memory described above because the comparison must relate to the TSTP 'field and to the single bit not zero in OM '.
- the N-1 other bits in OM 'and the N-1 other bits corresponding in the OM field of the TSTP-OM identifiers stored should not be compared.
- the OM field bits in each word TSTP - OM must be masked by the bits of the OM 'field of TSTP'-OM' before comparing the identifier TSTP'-OM 'and each pending cell identifier, TSTP- OM, stored in VIM memory.
- the TC transfer control circuit is modified to provide cell identifiers to queue, TSTP'-OM ', in which field TSTP 'is still the identity of a time interval where a timeout expires, but where OM 'is a word of N bits, among which a single bit has the value 1.
- the rank of this bit indicates a single output, for which the TC circuit searches for cells with line up.
- the device according to the invention is applicable to cells of fixed length or to cells comprising a variable number of sub-cells each having a fixed length.
- the capacity of the LWSN and LRSN counters, providing the order numbers SN and SN ' is greater than the maximum number of sub-cells that a cell can contain , increased by the number of sub-cell periods corresponding to the maximum transit time in the switching network SW.
- An alternative embodiment consists in assigning a label TSTP time to each cell leaving the SW network, instead of assign it as input to the SW network.
- the TSG generator of time labels is different. It still has a clock defining time intervals of constant duration equal to one sub-cell period; and a modulo TSTP counter max. But he further includes: a circuit for estimating the transit time of each cell through the SN network; a circuit to subtract this estimate to the content of the counter; and a circuit to add the result is the duration of the total delay that each cell must undergo.
- the result of this calculation constitutes the value of the TSTP label indicating the time interval at which the waiting period for the cell. It can be used exactly as the label value TSTP allocated at the input of the SW network, as described above. The realization of these circuits is within the reach of Man art.
- the time unit is preferably chosen equal to the period of sub-cell because the duration of each cell is at least equal to one sub-cell period, but it is possible to use a unit of smaller time.
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Description
- un générateur de premières étiquettes temporelles, fournissant une valeur incrémentée d'une unité pour chaque intervalle de temps correspondant à une sous-cellule, avec une durée de cycle au moins égale au retard total prédéterminé pour retarder uniformément toutes les cellules;
- une mémoire tampon ayant une entrée couplée à une entrée du dispositif de reséquencement, et ayant une sortie couplée à une sortie du dispositif de reséquencement; chaque emplacement de cette mémoire ayant une capacité égale à une sous-cellule;
- un circuit de gestion de cette mémoire tampon, pour fournir des adresses d'emplacements libres dans cette mémoire tampon et pour y stocker respectivement les sous-cellules de chaque cellule reçue par le dispositif de reséquencement;
- un pointeur de lecture-écriture associé à la mémoire tampon;
- une mémoire d'adresses ayant des emplacements correspondant respectivement aux diverses valeurs possibles de l'étiquette temporelle; chaque emplacement de cette mémoire d'adresses stockant un pointeur de début de liste et un pointeur de fin de liste qui sont respectivement les adresses, dans la mémoire tampon, de la première et de la dernière sous-cellule d'une suite contenant toutes les cellules ayant une même étiquette temporelle;
- une mémoire de liens, ayant le même ensemble d'adresses que la mémoire tampon, pour mémoriser des liens entre les adresses de toutes les sous-cellules ayant une même étiquette temporelle, et pour mémoriser des liens entre les adresses de sous-cellules appartenant à des cellules devant être émises successivement;
- un pointeur d'écriture associé à cette mémoire d'adresses pour stocker dans chaque emplacement la première adresse et la dernière adresse d'une liste d'adresses d'emplacements de la mémoire tampon, contenant toutes les sous-cellules de toutes les cellules ayant la même étiquette temporelle;
- un pointeur de lecture associé à la mémoire d'adresses, ayant un fonctionnement cyclique, pour lire successivement les contenus des emplacements de cette mémoire d'adresses, afin de lire des sous-cellules dans la mémoire tampon à des adresses correspondant à des étiquettes temporelles croissant de manière régulière.
- une mémoire tampon pour stocker toutes les sous-cellules de chaque cellule reçue par le dispositif de reséquencement;
- une mémoire d'adresses pour mémoriser l'adresse, de la mémoire tampon, contenant la première sous-cellule de chaque cellule;
- des moyens pour retrouver l'adresse, de la mémoire d'adresses, contenant la première sous-cellule d'une cellule, lorsque le délai d'attente de cette dernière a expiré, et qu'une sortie qui doit émettre cette cellule est disponible;
- une mémoire dite de cellules en attente, du type accessible par son contenu, pour mémoriser un identificateur dit de cellule en attente, lorsqu'une cellule est stockée dans la mémoire tampon; cet identificateur étant stocké à une adresse identique à celle où est stockée, dans la mémoire d'adresses, l'adresse FSA de la première sous-cellule; et cet identificateur étant constitué : d'une étiquette temporelle identifiant un intervalle de temps au cours duquel expire le délai d'attente de cette cellule, et de l'identité d'au moins une sortie sur laquelle elle doit être émise;
- des moyens pour retrouver, dans la mémoire de cellules en attente, l'identificateur de chaque cellule lorsque son délai d'attente expire, et fournir, pour chaque identificateur retrouvé, l'adresse, de la mémoire de cellules en attente, qui contient cet identificateur retrouvé;
- des mémoires dites de queue, associées respectivement aux sorties du noeud, et accessibles par leur contenu, pour mémoriser un numéro d'ordre pour chaque cellule qui est destinée à la sortie associée à la mémoire considérée;
- des moyens pour déterminer et inscrire dans une mémoire de queue un numéro d'ordre, à l'adresse fournie par les moyens pour retrouver l'identificateur de chaque cellule lorsque son délai d'attente expire;
- des moyens pour retrouver, dans un ordre croissant, chaque numéro mémorisé dans la mémoire de queue d'une sortie, lorsque cette sortie devient disponible; et pour restituer l'adresse, de cette mémoire de queue, contenant le numéro retrouvé;
- des moyens, pour lire une adresse de première sous-cellule, dans la mémoire d'adresses, à l'adresse restituée par les moyens pour retrouver chaque numéro.
- la figure 1 représente le schéma synoptique d'un exemple de réalisation du dispositif selon l'invention, raccordé à un réseau de commutation, pour constituer un noeud d'un système de commutation de cellules;
- la figure 2 représente un schéma synoptique plus détaillé de cet exemple de réalisation.
- M circuits étiquetteurs IC1,...,ICM, ayant chacun : une entrée reliée respectivement à une entrée IN1,...,INM du noeud, une sortie reliée respectivement à l'une des N entrées du réseau de commutation SW, et une entrée commune;
- M circuits d'entrée IL1,...,ILM ayant chacun : une entrée reliée respectivement à l'une des M sorties du réseau de commutation SW, et une sortie reliée à un bus TDM1 à multiplexage temporel;
- un circuit HP de traitement des en-têtes de cellule, ayant une première entrée reliée au bus TDM1;
- une unité de commande CU qui sera détaillée plus loin et qui comporte une première entrée reliée respectivement à une première sortie du circuit HP de traitement des en-têtes;
- un générateur d'étiquettes temporelles, TSG, ayant une sortie reliée à l'entrée commune des circuits étiquetteurs IC1,...,ICM, ; ce générateur étant constitué d'une horloge et d'un compteur, non représentés, pour fournir une valeur d'étiquette temporelle incrémentée d'une unité pour chaque intervalle de temps correspondant à une sous-cellule, de O à TSTPmax, modulo TSTPmax;
- une mémoire tampon BM associée à une unité de gestion de mémoire tampon BMMU, cet ensemble ayant : une entrée reliée à une deuxième sortie du circuit HP de traitement d'en-têtes, une sortie reliée à une deuxième entrée du circuit HP, et une entrée-sortie reliée à un bus TDM2 à multiplexage temporel;
- une mémoire FSAM appelée mémoire d'adresses, ayant : une entrée de données, di, reliée à une troisième sortie du circuit HP, une entrée d'adresse ad reliée à une sortie de l'unité CU, et une sortie do reliée à une deuxième entrée de l'unité CU;
- N circuits de sorties OL1,...,OLN ayant chacun : une entrée-sortie reliée au bus TDM2, une sortie reliée respectivement à l'une des sorties OU1,...,OUN du noeud, et une entrée-sortie reliée à un bus RQB, lui-même relié à une entrée-sortie de l'unité de commande CU.
- une mémoire VIM, dite de cellules en attente, du type accessible par le contenu, qui a le même ensemble d'adresses que les mémoires FSAM et BM, et qui possède une sortie d'un bit pour chaque emplacement de mémoire, le nombre d'emplacements étant choisi en fonction du nombre N de sorties du noeud, et du délai d'attente moyen des cellules dans la mémoire tampon BM;
- un circuit d'arbitrage et de codage, AC, ayant une pluralité d'entrées reliées respectivement aux sorties de la mémoire VIM;
- un multiplexeur DMX ayant : une entrée de données, N sorties, et une entrée de commande;
- un circuit logique TC, dit de commande de transfert de cellules;
- un multiplexeur MUX ayant : deux entrées de données, une sortie, et une entrée de commande non représentée;
- un circuit logique FMM dit de gestion des adresses des mémoires VIM et FSAM;
- N mémoires de queue, QC1, ..., QCN, du type accessible par le contenu, ayant le même ensemble d'adresses que la mémoire VIM, et chaque mémoire de queue ayant une sortie d'un bit pour chaque emplacement de mémoire;
- N circuits d'arbitrage, FFO1, ..., FFON, respectivement associés au N mémoires QC, ..., QCN et ayant chacun une pluralité d'entrées respectivement connectées aux sorties de l'une des mémoires QC1, ..., QCN;
- N circuits logiques dits de mise en queue, SNL1, ..., SNLN, respectivement associés au N mémoires QC1, ..., QCN.
- un compteur LWSN dit de dernier numéro écrit;
- un compteur LRSN dit de dernier numéro lu;
- et un circuit logique SNM de gestion de numéros.
6, 7, 8) trois valeurs successives de l'adresse NA, qui sont nulles, et qui ne sont pas accompagnées du signal QR, ni du signal C.
le dispositif selon l'invention est applicable à des cellules de longueur fixe ou à des cellules comprenant un nombre variable de sous-cellules ayant chacune une longueur fixe. Pour éviter tout déséquencement de cellule, et toute perte de cellule, il est nécessaire que la capacité des compteurs LWSN et LRSN, fournissant les numéros d'ordre SN et SN', soit supérieure au nombre maximal de sous-cellules que peut comporter une cellule, augmenté du nombre de périodes de sous-cellules correspondant au temps de transit maximal dans le réseau de commutation SW.
Claims (4)
- Dispositif de reséquencement (RU) pour un noeud d'un système de commutation de cellules, chaque cellule étant constituée d'un nombre variable de sous-cellules ayant une longueur fixe, ce noeud comportant un réseau de commutation (SW) transmettant les cellules avec des premiers retards variables, toutes les sous-cellules d'une même cellule subissant un même premier retard; ce dispositif de reséquencement (RU) comportant des moyens pour stocker toutes les cellules ayant été transmises à travers le réseau de commutation, puis les émettre sur au moins une sortie du dispositif de reséquencement, après l'expiration de divers délais d'attente constituant des seconds retards tels que, pour chaque cellule, la somme du premier et du second retard est égale à une valeur prédéterminée sensiblement identique pour toutes les cellules; ces moyens comportant :une mémoire tampon (BM) pour stocker toutes les sous-cellules de chaque cellule reçue par le dispositif de reséquencement;une mémoire d'adresses (FSAM) pour mémoriser l'adresse (FSA), de la mémoire tampon, contenant la première sous-cellule de chaque cellule;des moyens (TSG, IC1, ..., ICM, CU) pour retrouver l'adresse (FSA'), de la mémoire d'adresses, contenant la première sous-cellule d'une cellule, lorsque le délai d'attente de cette dernière a expiré, et qu'une sortie qui doit émettre cette cellule est disponible;une mémoire (VIM) dite de cellules en attente, du type accessible par son contenu, pour mémoriser un identificateur dit de cellule en attente (TSTP-OA), lorsqu'une cellule est stockée dans la mémoire tampon (BM); cet identificateur étant stocké à une adresse (FA) identique à celle où est stockée, dans la mémoire d'adresses (FSAM), l'adresse FSA de la première sous-cellule; et cet identificateur étant constitué : d'une étiquette temporelle (TSTP) identifiant un intervalle de temps au cours duquel expire le délai d'attente de cette cellule, et de l'identité (OA; OM) d'au moins une sortie sur laquelle elle doit être émise;des moyens (TC, AC) pour retrouver, dans la mémoire de cellules en attente, (VIM), l'identificateur (TSTP-OA) de chaque cellule lorsque son délai d'attente expire, et fournir, pour chaque identificateur retrouvé, l'adresse (NA), de la mémoire de cellules en attente (VIM) qui contient cet identificateur retrouvé;des mémoires (QC1, ..., QCN) dites de queue, associées respectivement aux sorties du noeud, et accessibles par leur contenu; pour mémoriser un numéro d'ordre pour chaque cellule qui est destinée à la sortie associée à la mémoire considérée;des moyens (DMX, SNL1, ..., SNLN) pour déterminer et inscrire dans une mémoire de queue un numéro d'ordre, à l'adresse (NA) fournie par les moyens (TC, AC) pour retrouver l'identificateur de chaque cellule lorsque son délai d'attente expire;des moyens (SNL1, ..., SNLN, FFO1, ..., FFON) pour retrouver, dans un ordre croissant, chaque numéro (SN') mémorisé dans la mémoire de queue d'une sortie, lorsque cette sortie devient disponible; et pour restituer l'adresse (NA'), de cette mémoire de queue, contenant le numéro retrouvé (SN');des moyens (MUX), pour lire une adresse (FSA') de première sous-cellule, dans la mémoire d'adresses (FSAM), à l'adresse restituée par les moyens (SNL1, ..., SNLN, LRSN) pour retrouver chaque numéro.
- Dispositif selon la revendication 1, caractérisé en ce que les moyens pour retrouver, dans la mémoire de cellules en attente (VIM), l'identificateur de chaque cellule lorsque son délai d'attente expire, et fournir pour chaque identificateur retrouvé, chaque adresse (NA), de la mémoire de cellule en attente (VIM), qui contient cet identificateur retrouvé, comportent :des moyens (TC) pour fournir à une entrée de comparaison de la mémoire de cellules en attente (VIM), pour chaque intervalle de temps correspondant à un délai d'attente qui expire, une suite d'identificateurs (TSTP'-OA') dits de cellules à émettre, constitués chacun de l'identité (TSTP') de l'intervalle de temps en cours, et de l'identité (OA') d'une sortie unique du noeud; cette suite étant constituée avec les identités (OA') de toutes les sorties du noeud;des moyens (AC) couplés à des sorties de la mémoire de cellules en attente (VIM) pour fournir successivement chaque adresse (NA), de la mémoire de cellules en attente, contenant un identificateur retrouvé.
- Dispositif selon la revendication 1, caractérisé en ce que les moyens pour déterminer, et inscrire dans une mémoire de queue (QC1, ..., QCN) un numéro d'ordre (SN) comportent, pour chaque sortie du noeud, un compteur (LWSN) fournissant un numéro d'ordre (SN) qui est incrémenté d'une unité lorsqu'au moins un identificateur de cellule en attente est retrouvé dans la mémoire de cellules en attente (VIM), pour un intervalle de temps donné et une sortie donnée.
- Dispositif selon la revendication 1, caractérisé en ce que les moyens pour retrouver, dans un ordre croissant, chaque numéro (SN') mémorisé, comportent, pour chaque sortie du noeud, un compteur (LRSN) fournissant un numéro d'ordre à retrouver (SN') qui est incrémenté d'une unité lorsque cette sortie devient disponible, ce numéro d'ordre à retrouver (SN') étant appliqué à une entrée de comparaison de la mémoire de queue (QC1, ..., QCN) associée à cette sortie.
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP92203694A EP0602281B1 (fr) | 1992-11-30 | 1992-11-30 | Dispositif de reséquencement pour un noeud d'un système de commutation de cellules |
AT92203694T ATE211337T1 (de) | 1992-11-30 | 1992-11-30 | Einrichtung zum wiederherstellen der richtigen zellenfolge in einem knoten eines zellenvermittlungssystems |
DE69232312T DE69232312T2 (de) | 1992-11-30 | 1992-11-30 | Einrichtung zum Wiederherstellen der richtigen Zellenfolge in einem Knoten eines Zellenvermittlungssystems |
ES92203694T ES2167315T3 (es) | 1992-11-30 | 1992-11-30 | Dispositivo de resecuenciamiento para un nudo de un sistema de conmutacion de celulas. |
CA002108809A CA2108809C (fr) | 1992-11-30 | 1993-10-20 | Dispositif de resequencement pour un noeud d'un systeme de commutation de cellules |
US08/152,594 US5383182A (en) | 1992-11-30 | 1993-11-12 | Resequencing device for a node of a cell switching system |
AU50622/93A AU669747B2 (en) | 1992-11-30 | 1993-11-12 | A re-sequencing unit |
JP5297074A JPH0779234A (ja) | 1992-11-30 | 1993-11-26 | セル切替えシステムのノードのための再順序づけ装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP92203694A EP0602281B1 (fr) | 1992-11-30 | 1992-11-30 | Dispositif de reséquencement pour un noeud d'un système de commutation de cellules |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0602281A1 EP0602281A1 (fr) | 1994-06-22 |
EP0602281B1 true EP0602281B1 (fr) | 2001-12-19 |
Family
ID=8211085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP92203694A Expired - Lifetime EP0602281B1 (fr) | 1992-11-30 | 1992-11-30 | Dispositif de reséquencement pour un noeud d'un système de commutation de cellules |
Country Status (8)
Country | Link |
---|---|
US (1) | US5383182A (fr) |
EP (1) | EP0602281B1 (fr) |
JP (1) | JPH0779234A (fr) |
AT (1) | ATE211337T1 (fr) |
AU (1) | AU669747B2 (fr) |
CA (1) | CA2108809C (fr) |
DE (1) | DE69232312T2 (fr) |
ES (1) | ES2167315T3 (fr) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0602282B1 (fr) * | 1992-11-30 | 2002-01-23 | Alcatel | Dispositif de reséquencement pour un noeud d'un système de commutation de cellules |
CA2149006C (fr) * | 1994-06-07 | 2003-07-15 | Cecil Henry Bannister | Systeme synchrone de transmissions de paroles et de donnees |
KR100205368B1 (ko) * | 1995-10-16 | 1999-07-01 | 구자홍 | 디지탈 자기기록 매체의 전송 비트스트림의 기록/재생장치 및 그 제어방법 |
GB2308959A (en) * | 1995-12-29 | 1997-07-09 | Ericsson Telefon Ab L M | Data switching apparatus with fair queuing |
JP3159055B2 (ja) * | 1996-05-16 | 2001-04-23 | ヤマハ株式会社 | 通信システム |
US5867488A (en) * | 1996-06-30 | 1999-02-02 | Motorola, Inc. | Digital multi-channel simulcast system with centralized timestamping device |
US6226687B1 (en) * | 1996-09-05 | 2001-05-01 | Nortel Networks Limited | Method and apparatus for maintaining an order of data packets |
US6094430A (en) * | 1997-09-24 | 2000-07-25 | Xylan Corporation | Switching fabric for a digital traffic switch |
US6246684B1 (en) * | 1997-12-24 | 2001-06-12 | Nortel Networks Limited | Method and apparatus for re-ordering data packets in a network environment |
US6782056B1 (en) * | 1999-08-03 | 2004-08-24 | Sony Corporation | DSS packet reordering function |
US7095744B2 (en) * | 2000-11-22 | 2006-08-22 | Dune Networks | Method and system for switching variable sized packets |
KR100419609B1 (ko) * | 2001-10-29 | 2004-02-25 | 주식회사 케이티 | 스위칭시스템의 셀/패킷 스케쥴링 장치 |
US7372864B1 (en) | 2002-08-01 | 2008-05-13 | Applied Micro Circuits Corporation | Reassembly of data fragments in fixed size buffers |
US7558890B1 (en) | 2003-12-19 | 2009-07-07 | Applied Micro Circuits Corporation | Instruction set for programmable queuing |
JP4867778B2 (ja) * | 2007-05-07 | 2012-02-01 | 株式会社日立製作所 | 分散型スイッチファブリックシステム |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991002419A1 (fr) * | 1989-08-09 | 1991-02-21 | Alcatel N.V. | Systeme de remise en sequence pour n×ud de commutation |
EP0441787B1 (fr) * | 1989-08-09 | 1994-12-07 | BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap | Element de commutation de communications servant a la transmission de cellules divisees en sous-cellules |
IT1237302B (it) * | 1989-11-30 | 1993-05-27 | Vinicio Vercellone | Elemento base per la rete di connessione di un nodo di commutazione veloce di cella. |
DE3942977A1 (de) * | 1989-12-23 | 1991-06-27 | Standard Elektrik Lorenz Ag | Verfahren zum wiederherstellen der richtigen zellfolge, insbesondere in einer atm-vermittlungsstelle, sowie ausgangseinheit hierfuer |
CA2059027C (fr) * | 1991-01-08 | 1996-07-02 | Toshiya Aramaki | Systeme de commutation a etage d'entree a distribution de paquets horodates et a etage de sortie a ordonnancement de paquets |
JPH0630022A (ja) * | 1992-07-10 | 1994-02-04 | Matsushita Electric Ind Co Ltd | セル転送方法およびセル受信装置 |
-
1992
- 1992-11-30 EP EP92203694A patent/EP0602281B1/fr not_active Expired - Lifetime
- 1992-11-30 DE DE69232312T patent/DE69232312T2/de not_active Expired - Fee Related
- 1992-11-30 ES ES92203694T patent/ES2167315T3/es not_active Expired - Lifetime
- 1992-11-30 AT AT92203694T patent/ATE211337T1/de not_active IP Right Cessation
-
1993
- 1993-10-20 CA CA002108809A patent/CA2108809C/fr not_active Expired - Fee Related
- 1993-11-12 AU AU50622/93A patent/AU669747B2/en not_active Ceased
- 1993-11-12 US US08/152,594 patent/US5383182A/en not_active Expired - Fee Related
- 1993-11-26 JP JP5297074A patent/JPH0779234A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
ATE211337T1 (de) | 2002-01-15 |
DE69232312T2 (de) | 2002-07-18 |
AU5062293A (en) | 1994-06-09 |
CA2108809A1 (fr) | 1994-05-31 |
AU669747B2 (en) | 1996-06-20 |
JPH0779234A (ja) | 1995-03-20 |
CA2108809C (fr) | 2000-01-18 |
US5383182A (en) | 1995-01-17 |
DE69232312D1 (de) | 2002-01-31 |
ES2167315T3 (es) | 2002-05-16 |
EP0602281A1 (fr) | 1994-06-22 |
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