EP0591405A1 - Multiprocessor array - Google Patents
Multiprocessor arrayInfo
- Publication number
- EP0591405A1 EP0591405A1 EP92914447A EP92914447A EP0591405A1 EP 0591405 A1 EP0591405 A1 EP 0591405A1 EP 92914447 A EP92914447 A EP 92914447A EP 92914447 A EP92914447 A EP 92914447A EP 0591405 A1 EP0591405 A1 EP 0591405A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- bus
- coupled
- processor
- asynchronously
- cache memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
Definitions
- This invention relates to computer systems, and more particularly to techniques for arranging central processor means thereof including techniques for arranging a single input/output channel for several processors in a single system.
- An object hereof is to address at least some of the foregoing problems and to provide at least some of the mentioned, and other, advantages.
- Fig. 1 is a generalized simplified block diagram of a preferred embodiment
- Fig. 2 is a -more detailed version of this embodiment, while Fig. 2A, 2B, 2C are enlargements of portions of Fig. 2. .
- the present invention comprises a multiprocessor system with processors coupled, by a common bus arrangement, as is an input/output adapter (hereinafter "I/O") to common memory.
- I/O input/output adapter
- a “main memory” is coupled, by the common bus arrangement, to the several central processors (hereinafter “CPUs”)- the common bus thus being shared between such CPUs.
- CPUs central processors
- One of the processors is a base processor coupled to the I/O adapter (by the common bus arrangement) .
- the I/O adapter is the only one for the system, and is coupled, by output bus means, to I/O devices, and by a ring coupling to the base processor.
- the I/O adapter, and each CPU has its own dedicated cache memory.
- Each cache memory is preferably operated as a "write-back" cache which updates "main memory” only upon a CPU initiated "read miss” or "write miss” (on a dirty cache line) .
- Fig. 1 particularly represents a generalized, simplified block diagram of a multiple microprocessor computer system along the foregoing lines, being characterized by a base CPU 1 (central processing unit, e.g., preferably using Intel 80486 microprocessor chip), preferably coupled to its own associated private cache memory unit 1-C and, thence, via a connect • channel 8, to a single, shared MP (multiprocessor) bus 21.
- CPU 1 central processing unit, e.g., preferably using Intel 80486 microprocessor chip
- CPU 1 may preferably comprise a single processor card (printed circuit board—including cache 1-C) and that the entire computer system preferably involves a number of other similar (application) processor units (up to five, here), such as like CPU/cache units 23, 25—all similar to CPU 1/cache 1-C and linked by the shared MP bus 21.
- each CPU may be understood as connected to its cadhe memory to accommodate direct transmission there between (cf. requests, data).
- CPU 1 is also, coupled, in "O-Ring fashion” (see further below) to the I/O adapter (channel) 5 (input-output control unit—the only one in the system, preferably on a single board) which is, in turn, coupled to I/O bus means (preferably to a SCSI bus " 30 and an EISA bus 40, as illustrated, there being an associated EISA chip set on I/O card 5, along with an associated private cache memory 5-C).
- I/O unit 5 (with its cache 5-C) is coupled to MP bus 21 via the common single channel (connector) 8 that also couples CPU 1 (and its cache 1-C) to MP bus 21.
- This O-Ring coupling logically ties CPU 1 and I/O 5 together (exclusively) in a ring-like configuration, for bilateral, asynchronous intercommunication.
- CPU 1 and 1/0-5 are so connected in "O-Ring" fashion ("O-Ring architecture") to "talk bilaterally and asynchronously” over two inter- coupling ⁇ (channels).
- I/O register R-0 are provided on the base and application processor units to facilitate communication with, and between, the processors.
- This O-Ring logically ties CPU 1 TO 1/0-5, these being -shown in more detail in Figs. 2A, 2B (see inside respective dotted-lines) .
- the line (connector channel 8) connecting CPU 1 and I/O 5 with MP bus 21, is preferably coupled thereto via a SAD (system address) bus.
- channel 8 comprises a MAD bus and a bidirectional buffer-register (BCT-G52-M) A, linking MP bus 21 with SAD bus and thus linking 1/0-5 with all processors. Workers will recognize the advantageous use of such O-Ring architecture with such a common access-line to MP bus 21.
- Buses MAD, SAD are depicted in Fig. 2A, along with two private buses VD, VA from base processor 1 to I/O board 5.
- 3 - base processor 1 can "talk" asynchronously with I/O board 5 (not synchronously, as is conventional).
- the base processor cache can operate asynchronously with its processor, and also with
- SAD bus also links MP bus with a Cache Address bus (CA bus), with a Cache Data bus (CD bus), with a Cache Tag data bus (TD bus) and with a DMA ASIC portion of 1/0-5 ("Direct Memory Access" chip to move data between disks and CP-memory or cache memory 1-C?).
- Register BCT-652-M is a bidirectional buffer/register coupled between SAD bus and MP bus to transfer data to the CPU 1, 1/0-5 ring (e.g., from main memory, from other CPUs).
- a composite "bus tag” arrangement is provided with two tags for each CPU (board); as part of this, we provide a "cache tag” aa (Fig. 2A) and “bus tag” bb (Fig. 2A); their contents (they are static RAMs) should always be the same. Also provided is a math co-processor dd (e.g., preferably a "4167" chip by Weitek Corp. or an Intel 80387).
- PA bus Processor Address bus
- PD bus Processor Data bus
- All the above five buses are indicated in Figs. 2A, 2B.
- An address buffer 543 is- provided to isolate CA bus and PA bus.
- a latch 574 is provided to store the SAD address, while a D-flip flop 574 is provided to "evict" addresses to the SAD bus.
- a bidirectional buffer 245 provides the path for updating tag data and for "snooping" the CPU (i.e., to invalidate data elsewhere when it is updated in a given memory site) .
- a comparator unit 521 is provided to check for cache "hit"/"miss” .
- the base processor CPU 1 is coupled for bilateral asynchronous communication with the associated I/O unit 5 (cf. asynchronous I/O-CPU interface 2). It is conventional for such an interface to be synchronous (e.g., clock- synchronized; e.g., see US 4,669,043 to aplinsky, or US 4,591,977 to Nissen et al. where I/O is directly-coupled to a CPU; or see US 4,931,984 to Ny or US 4,161,024 to Joyce et al. ) .
- clock- synchronized e.g., see US 4,669,043 to aplinsky, or US 4,591,977 to Nissen et al. where I/O is directly-coupled to a CPU; or see US 4,931,984 to Ny or US 4,161,024 to Joyce et al.
- This "O-Ring" architecture may be contrasted with U.S. Patent 4,351,025 where a control CPU is coupled by a separate bus to a master control I/O unit; or with more conventional arrangements coupling I/O and CPU via a single shared bus—and doing so in a synchronous, tightly-coupled interface.
- This O-Ring coupling with its two channels enhances system performance—for instance, allowing MP bus to access CP-cache 1-C (or I/O cache 5-C) while CPU 1 simultaneously accesses EISA bus, and with no problematic contention.
- the asynchronous nature of this CPU-I/O interface allows I/O to operate at any frequency, thus enhancing system-modularity and design flexibility.
- O-Ring .
- couple 2 will be assumed to preferably comprise a pair of bidirectional connection channels between CPU 1 and I/O adapter 5 (e.g., vs. U.S. 4,459,655 using a master bus 17 along with a conversation bus 16 which allows two-way communication between slave- modules 12, 13, 14). . '
- each CPU in the system is provided with private cache memory means (e.g., 1-C for CPU 1) to which it is asynchronously coupled; likewise our I/O unit 5 is coupled, asynchronously, with an associated cache means 5-C. And, each cache is also coupled asynchronously with MP bus 21.
- private cache memory means e.g., 1-C for CPU 1
- I/O unit 5 is coupled, asynchronously, with an associated cache means 5-C.
- each cache is also coupled asynchronously with MP bus 21.
- the cited Joyce patent teaches no such private caching and no such bilateral asynchronous cache interfacing either.
- our multiple* processor system preferably uses a base processor (e.g., CPU 1) along with application processor CPUs, each preferably with associated cache memory) to share a single MP bus (21 in Fig. 1).
- a base processor e.g., CPU 1
- application processor CPUs each preferably with associated cache memory
- each CPU with the common shared bus via a single channel, and also via the respective associated private cache memory (e.g., vs. the multiprocessor system in U.S. 4,591,977 to Nissen which teaches other local memory units for each CPU, these unconnected to a common bus and also using a common memory that must be time-shared and is not asynchronous with any CPU or any common bus).
- private cache memory e.g., vs. the multiprocessor system in U.S. 4,591,977 to Nissen which teaches other local memory units for each CPU, these unconnected to a common bus and also using a common memory that must be time-shared and is not asynchronous with any CPU or any common bus.
- Fig. 2 expands on the described simplified arrangement of Fig. 1 in a multiprocessor system adapted for file server and OLTP (on-line transaction processing) applications.
- Base processor CPU 1' (including processor chip CP-11', and associated private cache memory 1-C), I/O adapter card 5' (including its own private cache memory).
- Processor CPU 1' and I/O adapter 5' will be understood as configured in O-Ring fashion, being intercoupled along VA bus and VD bus, via interface control IFC, and being both. coupled to MP-bus 21' along a single common" channel 8', (including MAD bus and buffer/register BCT-652), with I/O adapter 5' coupled to access SCSI bus and EISA bus.
- a system address bus couples channel 8' (register BCT-652 thereof) to a pair of (tag-check units H-A, H-B, via a latch 573, as well as to base processor array CP-1' (via register/buffers BCT-652: -C, -B lf -B 2 , and via evict unit 574-F); and also couples channel 8' to I/O adapter (via control IFC, and DMA-ASIC-DD, and BSAD bus and a tag- snoop unit 245-E).
- SAD bus system address bus
- Registers BCT-652-Bi are -B 2 are .coupled by a cache address bus (CA bus) to data cache 3' and to Moesi cache 3", as well as to a pair of isolation buffers 543-G' , 453-G", and also to a comparator stage 521-h (Fig. 2A) .
- CA bus cache address bus
- a cache data bus couples data cache 3' with address buffer 543-G and register BCT-652-C.
- a cache tag .data bus (TD bus) couples evict unit
- SAD bus provides linkage between MP bus on the one hand, and the following: BSAD bus, CA bus, CD bus, TD bus, and DMA ASIC DD (140, via tag snoop unit 245-E. ) .
- Fig. 2B also note that an 80486 data bus (PD bus) links buffer 543G and tag-snoop unit 245-E' with base processor chip CP-11' and with math coprocessor chip dd. Also, note processor address bus (PA bus, cf. address bus for Intel 80486 microprocessor) which links processors CP-11' and dd with evict unit 574-F' and with buffer 543-G' and tag cache TC.
- Fig. 2C is an enlargement of the 1/0-5' portion of Figs. 2 which will be better understood by the following description of salient component parts (Intel chip designations) as follows:
- the 82358 EBC is the central component of the EISA system.
- the EBC performs the translations between host CPU cycles, AT cycles, and EISA cycles. Masters on any of the three buses communicate with the other buses through the EBC. It takes care of all necessary timing alignments and translations for the different buses to communicate.
- the EBC sits between the fast host (CPU) bus and the 8 Mhz EISA/AT buses. It watches cycles initiated on all buses. When a host bus master initiates a cycle and no host slave responds, the EBC forwards the cycle to the EISA and AT buses. All cycles initiated by EISA bus masters are forwarded to the host and AT buses. It also provides the control for the address and data buffers between the buses and takes care of inserting delays between back to back I/O cycles coming from the host bus to the EISA bus. 82357 Integrated System Peripheral (5-A):
- the 82357 ISP is a multi-function support peripheral that is designed to work in conjunction with the 82358 EISA bus controller to provide most of the system functions necessary in EISA specific applications.
- the 82357 ISP is comprised of several computer system functions that are typically found in separate LSI and VLSI components.
- a high-performance 7-channel programmable DMA controller includes: a high-performance 7-channel programmable DMA controller; an arbitration scheme that allows efficient bus sharing among multiple EISA masters and DMA devices; a 15 level programmable interrupt controller which provides level-or-edge triggered interrupt capability on a channel by channel basis; non- maskable interrupt logic for multiple NMI control and generation; refresh address generation and control; 5 counter/timers which provide a system timer interrupt for a time of day, diskette time-out, DRAM refresh requests, and other system timing operations.
- the 82352 EBB is used to integrate the data swap logic - and the address buffers. This integrates approximately 17 components and lowers the system board chip count. Additionally, the EBB is designed to meet some of the timing requirements of EISA that would be difficult to do with discrete components and to eliminate excess EMI for FCC testing requirements.
- BMIC Master Interface Controller
- the 82355 BMIC greatly simplifies the design of 32-bit EISA bus masters.
- an expansion board can be implemented with, simple logic similar to that used in traditional AT DMA designs; however, the BMIC also allows the designer to take full advantage of the advanced features of EISA bus masters.
- Features available when using the BMIC are the burst " mode for data transfer rates up to 33 megabytes/sec, EISA automatic configuration, and 32-bit address bus which covers the entire 4-gigabyte EISA address space.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Système informatique multiprocesseur dans lequel un processeur de base est couplé en réunion logique asynchrone à un adaptateur d'entrée/sortie associé, le processeur ainsi que l'adaptateur E/S comprenant chacun une antémémoire privée associée par laquelle ils sont l'un et l'autre reliés à un bus MP partagé commun par l'intermédiaire d'un seul canal connecteur.A multiprocessor computer system in which a base processor is coupled in an asynchronous logical union to an associated I / O adapter, the processor as well as the I / O adapter each including an associated private cache by which they are one and the same. 'other connected to a common shared MP bus via a single connector channel.
Description
Claims
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US71890091A | 1991-06-20 | 1991-06-20 | |
US71889991A | 1991-06-20 | 1991-06-20 | |
US718899 | 1991-06-20 | ||
US718900 | 1991-06-20 | ||
PCT/US1992/005079 WO1993000639A1 (en) | 1991-06-20 | 1992-06-19 | Multiprocessor array |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0591405A1 true EP0591405A1 (en) | 1994-04-13 |
Family
ID=27109996
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP92914447A Ceased EP0591405A1 (en) | 1991-06-20 | 1992-06-19 | Multiprocessor array |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0591405A1 (en) |
JP (1) | JPH06508707A (en) |
WO (1) | WO1993000639A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6002883A (en) * | 1996-07-18 | 1999-12-14 | International Business Machines Corporation | System with intersystem information links for intersystem traffic having I/O traffic being transmitted to and from processor bus via processor means |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2474201B1 (en) * | 1980-01-22 | 1986-05-16 | Bull Sa | METHOD AND DEVICE FOR MANAGING CONFLICTS CAUSED BY MULTIPLE ACCESSES TO THE SAME CACH OF A DIGITAL INFORMATION PROCESSING SYSTEM COMPRISING AT LEAST TWO PROCESSES EACH HAVING A CACHE |
US4654778A (en) * | 1984-06-27 | 1987-03-31 | International Business Machines Corporation | Direct parallel path for storage accesses unloading common system path |
US5025365A (en) * | 1988-11-14 | 1991-06-18 | Unisys Corporation | Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors |
-
1992
- 1992-06-19 EP EP92914447A patent/EP0591405A1/en not_active Ceased
- 1992-06-19 WO PCT/US1992/005079 patent/WO1993000639A1/en not_active Application Discontinuation
- 1992-06-19 JP JP5501543A patent/JPH06508707A/en not_active Withdrawn
Non-Patent Citations (1)
Title |
---|
See references of WO9300639A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO1993000639A1 (en) | 1993-01-07 |
JPH06508707A (en) | 1994-09-29 |
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Legal Events
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18R | Application refused |
Effective date: 19970316 |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: TAM, SAM Inventor name: SHEIKH, TAHIR, Q. Inventor name: SASSONE, BRIAN, J. Inventor name: LIU, JONATHAN, W. Inventor name: LI, ADAM, W., K. Inventor name: KURPANEK, DIETMAR, M. Inventor name: HO, KIN, M. |