EP0496443A1 - Semiconductor device and method of manufacturing such a semiconductor device - Google Patents
Semiconductor device and method of manufacturing such a semiconductor device Download PDFInfo
- Publication number
- EP0496443A1 EP0496443A1 EP92200079A EP92200079A EP0496443A1 EP 0496443 A1 EP0496443 A1 EP 0496443A1 EP 92200079 A EP92200079 A EP 92200079A EP 92200079 A EP92200079 A EP 92200079A EP 0496443 A1 EP0496443 A1 EP 0496443A1
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- layer
- insulating layer
- etching stopper
- conductive regions
- etching
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000005530 etching Methods 0.000 claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 13
- 239000010410 layer Substances 0.000 description 110
- 238000003384 imaging method Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001429 visible spectrum Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
- H01L27/1485—Frame transfer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66946—Charge transfer devices
- H01L29/66954—Charge transfer devices with an insulated gate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Definitions
- the invention relates to a semiconductor device comprising a semiconductor body having at a surface one or several circuit elements with at least two conductive regions, the surface being coated with an insulating layer on which a conductor track is provided which interconnects the conductive regions through contact windows in the insulating layer and which is recessed into the insulating layer over at least substantially its entire thickness.
- the invention also relates to a method of manufacturing a semiconductor device comprising a semiconductor body having at a surface one or several circuit elements with at least two conductive regions, the surface being coated with an insulating layer on which a conductor track is formed which interconnects the conductive regions through contact windows in the insulating layer and which is recessed into the insulating layer over at least substantially its entire thickness.
- conductive regions is to be widely interpreted here so as to include: doped semiconductor zones in the semiconductor body, gate electrodes of field effect devices, portions of subjacent wirings, contact surfaces, etc.
- the interconnection pattern lies recessed in the insulating layer, so that the structure remains plane.
- no plugs are required for the connections between the interconnection pattern and semiconductor zones or poly tracks.
- a semiconductor device of the kind described in the opening paragraph according to the invention is characterized in that an etching stopper layer is present in an interposed region between the conductive regions, which layer separates the conductor track from a subjacent portion of the insulating layer and which comprises a material which is selectively etchable relative to the insulating layer, while the etching stopper layer forms part of a layer pattern manufactured from a common layer, which pattern comprises besides the etching stopper layer further portions elsewhere in the device.
- a polycrystalline silicon layer for example, or a dielectric layer of a material different from the insulating layer may be used for the etching stopper layer. Since such a layer is usually present in the process anyway, it is not necessary to use a separate photomask for the contact windows.
- a method of the kind described in the opening paragraph is characterized in that, after the conductive regions have been provided, the insulating layer is formed over a first part of its thickness, in that an etching stopper layer of a conductive material which is selectively etchable relative to the insulating layer is formed on this part in an intermediate region situated between the conductive regions, and in that subsequently the insulating layer is provided over a second part of its thickness, upon which the insulating layer is subjected to an etching treatment at the area of the conductor track to be formed, during which it is removed in the said intermediate region down to the etching stopper layer and at the area of the contact windows down to the conductive regions, after which the configuration thus obtained is covered with a conductive layer, from which the recessed conductor track is formed by etching back.
- Fig. 1 shows a diagrammatic plan view of a raster transfer imaging device comprising a system of vertical CCD lines 1 situated next to one another divided into an imaging section A and a memory section B.
- the imaging section A serves, as is known, for converting a projected image into charge packages.
- these charge packages are quickly transported to the memory section B which is screened from incident radiation.
- the horizontal readout register C which is provided with an output amplifier 2.
- the charge packages stored in the B section are transported to the readout register C row by row and read sequentially at the output amplifier 2.
- the charge transport and charge storage are controlled by clock voltages which are applied to clock electrodes 3, four of which are diagrammatically depicted in Fig. 1, ⁇ 1, ⁇ 2, ⁇ 3 and ⁇ 4.
- the clock electrodes are made by the double- or triple-layer poly-Si technology, by means of which an overlapping gate structure is made in two or three layers.
- a drawback of this technology is that the structure onto which the image is projected is of very imperfect flatness, so that light can be deflected towards insensitive regions.
- the poly layers used are usually 0,3-0,5 ⁇ m thick, which is too thick for transmitting sufficient blue light. Therefore, a photosensitive surface free from poly-Si is often formed through adaptation of the gate configuration. The thickness of the poly-Si is so great because otherwise, i.e.
- a single-layer poly technology will be used for the clock electrodes of at least the A section with a very thin poly layer, approximately 50 nm thick, so that the sensor has a good sensitivity to the entire visible spectrum, there is no overlap between the gates of the various phases, and the structure is topographically very plane.
- Fig. 2 is a diagrammatic plan view of part of the electrode configuration in the imaging section A.
- the clock electrodes 3 are formed by non-overlapping polystrips with a thickness of 50 nm situated next to one another.
- the comparatively high-ohmic tracks 3 are connected to low-ohmic metal tracks 4 which are connected to the polystrips 3 at the areas of the dots.
- each metal strip 4 is connected to each fourth clock electrode 3.
- the metal strips 4 may be made very narrow, so that comparatively wide spaces remain open between the metal strips, through which spaces the light may penetrate into the semiconductor body.
- the gates 3 may each be connected to the clock lines by a number of interspaced tracks 4 in order to obtain the desired low RC time value.
- the metal tracks 4 may be connected to four clock lines 5, by means of which the clocks ⁇ 1, ⁇ 2, ⁇ 3 and ⁇ 4 are provided, via connections 6.
- Fig. 3a shows in cross-section a portion of a semiconductor device in which the invention is incorporated, with a portion of a charge-coupled device to be used in the imaging section A of the imaging device according to Fig. 2, and an MOS transistor which is integrated with the charge-coupled device.
- Fig. 3b gives a diagrammatic plan view of the portion shown in Fig. 3a.
- the device comprises a semiconductor body 10 of silicon with a surface 11 at which or near which the charge-coupled device 12 and the MOST 13 are situated.
- the charge-coupled device comprises a range of clock electrodes 3a, 3b, 3c, etc. formed by thin, approximately 50 nm thick polycrystalline silicon tracks.
- the gates 3 constitute the conductive regions referred to above and are separated from the surface 11 by the thin dielectric layer 14.
- the gate dielectric only comprises a silicon oxide layer, but it may obviously also consist of a different insulating material or of double layers of, for example, silicon oxide and silicon nitride.
- the gates 3 are embedded in a dielectric layer 15 which may be entirely of silicon oxide, but which may obviously also be composed entirely or partly of other materials.
- the layer 15 is composed of two portions 15a and 15b, which will be discussed below.
- the MOS transistor 13 comprises a source and a drain zone 17, 18 and a gate electrode 19 which is insulated from the subjacent channel region by the gate oxide 14.
- a conductor track 4 is formed which interconnects the conductive regions 3b and 3f via contact windows in the insulating layer 15.
- the conductor 4 is embedded in the layer 15 over at least substantially its entire thickness, so that a practically plane upper surface is obtained.
- an etching stopper layer 21 separating the conductor track 4 from the subjacent portion 15a of the insulating layer 15 is present in the intermediate region between the conductive regions 3b and 3f.
- the layer 21 comprises a material which is different from that of the insulating layer 15 and relative to which the layer 15 can be selectively etched.
- the etching stopper layer 21 requires no extra process steps since the layer 21 forms part of a layer pattern manufactured from a common layer, which pattern comprises besides the etching stopper layer 21 further portions in the device and which can accordingly be formed simultaneously with these further portions.
- the etching stopper layer 21 is made of polycrystalline silicon which together with the gate 19 of the transistor 13 belongs to the second polycrystalline wiring layer.
- the thickness of this second layer is approximately 0,4 ⁇ m and is chosen to be much greater, for reasons of resistance, than the thickness of the gates 3a, 3b, etc. which is only approximately 50 nm for reasons of photosensitivity.
- the transistor 13 is further provided with a contact 22 which is connected to the zone 18, and with a contact 23 which is connected to the gate 19, the contacts 22, 23 being formed by plugs.
- the contact 23 is drawn above the channel region in the drawing. In actual fact, however, it will preferably be provided above the field oxide not shown in the drawing.
- Fig. 5 shows the stage in which the clock electrodes 3 are formed from an approximately 50 nm thick polycrystalline silicon layer.
- the gates 3 are then coated with an oxide layer 15a.
- This layer which may be provided by, for example, CVD techniques known per se and local removal through etching, has a thickness of approximately 0,3 ⁇ m. Then an approximately 0,4 ⁇ m thick second polycrystalline silicon layer 24 is provided by deposition.
- the gate 19 of the MOST 13 is formed from this layer, and on the other hand the etching stopper layer 21.
- the width of the etching stopper layer is 1,7 - 2 ⁇ m and is chosen to be somewhat greater than the width of the conductor track 4 to be provided in a later stage.
- the layer 21 has an interruption with a width of approximately 1,1 ⁇ m at the area of the connection to be provided between the conductor track 4 and the gate 3b, at a width of approximately 2 ⁇ m of the gate 3b.
- the entire assembly is then covered with a thick oxide layer 15b, having a thickness of approximately 1 ⁇ m.
- a mask 26 in the form of a photoresist layer is formed on the surface of this oxide layer, which mask is complementary to, or the inverted image of, the metal pattern to be obtained at a later stage.
- the mask 26 has openings 27 at the areas of the contacts 22, 23 and an opening 28 at the area of the connection 4 to be formed.
- the width of the opening 28, which is situated as symmetrically as possible above the etching stopper layer 21, is approximately 1,1 ⁇ m, so that the etching stopper layer projects by approximately 0,3-0,5 ⁇ m on either side of the opening 28.
- the source and drain zones 17, 18 of MOSTs and other zones may also be provided.
- the device is then in the stage as shown in Fig. 6. Then the device is subjected to an etching treatment during which the oxide layer 15a, 15b is removed at the areas of the openings 27, 28.
- the etching treatment is carried out selectively in that the polycrystalline silicon of the gates 3, 19 and the etching stopper layer 21 are not attacked or at least attacked to a much lesser degree during etching of the oxide.
- Etching is preferably carried out in an anisotropic plasma etching stage to prevent underetching.
- Etching of the oxide is continued down to a depth where a different material is present, i.e. for example up to the monocrystalline Si material at the area of the source or drain zone 18, down to the polycrystalline Si material at the area of the gate 19 of the MOST and the etching stopper layer 21.
- the contact window 30 is formed at the area of the gate 3b, where the etching stopper layer 21 has an interruption 25.
- Etching of the oxide layer 15 continues down to the polycrystalline Si material of the first poly layer.
- the width of the window 30 in the direction of the cross-section of Fig. 7 is determined by the width of the interruption 25 in the etching stopper layer 21.
- the width in the direction transverse to the plane of the drawing is determined by the mask 26.
- the width of the contact window 31 at the area of the poly track 3f is determined, in the cross-section of Fig. 7, by the spacing between the etching stopper layer 21 to the left of the window 31 and the edge of the mask 26 to the right of the window 31 to be formed.
- the width of the window 31 in the direction transverse to the plane of the drawing is again determined by the mask 26.
- a thick metal layer 31 (Fig. 8) is provided, which covers the entire surface.
- Tungsten is chosen for the layer 32 in the present embodiment. Obviously, other suitable materials may also be chosen.
- a thin layer of TiW 33 may be provided, for example, by sputtering. The layer 33 ensures a good adhesion of the metal layer 32 and also forms a good barrier against diffusion.
- the metal layer 32/33 is subjected to an etching treatment and etched back to the upper surface of the thick oxide layer 15.
- the configuration of Fig. 3 is then obtained.
- the use of the second polycrystalline silicon layer for the etching stopper layer 21 renders an extra mask for masking the oxide layer 15 in the intermediate region between the contact windows 30, 31 to be formed redundant.
- Only two polycrystalline silicon layers are used in the embodiment described here.
- Fig. 9 gives in cross-section an embodiment comprising three polycrystalline layers. Only part of a CCD channel is shown in the drawing.
- the charge-coupled device comprises clock electrodes in two poly layers, i.e. the gates 35a, b, c in poly 1, and the gates 36a, b, c in poly 2.
- the thickness of the two poly layers is between, for example, 0,3 and 0,5 ⁇ m. This thickness is much greater than the thickness of the CCD electrodes 3 in the preceding embodiment, so that the resistance will be much lower. Nevertheless, it may yet be advantageous also in this case to connect the electrodes to low-ohmic bridge connections 4, for example, when the dimensions of the image sensor are very great.
- the electrodes 35a, 35b, 35c are formed from a first polycrystalline silicon layer, with openings between the electrodes.
- a second polycrystalline silicon layer is deposited, from which the gates 36a, 36b, 36c are formed, which fill up the openings between the gates 35.
- the gates 36 may overlap the gates 35, as is shown in Fig. 9.
- the gates 35, 36 are covered with the oxide layer 15a, after which a third polycrystalline silicon layer is deposited, from which the etching stopper layer 21 is formed. Since this third polylayer is necessary elsewhere in any case, inter alia for the parallel-serial interface (not shown in Fig.
- the provision of the etching stopper layer 21 does not require an extra deposition step and mask.
- the gate electrode 19 of MOS transistors may be formed in poly 2 before doping stages for source and drain zones are implemented.
- the manufacture of the device can be continued in a manner analogous to that for the preceding embodiment.
- a thick oxide layer 15 is then deposited first, in which the pattern of the wiring to be shaped is provided by means of an inverted metal mask. Etching continues at the areas of the gates 35b and 35d down to the polymaterial of these gates. In the area situated between these gates, etching is stopped by the etching stopper layer 21. After the etching treatment, the recessed metal pattern with the bridge connection 4 is formed in the manner described above by means of deposition and etching back.
- etching stopper layer 21 need not necessarily consist of polysilicon, it may alternatively consist of a different material, for example, silicide. Instead of W or TiW, other metals or conductive materials, such as doped semiconductor material, may be used for the connections 4.
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Abstract
Description
- The invention relates to a semiconductor device comprising a semiconductor body having at a surface one or several circuit elements with at least two conductive regions, the surface being coated with an insulating layer on which a conductor track is provided which interconnects the conductive regions through contact windows in the insulating layer and which is recessed into the insulating layer over at least substantially its entire thickness.
- The invention also relates to a method of manufacturing a semiconductor device comprising a semiconductor body having at a surface one or several circuit elements with at least two conductive regions, the surface being coated with an insulating layer on which a conductor track is formed which interconnects the conductive regions through contact windows in the insulating layer and which is recessed into the insulating layer over at least substantially its entire thickness. The term "conductive regions" is to be widely interpreted here so as to include: doped semiconductor zones in the semiconductor body, gate electrodes of field effect devices, portions of subjacent wirings, contact surfaces, etc.
- It is usual in complicated integrated circuits to use multilayer interconnections with one or several of the lower interconnection layers made of polycrystalline silicon (poly) and/or silicide, and the upper layer or layers made of metal, such as Al. It is usual thereby to connect poly tracks (or silicide tracks) and monocrystalline zones in the body to the first metal layer by means of metal plugs. These mostly contain W, or TiW and W. The first metal layer is also connected to the second metal layer by means of plug connections.
- A semiconductor device and a method of the kind described in the opening paragraph are described in the publication "Reverse Pillar and Maskless Contact - Two novel recessed metal schemes and their comparisons to conventional VLSI metallization schemes" by J.L. Yeh et al. in IEEE Proc. VLSI MIC, pp. 95-100, Santa Clara 1988. In this known method, a mask which is the inverted image of the interconnection pattern in the insulating layer is used for etching a pattern corresponding to the interconnection pattern over part of the thickness of the insulating layer. The contact windows are then formed by means of an additional photoresist mask which covers the insulating layer with the exception of the contact windows to be formed. Then a metal layer is provided, from which the interconnection pattern is formed by etching back. The interconnection pattern lies recessed in the insulating layer, so that the structure remains plane. In addition, no plugs are required for the connections between the interconnection pattern and semiconductor zones or poly tracks.
- In this known process, a separate photoresist mask is required for the definition of the contact windows. It is an object of the invention to render this photoresist mask redundant and thus to simplify the manufacture of the device considerably.
- A semiconductor device of the kind described in the opening paragraph according to the invention is characterized in that an etching stopper layer is present in an interposed region between the conductive regions, which layer separates the conductor track from a subjacent portion of the insulating layer and which comprises a material which is selectively etchable relative to the insulating layer, while the etching stopper layer forms part of a layer pattern manufactured from a common layer, which pattern comprises besides the etching stopper layer further portions elsewhere in the device.
- A polycrystalline silicon layer, for example, or a dielectric layer of a material different from the insulating layer may be used for the etching stopper layer. Since such a layer is usually present in the process anyway, it is not necessary to use a separate photomask for the contact windows.
- According to the invention, a method of the kind described in the opening paragraph is characterized in that, after the conductive regions have been provided, the insulating layer is formed over a first part of its thickness, in that an etching stopper layer of a conductive material which is selectively etchable relative to the insulating layer is formed on this part in an intermediate region situated between the conductive regions, and in that subsequently the insulating layer is provided over a second part of its thickness, upon which the insulating layer is subjected to an etching treatment at the area of the conductor track to be formed, during which it is removed in the said intermediate region down to the etching stopper layer and at the area of the contact windows down to the conductive regions, after which the configuration thus obtained is covered with a conductive layer, from which the recessed conductor track is formed by etching back.
- The invention will be explained in more detail with reference to an embodiment and the accompanying diagrammatic drawing in which
- Fig. 1 shows the diagram of a charge-coupled image sensor of the raster transfer type;
- Fig. 2 shows a portion of the device depicted in Fig. 1 with the diagrammatically indicated connections between the clock lines and the clock electrodes according to the invention;
- Fig. 3 is a cross-section of a portion of the device according to Fig. 2;
- Fig. 4 is a plan view of the portion shown in Fig. 3;
- Figs. 5-8 show the device in a number of stages of manufacture thereof;
- Fig. 9 is a cross-section of a second embodiment of the device.
- The invention will be explained in more detail with reference to a charge-coupled device, more particularly an imaging device for which the invention is especially important. It will be quite clear from the description, however, that the invention may also be advantageously used in other types of integrated circuits.
- Fig. 1 shows a diagrammatic plan view of a raster transfer imaging device comprising a system of
vertical CCD lines 1 situated next to one another divided into an imaging section A and a memory section B. The imaging section A serves, as is known, for converting a projected image into charge packages. At the end of the imaging period, these charge packages are quickly transported to the memory section B which is screened from incident radiation. At the lower side of the memory section is provided the horizontal readout register C which is provided with anoutput amplifier 2. The charge packages stored in the B section are transported to the readout register C row by row and read sequentially at theoutput amplifier 2. The charge transport and charge storage are controlled by clock voltages which are applied toclock electrodes 3, four of which are diagrammatically depicted in Fig. 1, φ1, φ2, φ3 and φ4. - It is usual for the clock electrodes to be made by the double- or triple-layer poly-Si technology, by means of which an overlapping gate structure is made in two or three layers. A drawback of this technology is that the structure onto which the image is projected is of very imperfect flatness, so that light can be deflected towards insensitive regions. In addition, it is difficult in the case of a colour sensor to provide a colour filter in an accurate manner. The poly layers used are usually 0,3-0,5 µm thick, which is too thick for transmitting sufficient blue light. Therefore, a photosensitive surface free from poly-Si is often formed through adaptation of the gate configuration. The thickness of the poly-Si is so great because otherwise, i.e. in the case of a smaller thickness, the resistance becomes too great, and thus the RC time per clock phase. In the embodiment to be described here, a single-layer poly technology will be used for the clock electrodes of at least the A section with a very thin poly layer, approximately 50 nm thick, so that the sensor has a good sensitivity to the entire visible spectrum, there is no overlap between the gates of the various phases, and the structure is topographically very plane.
- Fig. 2 is a diagrammatic plan view of part of the electrode configuration in the imaging section A. The
clock electrodes 3 are formed by non-overlapping polystrips with a thickness of 50 nm situated next to one another. The comparatively high-ohmic tracks 3 are connected to low-ohmic metal tracks 4 which are connected to thepolystrips 3 at the areas of the dots. In the embodiment shown of a 4-phase CCD, eachmetal strip 4 is connected to eachfourth clock electrode 3. Themetal strips 4 may be made very narrow, so that comparatively wide spaces remain open between the metal strips, through which spaces the light may penetrate into the semiconductor body. As is shown in Fig. 1, thegates 3 may each be connected to the clock lines by a number ofinterspaced tracks 4 in order to obtain the desired low RC time value. At the upper side of the CCD matrix, themetal tracks 4 may be connected to fourclock lines 5, by means of which the clocks φ1, φ2, φ3 and φ4 are provided, viaconnections 6. - Fig. 3a shows in cross-section a portion of a semiconductor device in which the invention is incorporated, with a portion of a charge-coupled device to be used in the imaging section A of the imaging device according to Fig. 2, and an MOS transistor which is integrated with the charge-coupled device. Fig. 3b gives a diagrammatic plan view of the portion shown in Fig. 3a.
- The device comprises a
semiconductor body 10 of silicon with asurface 11 at which or near which the charge-coupleddevice 12 and theMOST 13 are situated. The charge-coupled device comprises a range ofclock electrodes gates 3 constitute the conductive regions referred to above and are separated from thesurface 11 by the thindielectric layer 14. In the present embodiment, the gate dielectric only comprises a silicon oxide layer, but it may obviously also consist of a different insulating material or of double layers of, for example, silicon oxide and silicon nitride. Thegates 3 are embedded in adielectric layer 15 which may be entirely of silicon oxide, but which may obviously also be composed entirely or partly of other materials. Thelayer 15 is composed of twoportions - The
MOS transistor 13 comprises a source and adrain zone gate electrode 19 which is insulated from the subjacent channel region by thegate oxide 14. - On the
insulating layer 15, or at least on theportion 15a of the insulating layer, aconductor track 4 is formed which interconnects theconductive regions insulating layer 15. Theconductor 4 is embedded in thelayer 15 over at least substantially its entire thickness, so that a practically plane upper surface is obtained. According to the invention, anetching stopper layer 21 separating theconductor track 4 from thesubjacent portion 15a of theinsulating layer 15 is present in the intermediate region between theconductive regions layer 21 comprises a material which is different from that of theinsulating layer 15 and relative to which thelayer 15 can be selectively etched. - The provision of the etching stopper layer requires no extra process steps since the
layer 21 forms part of a layer pattern manufactured from a common layer, which pattern comprises besides theetching stopper layer 21 further portions in the device and which can accordingly be formed simultaneously with these further portions. In the present embodiment, theetching stopper layer 21 is made of polycrystalline silicon which together with thegate 19 of thetransistor 13 belongs to the second polycrystalline wiring layer. The thickness of this second layer is approximately 0,4 µm and is chosen to be much greater, for reasons of resistance, than the thickness of thegates transistor 13 is further provided with acontact 22 which is connected to thezone 18, and with acontact 23 which is connected to thegate 19, thecontacts contact 23 is drawn above the channel region in the drawing. In actual fact, however, it will preferably be provided above the field oxide not shown in the drawing. - A few steps in the manufacture of the device according to Figs. 3 and 4 will be described with reference to Figs. 5-7. The device is shown in these Figs. in the same cross-section as in Fig. 3.
- Fig. 5 shows the stage in which the
clock electrodes 3 are formed from an approximately 50 nm thick polycrystalline silicon layer. - The
gates 3 are then coated with anoxide layer 15a. This layer, which may be provided by, for example, CVD techniques known per se and local removal through etching, has a thickness of approximately 0,3 µm. Then an approximately 0,4 µm thick secondpolycrystalline silicon layer 24 is provided by deposition. By means of photolithographic steps known per se, on the one hand thegate 19 of the MOST 13 is formed from this layer, and on the other hand theetching stopper layer 21. The width of the etching stopper layer is 1,7 - 2 µm and is chosen to be somewhat greater than the width of theconductor track 4 to be provided in a later stage. Thelayer 21 has an interruption with a width of approximately 1,1 µm at the area of the connection to be provided between theconductor track 4 and thegate 3b, at a width of approximately 2 µm of thegate 3b. The entire assembly is then covered with athick oxide layer 15b, having a thickness of approximately 1 µm. Amask 26 in the form of a photoresist layer is formed on the surface of this oxide layer, which mask is complementary to, or the inverted image of, the metal pattern to be obtained at a later stage. Themask 26 hasopenings 27 at the areas of thecontacts opening 28 at the area of theconnection 4 to be formed. The width of theopening 28, which is situated as symmetrically as possible above theetching stopper layer 21, is approximately 1,1 µm, so that the etching stopper layer projects by approximately 0,3-0,5 µm on either side of theopening 28. In this stage of the process, the source and drainzones oxide layer openings gates etching stopper layer 21 are not attacked or at least attacked to a much lesser degree during etching of the oxide. Etching is preferably carried out in an anisotropic plasma etching stage to prevent underetching. Etching of the oxide is continued down to a depth where a different material is present, i.e. for example up to the monocrystalline Si material at the area of the source ordrain zone 18, down to the polycrystalline Si material at the area of thegate 19 of the MOST and theetching stopper layer 21. Thecontact window 30 is formed at the area of thegate 3b, where theetching stopper layer 21 has aninterruption 25. Etching of theoxide layer 15 continues down to the polycrystalline Si material of the first poly layer. The width of thewindow 30 in the direction of the cross-section of Fig. 7 is determined by the width of theinterruption 25 in theetching stopper layer 21. The width in the direction transverse to the plane of the drawing is determined by themask 26. The width of thecontact window 31 at the area of thepoly track 3f is determined, in the cross-section of Fig. 7, by the spacing between theetching stopper layer 21 to the left of thewindow 31 and the edge of themask 26 to the right of thewindow 31 to be formed. The width of thewindow 31 in the direction transverse to the plane of the drawing is again determined by themask 26. - After etching, the
mask 26 is removed again, upon which a thick metal layer 31 (Fig. 8) is provided, which covers the entire surface. Tungsten is chosen for thelayer 32 in the present embodiment. Obviously, other suitable materials may also be chosen. Before thelayer 32 is provided, a thin layer ofTiW 33 may be provided, for example, by sputtering. Thelayer 33 ensures a good adhesion of themetal layer 32 and also forms a good barrier against diffusion. - After the metal deposition, the
metal layer 32/33 is subjected to an etching treatment and etched back to the upper surface of thethick oxide layer 15. The configuration of Fig. 3 is then obtained. - The use of the second polycrystalline silicon layer for the
etching stopper layer 21 renders an extra mask for masking theoxide layer 15 in the intermediate region between thecontact windows gates 35a, b, c inpoly 1, and thegates 36a, b, c inpoly 2. The thickness of the two poly layers is between, for example, 0,3 and 0,5 µm. This thickness is much greater than the thickness of theCCD electrodes 3 in the preceding embodiment, so that the resistance will be much lower. Nevertheless, it may yet be advantageous also in this case to connect the electrodes to low-ohmic bridge connections 4, for example, when the dimensions of the image sensor are very great. - In the manufacture of the device shown in Fig. 9, first the
electrodes gates oxide layer 15a, after which a third polycrystalline silicon layer is deposited, from which theetching stopper layer 21 is formed. Since this third polylayer is necessary elsewhere in any case, inter alia for the parallel-serial interface (not shown in Fig. 9) between the memory section B and the horizontal readout register C (see Fig. 1), the provision of theetching stopper layer 21 does not require an extra deposition step and mask. Thegate electrode 19 of MOS transistors (not shown in Fig. 9) may be formed inpoly 2 before doping stages for source and drain zones are implemented. When theetching stopper layer 21 has been formed, the manufacture of the device can be continued in a manner analogous to that for the preceding embodiment. Athick oxide layer 15 is then deposited first, in which the pattern of the wiring to be shaped is provided by means of an inverted metal mask. Etching continues at the areas of thegates etching stopper layer 21. After the etching treatment, the recessed metal pattern with thebridge connection 4 is formed in the manner described above by means of deposition and etching back. - It will be obvious that the invention is not limited to the embodiments given here, but that many variations are possible to those skilled in the art within the scope of the invention. Thus the invention may also be applied in different types of charge-coupled devices as well as in integrated circuits without charge-coupled devices. Besides bridge connections between gate electrodes, connections between surface zones in the semiconductor body or between zones and gates of conductor tracks may also be formed in the manner described here. The
etching stopper layer 21 need not necessarily consist of polysilicon, it may alternatively consist of a different material, for example, silicide. Instead of W or TiW, other metals or conductive materials, such as doped semiconductor material, may be used for theconnections 4.
Claims (6)
- A semiconductor device comprising a semiconductor body having at a surface one or several circuit elements with at least two conductive regions, the surface being coated with an insulating layer on which a conductor track is provided which interconnects the conductive regions through contact windows in the insulating layer and which is recessed into the insulating layer over at least substantially its entire thickness, characterized in that an etching stopper layer is present in an interposed region between the conductive regions, which layer separates the conductor track from a subjacent portion of the insulating layer and which comprises a material which is selectively etchable relative to the insulating layer, while the etching stopper layer forms part of a layer pattern manufactured from a common layer, which pattern comprises besides the etching stopper layer further portions elsewhere in the device.
- A semiconductor device as claimed in Claim 1, characterized in that the etching stopper layer comprises a metal or a semiconductor material, in particular polycrystalline silicon.
- A semiconductor device as claimed in any one of the preceding Claims, characterized in that the two conductive regions form gate electrodes of the charge-coupled device, with a range of gate electrodes which are situated next to one another and form part of a common wiring layer.
- A semiconductor device as claimed in Claim 3, characterized in that the gate electrodes are manufactured from a first layer of polycrystalline silicon, and that the etching stopper layer is manufactured from a second polycrystalline silicon layer which is electrically separated from the first one by an interposed portion of the insulating layer, the thickness of the second polycrystalline silicon layer being greater than that of the first polycrystalline silicon layer.
- A method of manufacturing a semiconductor device comprising a semiconductor body having at a surface one or several circuit elements with at least two conductive regions, the surface being coated with an insulating layer on which a conductor track is formed which interconnects the conductive regions through contact windows in the insulating layer and which is recessed into the insulating layer over at least substantially its entire thickness, characterized in that, after the conductive regions have been provided, the insulating layer is formed over a first part of its thickness, in that an etching stopper layer of a conductive material which is selectively etchable relative to the insulating layer is formed on this part in an intermediate region situated between the conductive regions, and in that subsequently the insulating layer is provided over a second part of its thickness, upon which the insulating layer is subjected to an etching treatment at the area of the conductor track to be formed, during which it is removed in the said intermediate region down to the etching stopper layer and at the area of the contact windows down to the conductive regions, after which the configuration thus obtained is covered with a conductive layer, from which the recessed conductor track is formed by etching back.
- A method as claimed in Claim 5, characterized in that the etching treatment for removing the insulating layer in the intermediate region and at the areas of the contact windows is carried out anisotropically.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL9100094A NL9100094A (en) | 1991-01-21 | 1991-01-21 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH SEMICONDUCTOR DEVICE. |
NL9100094 | 1991-01-21 |
Publications (2)
Publication Number | Publication Date |
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EP0496443A1 true EP0496443A1 (en) | 1992-07-29 |
EP0496443B1 EP0496443B1 (en) | 1998-09-09 |
Family
ID=19858750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP92200079A Expired - Lifetime EP0496443B1 (en) | 1991-01-21 | 1992-01-14 | Semiconductor device and method of manufacturing such a semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (2) | US5396092A (en) |
EP (1) | EP0496443B1 (en) |
JP (1) | JP3048459B2 (en) |
KR (1) | KR100273070B1 (en) |
DE (1) | DE69226887T2 (en) |
NL (1) | NL9100094A (en) |
Cited By (5)
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EP0625800A1 (en) * | 1993-05-21 | 1994-11-23 | Koninklijke Philips Electronics N.V. | Charge coupled imaging device |
US5449931A (en) * | 1993-05-21 | 1995-09-12 | U.S. Philips Corporation | Charge coupled imaging device having multilayer gate electrode wiring |
EP0757380A2 (en) * | 1995-07-31 | 1997-02-05 | Eastman Kodak Company | Method of making a planar charged coupled device with edge aligned implants and electrodes connected with overlaying metal |
EP0766303A2 (en) * | 1995-09-29 | 1997-04-02 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having wiring groove and contact hole formed in self-alignment manner and method of fabricating the same |
US5652173A (en) * | 1996-05-09 | 1997-07-29 | Philips Electronics North America Corporation | Monolithic microwave circuit with thick conductors |
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NL9100094A (en) * | 1991-01-21 | 1992-08-17 | Koninkl Philips Electronics Nv | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH SEMICONDUCTOR DEVICE. |
US5382545A (en) * | 1993-11-29 | 1995-01-17 | United Microelectronics Corporation | Interconnection process with self-aligned via plug |
US5635421A (en) * | 1995-06-15 | 1997-06-03 | Taiwan Semiconductor Manufacturing Company | Method of making a precision capacitor array |
US6008121A (en) * | 1996-03-19 | 1999-12-28 | Siemens Aktiengesellschaft | Etching high aspect contact holes in solid state devices |
JPH09270461A (en) * | 1996-03-29 | 1997-10-14 | Mitsubishi Electric Corp | Semiconductor device |
EP0925604B1 (en) * | 1997-05-29 | 2008-07-09 | Nxp B.V. | A method of manufacturing an electronic device whereby a conductive layer is provided on an electrically insulating substrate, from which layer a conductor pattern is formed |
US5989784A (en) * | 1998-04-06 | 1999-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch recipe for embedded DRAM passivation with etch stopping layer scheme |
EP1374301A2 (en) * | 2001-03-21 | 2004-01-02 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device with metallization layers interconnected by tungsten plugs |
DE10320166B4 (en) * | 2002-05-16 | 2007-06-06 | Dalsa Corp., Waterloo | Pixel design for CCD image sensors |
US6562711B1 (en) * | 2002-06-28 | 2003-05-13 | Intel Corporation | Method of reducing capacitance of interconnect |
US8166438B2 (en) * | 2009-01-28 | 2012-04-24 | Oracle America, Inc. | Low RC local clock distribution |
US8245781B2 (en) * | 2009-12-11 | 2012-08-21 | Schlumberger Technology Corporation | Formation fluid sampling |
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1991
- 1991-01-21 NL NL9100094A patent/NL9100094A/en not_active Application Discontinuation
-
1992
- 1992-01-14 DE DE69226887T patent/DE69226887T2/en not_active Expired - Fee Related
- 1992-01-14 EP EP92200079A patent/EP0496443B1/en not_active Expired - Lifetime
- 1992-01-18 KR KR1019920000667A patent/KR100273070B1/en not_active IP Right Cessation
- 1992-01-21 JP JP4008554A patent/JP3048459B2/en not_active Expired - Fee Related
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1994
- 1994-04-08 US US08/225,403 patent/US5396092A/en not_active Expired - Fee Related
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EP0224013A2 (en) * | 1985-10-28 | 1987-06-03 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate |
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Cited By (10)
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EP0625800A1 (en) * | 1993-05-21 | 1994-11-23 | Koninklijke Philips Electronics N.V. | Charge coupled imaging device |
US5449931A (en) * | 1993-05-21 | 1995-09-12 | U.S. Philips Corporation | Charge coupled imaging device having multilayer gate electrode wiring |
EP0757380A2 (en) * | 1995-07-31 | 1997-02-05 | Eastman Kodak Company | Method of making a planar charged coupled device with edge aligned implants and electrodes connected with overlaying metal |
EP0757380A3 (en) * | 1995-07-31 | 1997-12-29 | Eastman Kodak Company | Method of making a planar charged coupled device with edge aligned implants and electrodes connected with overlaying metal |
EP0766303A2 (en) * | 1995-09-29 | 1997-04-02 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having wiring groove and contact hole formed in self-alignment manner and method of fabricating the same |
EP0766303A3 (en) * | 1995-09-29 | 1997-04-23 | Toshiba Kk | |
US5976972A (en) * | 1995-09-29 | 1999-11-02 | Kabushiki Kaisha Toshiba | Method of making semiconductor apparatus having wiring groove and contact hole formed in a self-alignment manner |
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US6163067A (en) * | 1995-09-29 | 2000-12-19 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having wiring groove and contact hole in self-alignment manner |
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Also Published As
Publication number | Publication date |
---|---|
DE69226887D1 (en) | 1998-10-15 |
NL9100094A (en) | 1992-08-17 |
US5396092A (en) | 1995-03-07 |
US5536678A (en) | 1996-07-16 |
KR100273070B1 (en) | 2000-12-01 |
KR920015623A (en) | 1992-08-27 |
JP3048459B2 (en) | 2000-06-05 |
DE69226887T2 (en) | 1999-04-08 |
EP0496443B1 (en) | 1998-09-09 |
JPH04302472A (en) | 1992-10-26 |
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