EP0485130A2 - Method for forming a metal contact - Google Patents
Method for forming a metal contact Download PDFInfo
- Publication number
- EP0485130A2 EP0485130A2 EP91310146A EP91310146A EP0485130A2 EP 0485130 A2 EP0485130 A2 EP 0485130A2 EP 91310146 A EP91310146 A EP 91310146A EP 91310146 A EP91310146 A EP 91310146A EP 0485130 A2 EP0485130 A2 EP 0485130A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- deposition
- approximately
- aluminum
- integrated circuit
- rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 title description 11
- 239000002184 metal Substances 0.000 title description 11
- 238000000151 deposition Methods 0.000 claims abstract description 90
- 230000008021 deposition Effects 0.000 claims abstract description 71
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 66
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 66
- 238000013508 migration Methods 0.000 claims abstract description 5
- 230000005012 migration Effects 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- 238000005137 deposition process Methods 0.000 abstract description 6
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010409 thin film Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000003870 refractory metal Substances 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000003287 bathing Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
- C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
- C23C16/0281—Deposition of sub-layers, e.g. to promote the adhesion of the main coating of metallic sub-layers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
- C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
- C23C16/20—Deposition of aluminium only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates generally to semiconductor integrated circuits, and more specifically to a method for depositing metal layers in integrated circuits so as to form an improved interlevel contact.
- metal interconnect layers are important to the proper operation of these devices.
- Metal interconnect signal lines make contact to lower conductive layers of the integrated circuit through vias in an insulating layer.
- the metal used to form the interconnect layer should completely fill the via.
- aluminum is especially suited for fabrication of metal interconnect lines in integrated circuits.
- the sputtering process used to apply aluminum thin film layers to an integrated circuit generally results in less than ideal filling of contact vias.
- Large aluminum grains tend to form on the upper surface of the insulating layer. Those grains which form at the edges of the contact via tend to block it before aluminum has a chance to completely fill the via. This results in voids and uneven structures within the via.
- the uneven thickness of the aluminum layer going into the via has an adverse impact on device functionality. If the voids in the via are large enough, contact resistance can be significantly higher than desired. In addition, the thinner regions of the aluminum layer will be subject the well known electromigration problem. This can cause eventual open circuits at the contacts and failure of the device.
- a method for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids.
- the low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.
- Figures 1 and 2 illustrate the formation of a metallic contact according to the present invention
- Figure 3 is a graph illustrating preferred process conditions for formation of an aluminum contact
- Figure 4 illustrates several alternative deposition rate diagrams for forming contacts according to the present invention.
- an integrated circuit device is formed in and on a substrate 10.
- Layer 12 typically has a thickness on the order of approximately 6000-12,000 angstroms.
- a contact via 14 is formed through the oxide layer 12 using a mask and an isotropic etching technique as known in the art. Via 14 is shown as making contact with substrate 10 in Figure 1, but may be formed over a lower interconnect layer as known in the art.
- a barrier metal layer 16 such as a refractory metal, refractory metal nitrode, refractory metal silicide, or combination thereof, is deposited over the surface of the device as known in the art.
- Layer 16 is relatively thin, typically approximately 500-2000 angstroms angstroms thick, and is deposited conformally to cover the bottom and sidewalls of contact opening 14.
- an aluminum layer 18 is deposited over the surface of the device.
- the layer 18 actually completely fills in the via 14 as shown in Figure 2. This occurs because the preferred process conditions enhance the surface migration of the deposited aluminum atoms, so that aluminum formation in the bottom of the via 14 occurs preferentially to formation on the oxide layer 12 near the edges of the via 14. This ensures a high quality, reproducible contact within the via 14, greatly minimizing the problems caused by incomplete filling of the via 14.
- Figures 3 and 4 illustrate preferred conditions for deposition of the aluminum layer 18 in order to provide an improved contact.
- Graph 30 illustrates the deposition rate, in angstroms per second, as a function of the deposition temperature in degrees Celsius.
- the preferred region 32 lies between 400°C-500°C, with the maximum deposition rate lying below a line extending from a rate of about 30 angstroms per second at 400°C to 100 angstroms per second at 500°C.
- the region 32 depicted in Figure 3 outlines, approximately, a preferred pairing of processing conditions under which deposited aluminum migrates into the contact via and fills it while minimizing the formation of voids and uneven regions.
- Process conditions can be varied slightly from that shown in Figure 3 without departing from the teachings of the present invention. For example, temperatures a little below 400°C can be used, as long as the deposition rates are not too high. As the temperature decreases, the mobility of the deposited aluminum atoms goes down, so that incomplete filling of the via occurs if the deposition rates are too high.
- Figure 4 includes four graphs illustrating preferred processes by which an aluminum interconnect layer can be formed. All of these processes utilize, to a greater or lesser degree, processing which occurs within the preferred region 32.
- Each of the curves 40, 42, 44, 46 illustrates a variation in the aluminum deposition rate with time.
- Each curve 40-46 illustrates an alternative process utilizing the concepts of the present invention.
- Each of the four processes shown in Figure 4 preferably uses approximately the same set of initial conditions.
- the wafer on which the integrated circuit device is located is then preheated to the required deposition temperature, over 500°C, by bathing the wafer with a stream of preheated argon gas. Once the wafer has reached the deposition temperature, deposition of the aluminum is resumed at such elevated temperature.
- aluminum is preferably deposited on the device continuously while the device is being heated.
- a small amount of aluminum is deposited on the device while the wafer is at or below 350°C.
- aluminum deposition continues. This gives a layer of aluminum which is deposited with very small grain sizes, tending to minimize grain size growth at later stages.
- the deposition temperature is between 400°C and 500°C, and is typically reached in about 40 seconds.
- Figure 4 shows deposition rate curves for four alternative deposition techniques.
- the initial temperature of the wafer is assumed to be approximately 350°C, with the final deposition temperature being 450°C. Heating the wafer to 450°C takes approximately 40 seconds. It will be appreciated by those skilled in the art that different deposition temperatures may be used. Once the wafer has heated to the deposition temperature, the temperature remains constant.
- Curve 40 in Figure 4 (a) depicts a deposition process in which the deposition rate stays constant during the entire course of depositing the aluminum layer 18. Deposition begins when heat is first applied to the wafer in the chamber, and continues while the wafer heats to 450°C and remains there. At a rate of 40 angstroms per second, an 8000 angstrom thick aluminum layer will take approximately 200 seconds to deposit.
- Figure 4(b) shows an alternative deposition process in which the deposition rate is performed at 40 angstroms per second for the first 20 seconds, and 60 angstroms per second thereafter.
- the temperature is increasing toward the 450°C point during the entire deposition step at 40 angstroms per second, and for the first 20 seconds at 60 angstroms per second.
- the process curve 42 will result in an aluminum layer formation process which takes approximately 140 seconds.
- Curve 44 shows a process in which the initial deposition rate is 40 angstroms per second, followed by an increase to 80 angstroms per second after 20 seconds. After approximately one-third of the entire thickness of the aluminum layer has been deposited, the deposition rate is changed to 30 angstroms per second. This rate is maintained for the deposition of approximately another one-third of the entire layer thickness, followed by an increase of the deposition rate back to 80 angstroms per second.
- curve 44 will take approximately 160 seconds to deposit an 8000 angstrom layer of aluminum. This assumes that 2400 angstroms are deposited during each of the 80 angstrom per second segments, and during the 30 angstrom per second segment.
- the process of Figure 4(c) provides for an initial fast deposition of aluminium, followed by a slow deposition period in which deposited aluminium is given the opportunity to migrate into the contact opening.
- the 30 angstrom deposition period will last for approximately 80 seconds, in order to deposit 2400 angstroms.
- Curve 46 in Figure 4(d) starts in the same manner as curve 44, but ends with a higher deposition rate. Processing time is saved by the faster deposition near the end of the process. By this point in the deposition process, the contact opening has been mostly filled, and the possibility of voiding in the via has been greatly decreased. Thus, there is no harm to depositing aluminum at a rate which falls outside of the preferred region 32.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
- The present invention relates generally to semiconductor integrated circuits, and more specifically to a method for depositing metal layers in integrated circuits so as to form an improved interlevel contact.
- In semiconductor integrated circuits, formation of metal interconnect layers is important to the proper operation of these devices. Metal interconnect signal lines make contact to lower conductive layers of the integrated circuit through vias in an insulating layer. For best operation of the device, the metal used to form the interconnect layer should completely fill the via.
- Because of its physical properties, aluminum is especially suited for fabrication of metal interconnect lines in integrated circuits. However, the sputtering process used to apply aluminum thin film layers to an integrated circuit generally results in less than ideal filling of contact vias. Large aluminum grains tend to form on the upper surface of the insulating layer. Those grains which form at the edges of the contact via tend to block it before aluminum has a chance to completely fill the via. This results in voids and uneven structures within the via.
- This problem is especially acute as integrated circuit devices are fabricated using smaller geometries. The smaller contacts used in these devices tend to have a larger aspect ratio (height to width ratio) than larger geometry devices, which exacerbates the aluminum filling problem.
- The uneven thickness of the aluminum layer going into the via, caused by the step coverage problem just described, has an adverse impact on device functionality. If the voids in the via are large enough, contact resistance can be significantly higher than desired. In addition, the thinner regions of the aluminum layer will be subject the well known electromigration problem. This can cause eventual open circuits at the contacts and failure of the device.
- Many approaches have been used to try to ensure good metal contact to lower interconnect levels. For example, refractory metal layers have been used in conjunction with the aluminum interconnect layer to improve conduction through a via. Sloped via sidewalls have been used to improve metal filling in the via. The use of sloped sidewalls is becoming less common as device sizes shrink because they consume too much area on a chip.
- Even with these techniques, the problems of completely filling a via with aluminum are not solved. In part this is due to the fact that aluminum is deposited at a temperature which tends to encourage fairly large grain sizes. Voids and other irregularities within the contact continue to be problems with current technologies.
- One technique which has been proposed to overcome the via filling problem is to deposit the aluminum interconnect layers at a temperature between 500°C and 550°C. At these temperatures, the liquidity of the aluminium is increased, allowing it to flow down into the vias and fill them. This technique is described, for example, in DEVELOPMENT OF A PLANARIZED Al-Si CONTACT FILLING TECHNOLOGY, H. Ono et al, June 1990 VMIC Conference proceedings, pages 76-82. This references teaches that temperatures below 500°C and above 550°C result in degraded metal filling of contact vias. It is believed that use of such technique still suffers from problems caused by large grain sizes.
- It would be desirable to provide a technique for depositing aluminum thin film layers on an integrated circuit so as to improve coverage in contact vias. It is further desirable that such a technique be compatible with current standard process flows.
- It is therefore an object of the present invention to provide a method for forming an aluminum contact on an integrated circuit.
- It is another object of the present invention to provide such a method in which aluminum fills the contact via while minimizing the number of voids formed therein.
- It is a further object of the present invention to provide such a method which is compatible with current process technology.
- Therefore, according to the present invention, a method is provided for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.
- The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
- Figures 1 and 2 illustrate the formation of a metallic contact according to the present invention; Figure 3 is a graph illustrating preferred process conditions for formation of an aluminum contact; and Figure 4 illustrates several alternative deposition rate diagrams for forming contacts according to the present invention.
- The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.
- Referring to Figure 1, an integrated circuit device is formed in and on a
substrate 10. Aninsulating layer 12, such as a a reflow glass or other oxide layer as known in the art, is formed over thesubstrate 10.Layer 12 typically has a thickness on the order of approximately 6000-12,000 angstroms. A contact via 14 is formed through theoxide layer 12 using a mask and an isotropic etching technique as known in the art.Via 14 is shown as making contact withsubstrate 10 in Figure 1, but may be formed over a lower interconnect layer as known in the art. - A
barrier metal layer 16, such as a refractory metal, refractory metal nitrode, refractory metal silicide, or combination thereof, is deposited over the surface of the device as known in the art.Layer 16 is relatively thin, typically approximately 500-2000 angstroms angstroms thick, and is deposited conformally to cover the bottom and sidewalls ofcontact opening 14. - Referring to Figure 2, an
aluminum layer 18 is deposited over the surface of the device. When thealuminum layer 18 is deposited using the process conditions described below, thelayer 18 actually completely fills in thevia 14 as shown in Figure 2. This occurs because the preferred process conditions enhance the surface migration of the deposited aluminum atoms, so that aluminum formation in the bottom of thevia 14 occurs preferentially to formation on theoxide layer 12 near the edges of thevia 14. This ensures a high quality, reproducible contact within thevia 14, greatly minimizing the problems caused by incomplete filling of thevia 14. - Figures 3 and 4 illustrate preferred conditions for deposition of the
aluminum layer 18 in order to provide an improved contact.Graph 30 illustrates the deposition rate, in angstroms per second, as a function of the deposition temperature in degrees Celsius. Thepreferred region 32 lies between 400°C-500°C, with the maximum deposition rate lying below a line extending from a rate of about 30 angstroms per second at 400°C to 100 angstroms per second at 500°C. - When aluminum is deposited within this
preferred region 32, its surface migration characteristics are enhanced over metal deposited under other conditions. For example, depositing aluminum at temperatures higher than 500°C tends to form large grains, so that blocking of the contact opening occurs as described earlier. If the deposition rate is too high, the deposited aluminum is not able to migrate quickly enough into the via to completely fill it. Therefore, theregion 32 depicted in Figure 3 outlines, approximately, a preferred pairing of processing conditions under which deposited aluminum migrates into the contact via and fills it while minimizing the formation of voids and uneven regions. - Process conditions can be varied slightly from that shown in Figure 3 without departing from the teachings of the present invention. For example, temperatures a little below 400°C can be used, as long as the deposition rates are not too high. As the temperature decreases, the mobility of the deposited aluminum atoms goes down, so that incomplete filling of the via occurs if the deposition rates are too high.
- Figure 4 includes four graphs illustrating preferred processes by which an aluminum interconnect layer can be formed. All of these processes utilize, to a greater or lesser degree, processing which occurs within the
preferred region 32. Each of thecurves - Each of the four processes shown in Figure 4 preferably uses approximately the same set of initial conditions. In the prior art, it is common to deposit a very thin layer of small grain aluminum at a relatively cold temperature, typically below 350°C, and then stop the deposition process. The wafer on which the integrated circuit device is located is then preheated to the required deposition temperature, over 500°C, by bathing the wafer with a stream of preheated argon gas. Once the wafer has reached the deposition temperature, deposition of the aluminum is resumed at such elevated temperature.
- In the present technique, aluminum is preferably deposited on the device continuously while the device is being heated. Thus, a small amount of aluminum is deposited on the device while the wafer is at or below 350°C. As the wafer gradually heats to the desired deposition temperature, aluminum deposition continues. This gives a layer of aluminum which is deposited with very small grain sizes, tending to minimize grain size growth at later stages. The deposition temperature is between 400°C and 500°C, and is typically reached in about 40 seconds.
- Figure 4 shows deposition rate curves for four alternative deposition techniques. For all of the curves in Figure 4, the initial temperature of the wafer is assumed to be approximately 350°C, with the final deposition temperature being 450°C. Heating the wafer to 450°C takes approximately 40 seconds. It will be appreciated by those skilled in the art that different deposition temperatures may be used. Once the wafer has heated to the deposition temperature, the temperature remains constant.
-
Curve 40 in Figure 4 (a) depicts a deposition process in which the deposition rate stays constant during the entire course of depositing thealuminum layer 18. Deposition begins when heat is first applied to the wafer in the chamber, and continues while the wafer heats to 450°C and remains there. At a rate of 40 angstroms per second, an 8000 angstrom thick aluminum layer will take approximately 200 seconds to deposit. - Figure 4(b) shows an alternative deposition process in which the deposition rate is performed at 40 angstroms per second for the first 20 seconds, and 60 angstroms per second thereafter. The temperature is increasing toward the 450°C point during the entire deposition step at 40 angstroms per second, and for the first 20 seconds at 60 angstroms per second. For an 8000 angstrom layer, the
process curve 42 will result in an aluminum layer formation process which takes approximately 140 seconds. -
Curve 44 shows a process in which the initial deposition rate is 40 angstroms per second, followed by an increase to 80 angstroms per second after 20 seconds. After approximately one-third of the entire thickness of the aluminum layer has been deposited, the deposition rate is changed to 30 angstroms per second. This rate is maintained for the deposition of approximately another one-third of the entire layer thickness, followed by an increase of the deposition rate back to 80 angstroms per second. - The process depicted by
curve 44 will take approximately 160 seconds to deposit an 8000 angstrom layer of aluminum. This assumes that 2400 angstroms are deposited during each of the 80 angstrom per second segments, and during the 30 angstrom per second segment. The process of Figure 4(c) provides for an initial fast deposition of aluminium, followed by a slow deposition period in which deposited aluminium is given the opportunity to migrate into the contact opening. The 30 angstrom deposition period will last for approximately 80 seconds, in order to deposit 2400 angstroms. -
Curve 46 in Figure 4(d) starts in the same manner ascurve 44, but ends with a higher deposition rate. Processing time is saved by the faster deposition near the end of the process. By this point in the deposition process, the contact opening has been mostly filled, and the possibility of voiding in the via has been greatly decreased. Thus, there is no harm to depositing aluminum at a rate which falls outside of the preferredregion 32. - It will be appreciated by those skilled in the art that the processes shown in Figure 4 are illustrative and not definitive. Other variations are possible. The precise combination of deposition temperatures and deposition rates can be varied to suit the requirements and restrictions of the particular processes at hand. For example, if large contact openings only are used, faster deposition rates can be made as the voiding problem is not so critical. For processes such as those illustrated by
curves - It is also possible to use the technique of depositing aluminum within the preferred
area 32 without continuously depositing aluminum while the wafer temperature is ramping up to the deposition temperature. As is done on the prior art, a thin layer of aluminum can be deposited at relatively cold temperatures, preferably below 350°C. Deposition is then stopped while the wafer is brought to a temperature between 400°C and 500°C. Deposition is then resumed at a rate within the preferredregion 32, and completed using the teachings set forth above. For example, any of the curves in Figure 4 can be used, with a difference that the initial 40 angstroms per second deposition rate is omitted. - Use of the continuous layer formation while the wafer is being heated, combined with deposition at rates and temperatures within the preferred
region 32, results in small deposited aluminum grain size and very good filling of the via. This is caused both by the good electromigration characteristics of the deposited aluminum layer at the temperatures and deposition rates involved, and by the fact that very small initial grain sizes result in smaller final grain sizes, having less tendency to block off the via before it is completely filled. - While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (19)
- A method for forming an aluminum layer on an integrated circuit, comprising the steps of:
providing an integrated circuit at a temperature below approximately 350°C;
increasing the temperature of the integrated circuit to a deposition temperature; and
depositing aluminum continuously on the integrated circuit during said temperature increasing step. - The method of Claim 1, wherein the deposition temperature is less than approximately 500°C.
- The method of Claim 1, wherein said depositing step is performed at a preselected rate of deposition.
- The method of Claim 3, wherein the preselected deposition rate is changed to a second preselected rate before the integrated circuit reaches the deposition temperature.
- A method for depositing an aluminum layer on a semiconductor integrated circuit, comprising the steps of:
controlling the temperature of the integrated circuit to a preselected temperature less than approximately 500°C; and
depositing aluminum on the integrated circuit at a rate which is low enough to allow surface migration of deposited aluminum to fill low regions in the integrated circuit. - The method of Claim 5, wherein the preselected temperature is between approximately 380°C and approximately 500°C.
- The method of Claim 6, wherein the preselected temperature is between approximately 420°C and 460°C.
- The method of Claim 7, wherein the preselected temperature is approximately 450°C.
- The method of Claim 5, wherein the rate of deposition of aluminum is less than approximately 100 angstroms/sec.
- The method of Claim 5, wherein the rate of deposition for aluminum is changed at least once during the deposition step.
- The method of Claim 10, wherein the rate of deposition of aluminum is less during a middle deposition period than during a beginning deposition period and during an ending deposition period.
- The method of Claim 11, wherein the deposition rate is less than approximately 40 angstroms/sec during the middle deposition period, and greater than approximately 50 angstroms/sec during the beginning and ending deposition periods.
- The method of Claim 12, wherein the aluminum deposition rate during the ending deposition period is greater than approximately 100 angstroms/sec.
- The method of Claim 5, wherein aluminum is deposited at a rate which lies within the selected region of Figure 3.
- A method for forming an aluminum contact in an integrated circuit, comprising the steps of:
forming an insulating layer over a conducting layer;
forming an opening through the insulating layer to expose a portion of the conducting layer;
raising the temperature of the integrated circuit from below approximately 350°C to a preselected value between approximately 400°C and approximately 500°C;
during said temperature raising step, depositing aluminum continuously on the integrated circuit;
after the integrated circuit temperature has reached the preselected value, depositing an aluminum layer on the integrated circuit to a desired thickness;
during said desired thickness depositing step, controlling the rate at which aluminum is deposited to allow deposited aluminum to migrate into the opening so as to provide a substantially complete fill thereof. - The method of Claim 15, wherein the deposition rate is varied, with one portion being faster than approximately 50 angstroms/sec, and another portion being slower than approximately 50 angstroms/sec.
- The method of Claim 17, wherein a last portion of said deposition step is performed at a deposition rate faster than approximately 100 angstroms/sec.
- The method of Claim 18, wherein a first deposition portion is performed at a rate above approximately 60 angstroms/sec, and a second deposition portion is performed at a rate below approximately 40 angstroms/sec.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98105211A EP0856883A3 (en) | 1990-11-05 | 1991-11-01 | Method for forming a metal contact |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US609883 | 1990-11-05 | ||
US07/609,883 US5108951A (en) | 1990-11-05 | 1990-11-05 | Method for forming a metal contact |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98105211A Division EP0856883A3 (en) | 1990-11-05 | 1991-11-01 | Method for forming a metal contact |
EP98105211.1 Division-Into | 1998-03-23 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0485130A2 true EP0485130A2 (en) | 1992-05-13 |
EP0485130A3 EP0485130A3 (en) | 1992-07-22 |
EP0485130B1 EP0485130B1 (en) | 2006-10-04 |
Family
ID=24442738
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91310146A Expired - Lifetime EP0485130B1 (en) | 1990-11-05 | 1991-11-01 | Method for forming a metal contact |
EP98105211A Ceased EP0856883A3 (en) | 1990-11-05 | 1991-11-01 | Method for forming a metal contact |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98105211A Ceased EP0856883A3 (en) | 1990-11-05 | 1991-11-01 | Method for forming a metal contact |
Country Status (5)
Country | Link |
---|---|
US (2) | US5108951A (en) |
EP (2) | EP0485130B1 (en) |
JP (1) | JP3280403B2 (en) |
KR (1) | KR100250919B1 (en) |
DE (1) | DE69133549D1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0586803A1 (en) * | 1992-08-12 | 1994-03-16 | Applied Materials, Inc. | Process for forming low resistance aluminum plug in via electrically connected to overlying patterned metal layer for integrated circuit structures |
EP0655780A1 (en) * | 1993-11-30 | 1995-05-31 | STMicroelectronics, Inc. | Method for forming an aluminum contact |
EP0716447A2 (en) * | 1994-12-05 | 1996-06-12 | AT&T Corp. | Metal layers formed as a composite of sub-layers and devices including same |
EP0856885A2 (en) * | 1997-02-03 | 1998-08-05 | Applied Materials, Inc. | Method and apparatus for reducing the first wafer effect |
WO1999053542A1 (en) * | 1998-04-14 | 1999-10-21 | Applied Materials, Inc. | Method for forming a multi-layered aluminum-comprising structure on a substrate |
US6033534A (en) * | 1992-05-20 | 2000-03-07 | Siemens Aktiengesellschaft | Method for producing an Al-containing layer with a planar surface on a substrate having hole structures with a high aspect ratio in the surface |
WO2001026149A1 (en) * | 1999-10-06 | 2001-04-12 | Infineon Technologies North America Corp. | Heat-up time reduction before metal deposition |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69031903T2 (en) * | 1989-11-30 | 1998-04-16 | Sgs Thomson Microelectronics | Process for making interlayer contacts |
US6271137B1 (en) | 1989-11-30 | 2001-08-07 | Stmicroelectronics, Inc. | Method of producing an aluminum stacked contact/via for multilayer |
US5472912A (en) * | 1989-11-30 | 1995-12-05 | Sgs-Thomson Microelectronics, Inc. | Method of making an integrated circuit structure by using a non-conductive plug |
US5108951A (en) * | 1990-11-05 | 1992-04-28 | Sgs-Thomson Microelectronics, Inc. | Method for forming a metal contact |
US6242811B1 (en) | 1989-11-30 | 2001-06-05 | Stmicroelectronics, Inc. | Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature |
US6287963B1 (en) | 1990-11-05 | 2001-09-11 | Stmicroelectronics, Inc. | Method for forming a metal contact |
JPH04363024A (en) * | 1990-11-30 | 1992-12-15 | Toshiba Corp | Manufacture of semiconductor device |
EP0491503A3 (en) * | 1990-12-19 | 1992-07-22 | AT&T Corp. | Method for depositing metal |
EP0499433B1 (en) * | 1991-02-12 | 1998-04-15 | Matsushita Electronics Corporation | Semiconductor device with improved reliability wiring and method of its fabrication |
TW520072U (en) * | 1991-07-08 | 2003-02-01 | Samsung Electronics Co Ltd | A semiconductor device having a multi-layer metal contact |
JP2946978B2 (en) * | 1991-11-29 | 1999-09-13 | ソニー株式会社 | Wiring formation method |
IT1252056B (en) | 1991-11-22 | 1995-05-29 | St Microelectronics Srl | PROCEDURE FOR THE IMPLEMENTATION OF HIGH STABILITY METAL CONTACTS IN AN INTEGRATED CIRCUIT WITH ONE OR MORE METALIZATION LEVELS |
US6051490A (en) * | 1991-11-29 | 2000-04-18 | Sony Corporation | Method of forming wirings |
JPH05198525A (en) * | 1992-01-21 | 1993-08-06 | Sony Corp | Wiring structure and method of forming wiring |
DE69327600T2 (en) * | 1992-02-28 | 2000-06-21 | St Microelectronics Inc | Manufacturing process of submicron contacts |
JP3332456B2 (en) * | 1992-03-24 | 2002-10-07 | 株式会社東芝 | Semiconductor device manufacturing method and semiconductor device |
KR950009934B1 (en) * | 1992-09-07 | 1995-09-01 | 삼성전자주식회사 | Metalizing method of semiconductor device |
EP0594300B1 (en) * | 1992-09-22 | 1998-07-29 | STMicroelectronics, Inc. | Method for forming a metal contact |
JPH07105441B2 (en) * | 1992-11-30 | 1995-11-13 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US5270255A (en) * | 1993-01-08 | 1993-12-14 | Chartered Semiconductor Manufacturing Pte, Ltd. | Metallization process for good metal step coverage while maintaining useful alignment mark |
US5356836A (en) * | 1993-08-19 | 1994-10-18 | Industrial Technology Research Institute | Aluminum plug process |
KR960026249A (en) | 1994-12-12 | 1996-07-22 | 윌리엄 이. 힐러 | High Pressure, Low Temperature Semiconductor Gap Filling Process |
KR960042974A (en) * | 1995-05-23 | 1996-12-21 | ||
US5892282A (en) * | 1995-05-31 | 1999-04-06 | Texas Instruments Incorporated | Barrier-less plug structure |
US5804251A (en) * | 1995-12-29 | 1998-09-08 | Intel Corporation | Low temperature aluminum alloy plug technology |
US6017144A (en) * | 1996-03-05 | 2000-01-25 | Applied Materials, Inc. | Method and apparatus for depositing highly oriented and reflective crystalline layers using a low temperature seeding layer |
US6291336B1 (en) | 1996-05-20 | 2001-09-18 | Taiwan Semiconductor Manufacturing Company | AlCu metal deposition for robust Rc via performance |
DE19621855C2 (en) | 1996-05-31 | 2003-03-27 | Univ Dresden Tech | Process for producing metallizations on semiconductor bodies using a pulsed vacuum arc evaporator |
US6069051A (en) * | 1996-06-17 | 2000-05-30 | International Business Machines Corporation | Method of producing planar metal-to-metal capacitor for use in integrated circuits |
US6309971B1 (en) | 1996-08-01 | 2001-10-30 | Cypress Semiconductor Corporation | Hot metallization process |
US5911113A (en) | 1997-03-18 | 1999-06-08 | Applied Materials, Inc. | Silicon-doped titanium wetting layer for aluminum plug |
US5913146A (en) * | 1997-03-18 | 1999-06-15 | Lucent Technologies Inc. | Semiconductor device having aluminum contacts or vias and method of manufacture therefor |
TW460597B (en) | 1997-03-27 | 2001-10-21 | Applied Materials Inc | A barrier layer structure for use in semiconductors and a method of producing an aluminum-comprising layer having a 111 crystal orientation |
US5925225A (en) * | 1997-03-27 | 1999-07-20 | Applied Materials, Inc. | Method of producing smooth titanium nitride films having low resistivity |
US6373088B2 (en) | 1997-06-16 | 2002-04-16 | Texas Instruments Incorporated | Edge stress reduction by noncoincident layers |
JP3085247B2 (en) * | 1997-07-07 | 2000-09-04 | 日本電気株式会社 | Metal thin film forming method |
US5882399A (en) * | 1997-08-23 | 1999-03-16 | Applied Materials, Inc. | Method of forming a barrier layer which enables a consistently highly oriented crystalline structure in a metallic interconnect |
US6140228A (en) * | 1997-11-13 | 2000-10-31 | Cypress Semiconductor Corporation | Low temperature metallization process |
US6365514B1 (en) | 1997-12-23 | 2002-04-02 | Intel Corporation | Two chamber metal reflow process |
US6169030B1 (en) * | 1998-01-14 | 2001-01-02 | Applied Materials, Inc. | Metallization process and method |
US5981382A (en) * | 1998-03-13 | 1999-11-09 | Texas Instruments Incorporated | PVD deposition process for CVD aluminum liner processing |
DE19816927A1 (en) * | 1998-04-16 | 1999-09-23 | Siemens Ag | Metal deposition onto a substrate surface with a recess especially a sub-micron size via in semiconductor device production |
US6187673B1 (en) * | 1998-09-03 | 2001-02-13 | Micron Technology, Inc. | Small grain size, conformal aluminum interconnects and method for their formation |
US6136709A (en) * | 1999-10-06 | 2000-10-24 | Infineon Technologies North America Corp. | Metal line deposition process |
US6455427B1 (en) | 1999-12-30 | 2002-09-24 | Cypress Semiconductor Corp. | Method for forming void-free metallization in an integrated circuit |
US6969448B1 (en) | 1999-12-30 | 2005-11-29 | Cypress Semiconductor Corp. | Method for forming a metallization structure in an integrated circuit |
US6420263B1 (en) | 2000-02-28 | 2002-07-16 | International Business Machines Corporation | Method for controlling extrusions in aluminum metal lines and the device formed therefrom |
US6468908B1 (en) | 2001-07-09 | 2002-10-22 | Taiwan Semiconductor Manufacturing Company | Al-Cu alloy sputtering method with post-metal quench |
US6943105B2 (en) | 2002-01-18 | 2005-09-13 | International Business Machines Corporation | Soft metal conductor and method of making |
US7675174B2 (en) * | 2003-05-13 | 2010-03-09 | Stmicroelectronics, Inc. | Method and structure of a thick metal layer using multiple deposition chambers |
US7189645B1 (en) | 2004-04-26 | 2007-03-13 | National Semiconductor Corporation | System and method for adjusting the ratio of deposition times to optimize via density and via fill in aluminum multilayer metallization |
US10429509B2 (en) | 2014-12-24 | 2019-10-01 | Stmicroelectronics Pte Ltd. | Molded proximity sensor |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0107259A2 (en) * | 1982-10-26 | 1984-05-02 | Koninklijke Philips Electronics N.V. | Method of fabricating a semiconductor device in which a layer is evaporatively deposited on a semiconductor body |
EP0273715A2 (en) * | 1986-12-25 | 1988-07-06 | Fujitsu Limited | Method for forming metal layer for a semiconductor device |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3158504A (en) * | 1960-10-07 | 1964-11-24 | Texas Instruments Inc | Method of alloying an ohmic contact to a semiconductor |
US3900598A (en) * | 1972-03-13 | 1975-08-19 | Motorola Inc | Ohmic contacts and method of producing same |
US4107726A (en) * | 1977-01-03 | 1978-08-15 | Raytheon Company | Multilayer interconnected structure for semiconductor integrated circuit |
JPS6047739B2 (en) * | 1977-11-17 | 1985-10-23 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
JPS57139939A (en) * | 1981-02-23 | 1982-08-30 | Seiko Instr & Electronics Ltd | Semiconductor device |
JPS5846641A (en) * | 1981-09-14 | 1983-03-18 | Fujitsu Ltd | Manufacture of semiconductor device |
US4478881A (en) * | 1981-12-28 | 1984-10-23 | Solid State Devices, Inc. | Tungsten barrier contact |
GB2128636B (en) * | 1982-10-19 | 1986-01-08 | Motorola Ltd | Silicon-aluminium alloy metallization of semiconductor substrate |
JPS6063926A (en) * | 1983-08-31 | 1985-04-12 | Fujitsu Ltd | Manufacture of semiconductor device |
US4502209A (en) * | 1983-08-31 | 1985-03-05 | At&T Bell Laboratories | Forming low-resistance contact to silicon |
FR2563048B1 (en) * | 1984-04-13 | 1986-05-30 | Efcis | PROCESS FOR PRODUCING ALUMINUM CONTACTS THROUGH A THICK INSULATING LAYER IN AN INTEGRATED CIRCUIT |
JPS60227446A (en) * | 1984-04-25 | 1985-11-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US4566177A (en) * | 1984-05-11 | 1986-01-28 | Signetics Corporation | Formation of electromigration resistant aluminum alloy conductors |
US4661228A (en) * | 1984-05-17 | 1987-04-28 | Varian Associates, Inc. | Apparatus and method for manufacturing planarized aluminum films |
JPH069199B2 (en) * | 1984-07-18 | 1994-02-02 | 株式会社日立製作所 | Wiring structure and manufacturing method thereof |
GB2164491B (en) * | 1984-09-14 | 1988-04-07 | Stc Plc | Semiconductor devices |
JPS61142739A (en) * | 1984-12-17 | 1986-06-30 | Toshiba Corp | Manufacture of semiconductor device |
US4796081A (en) * | 1986-05-02 | 1989-01-03 | Advanced Micro Devices, Inc. | Low resistance metal contact for silicon devices |
US4721689A (en) * | 1986-08-28 | 1988-01-26 | International Business Machines Corporation | Method for simultaneously forming an interconnection level and via studs |
JPH0691091B2 (en) * | 1986-11-13 | 1994-11-14 | 富士通株式会社 | Method for manufacturing semiconductor device |
JPH081950B2 (en) * | 1986-11-21 | 1996-01-10 | 株式会社東芝 | Method for manufacturing semiconductor device |
JPS63136547A (en) * | 1986-11-27 | 1988-06-08 | Matsushita Electronics Corp | Method of forming wiring for semiconductor device |
US4756810A (en) * | 1986-12-04 | 1988-07-12 | Machine Technology, Inc. | Deposition and planarizing methods and apparatus |
US4782380A (en) * | 1987-01-22 | 1988-11-01 | Advanced Micro Devices, Inc. | Multilayer interconnection for integrated circuit structure having two or more conductive metal layers |
US4988423A (en) * | 1987-06-19 | 1991-01-29 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating interconnection structure |
JPS6477122A (en) * | 1987-09-18 | 1989-03-23 | Fujitsu Ltd | Manufacture of semiconductor device |
US4758533A (en) * | 1987-09-22 | 1988-07-19 | Xmr Inc. | Laser planarization of nonrefractory metal during integrated circuit fabrication |
JPH0719841B2 (en) * | 1987-10-02 | 1995-03-06 | 株式会社東芝 | Semiconductor device |
JPH01160036A (en) * | 1987-12-17 | 1989-06-22 | Oki Electric Ind Co Ltd | Semiconductor device |
NL8800359A (en) * | 1988-02-15 | 1989-09-01 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE |
US4837183A (en) * | 1988-05-02 | 1989-06-06 | Motorola Inc. | Semiconductor device metallization process |
FR2634317A1 (en) * | 1988-07-12 | 1990-01-19 | Philips Nv | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING AT LEAST ONE CONTACT LEVEL THROUGH SMALL DIMENSION CONTACT OPENINGS |
JPH0666287B2 (en) * | 1988-07-25 | 1994-08-24 | 富士通株式会社 | Method for manufacturing semiconductor device |
US4944961A (en) * | 1988-08-05 | 1990-07-31 | Rensselaer Polytechnic Institute | Deposition of metals on stepped surfaces |
JPH02137230A (en) * | 1988-11-17 | 1990-05-25 | Nec Corp | Integrated circuit device |
US4994162A (en) * | 1989-09-29 | 1991-02-19 | Materials Research Corporation | Planarization method |
US4970176A (en) * | 1989-09-29 | 1990-11-13 | Motorola, Inc. | Multiple step metallization process |
US4975389A (en) * | 1989-10-25 | 1990-12-04 | At&T Bell Laboratories | Aluminum metallization for semiconductor devices |
JPH03167915A (en) * | 1989-11-27 | 1991-07-19 | Seiko Instr Inc | Signal processing unit |
US5108951A (en) * | 1990-11-05 | 1992-04-28 | Sgs-Thomson Microelectronics, Inc. | Method for forming a metal contact |
US5108570A (en) * | 1990-03-30 | 1992-04-28 | Applied Materials, Inc. | Multistep sputtering process for forming aluminum layer over stepped semiconductor wafer |
JPH04363024A (en) * | 1990-11-30 | 1992-12-15 | Toshiba Corp | Manufacture of semiconductor device |
KR920010620A (en) * | 1990-11-30 | 1992-06-26 | 원본미기재 | How to Form Aluminum Stacked Contacts / Pathways for Multi-layer Interconnect Lines |
JPH07109030B2 (en) * | 1991-02-12 | 1995-11-22 | アプライド マテリアルズ インコーポレイテッド | Method for sputtering aluminum layer on semiconductor wafer |
-
1990
- 1990-11-05 US US07/609,883 patent/US5108951A/en not_active Expired - Lifetime
-
1991
- 1991-10-29 KR KR1019910019013A patent/KR100250919B1/en not_active IP Right Cessation
- 1991-11-01 DE DE69133549T patent/DE69133549D1/en not_active Expired - Lifetime
- 1991-11-01 EP EP91310146A patent/EP0485130B1/en not_active Expired - Lifetime
- 1991-11-01 EP EP98105211A patent/EP0856883A3/en not_active Ceased
- 1991-11-02 JP JP28814891A patent/JP3280403B2/en not_active Expired - Lifetime
-
1995
- 1995-04-06 US US08/418,122 patent/US5930673A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0107259A2 (en) * | 1982-10-26 | 1984-05-02 | Koninklijke Philips Electronics N.V. | Method of fabricating a semiconductor device in which a layer is evaporatively deposited on a semiconductor body |
EP0273715A2 (en) * | 1986-12-25 | 1988-07-06 | Fujitsu Limited | Method for forming metal layer for a semiconductor device |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6033534A (en) * | 1992-05-20 | 2000-03-07 | Siemens Aktiengesellschaft | Method for producing an Al-containing layer with a planar surface on a substrate having hole structures with a high aspect ratio in the surface |
EP0586803A1 (en) * | 1992-08-12 | 1994-03-16 | Applied Materials, Inc. | Process for forming low resistance aluminum plug in via electrically connected to overlying patterned metal layer for integrated circuit structures |
EP0655780A1 (en) * | 1993-11-30 | 1995-05-31 | STMicroelectronics, Inc. | Method for forming an aluminum contact |
EP0716447A2 (en) * | 1994-12-05 | 1996-06-12 | AT&T Corp. | Metal layers formed as a composite of sub-layers and devices including same |
EP0716447A3 (en) * | 1994-12-05 | 1997-01-08 | At & T Corp | Metal layers formed as a composite of sub-layers and devices including same |
EP0856885A2 (en) * | 1997-02-03 | 1998-08-05 | Applied Materials, Inc. | Method and apparatus for reducing the first wafer effect |
EP0856885A3 (en) * | 1997-02-03 | 2000-05-31 | Applied Materials, Inc. | Method and apparatus for reducing the first wafer effect |
US6139698A (en) * | 1997-02-03 | 2000-10-31 | Applied Materials, Inc. | Method and apparatus for reducing the first wafer effect |
WO1999053542A1 (en) * | 1998-04-14 | 1999-10-21 | Applied Materials, Inc. | Method for forming a multi-layered aluminum-comprising structure on a substrate |
US6454919B1 (en) | 1998-04-14 | 2002-09-24 | Applied Materials, Inc. | Physical vapor deposition apparatus with deposition and DC target power control |
WO2001026149A1 (en) * | 1999-10-06 | 2001-04-12 | Infineon Technologies North America Corp. | Heat-up time reduction before metal deposition |
Also Published As
Publication number | Publication date |
---|---|
KR920010766A (en) | 1992-06-27 |
EP0485130A3 (en) | 1992-07-22 |
US5108951A (en) | 1992-04-28 |
EP0856883A3 (en) | 1998-09-16 |
DE69133549D1 (en) | 2006-11-16 |
JPH04284627A (en) | 1992-10-09 |
KR100250919B1 (en) | 2000-05-01 |
EP0856883A2 (en) | 1998-08-05 |
EP0485130B1 (en) | 2006-10-04 |
JP3280403B2 (en) | 2002-05-13 |
US5930673A (en) | 1999-07-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5108951A (en) | Method for forming a metal contact | |
EP0655780B1 (en) | Method for forming an aluminum contact | |
US5374592A (en) | Method for forming an aluminum metal contact | |
US5472912A (en) | Method of making an integrated circuit structure by using a non-conductive plug | |
US5106781A (en) | Method of establishing an interconnection level on a semiconductor device having a high integration density | |
US5266521A (en) | Method for forming a planarized composite metal layer in a semiconductor device | |
US5523259A (en) | Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer | |
US5668055A (en) | Method of filling of contact openings and vias by self-extrusion of overlying compressively stressed matal layer | |
US6150252A (en) | Multi-stage semiconductor cavity filling process | |
EP0488628A2 (en) | Method of producing an aluminum stacked contact/via for multilayer interconnections | |
EP0558304B1 (en) | Method of forming submicron contacts | |
GB2245596A (en) | A method for forming a metal layer in a semiconductor device | |
US5804251A (en) | Low temperature aluminum alloy plug technology | |
US5926736A (en) | Low temperature aluminum reflow for multilevel metallization | |
US5814556A (en) | Method of filling a contact hole in a semiconductor substrate with a metal | |
US5846877A (en) | Method for fabricating an Al-Ge alloy wiring of semiconductor device | |
US6271137B1 (en) | Method of producing an aluminum stacked contact/via for multilayer | |
US6287963B1 (en) | Method for forming a metal contact | |
EP0552893B1 (en) | Method for forming an aluminium contact | |
US6365514B1 (en) | Two chamber metal reflow process | |
JPH11274303A (en) | Formation of alloy-made mutual connection structure of integrated circuit | |
KR19980065841A (en) | Wiring Formation Method of Semiconductor Device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IT |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB IT |
|
17P | Request for examination filed |
Effective date: 19930119 |
|
17Q | First examination report despatched |
Effective date: 19941209 |
|
APAB | Appeal dossier modified |
Free format text: ORIGINAL CODE: EPIDOS NOAPE |
|
APAB | Appeal dossier modified |
Free format text: ORIGINAL CODE: EPIDOS NOAPE |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: STMICROELECTRONICS, INC. |
|
APAD | Appeal reference recorded |
Free format text: ORIGINAL CODE: EPIDOS REFNE |
|
APAD | Appeal reference recorded |
Free format text: ORIGINAL CODE: EPIDOS REFNE |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
APAF | Appeal reference modified |
Free format text: ORIGINAL CODE: EPIDOSCREFNE |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 21/285 20060101AFI20060824BHEP Ipc: H01L 21/3205 20060101ALI20060824BHEP |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRE;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.SCRIBED TIME-LIMIT Effective date: 20061004 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REF | Corresponds to: |
Ref document number: 69133549 Country of ref document: DE Date of ref document: 20061116 Kind code of ref document: P |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070105 |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20070705 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20101217 Year of fee payment: 20 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20101026 Year of fee payment: 20 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: PE20 Expiry date: 20111031 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION Effective date: 20111031 |