EP0392658B1 - Steuerstromkreis für münzbetätigte Spielautomaten - Google Patents

Steuerstromkreis für münzbetätigte Spielautomaten Download PDF

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Publication number
EP0392658B1
EP0392658B1 EP19900302480 EP90302480A EP0392658B1 EP 0392658 B1 EP0392658 B1 EP 0392658B1 EP 19900302480 EP19900302480 EP 19900302480 EP 90302480 A EP90302480 A EP 90302480A EP 0392658 B1 EP0392658 B1 EP 0392658B1
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EP
European Patent Office
Prior art keywords
data
playfield
microprocessor
line
data signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19900302480
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English (en)
French (fr)
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EP0392658A2 (de
EP0392658A3 (de
Inventor
David L. Poole
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Midway Manufacturing Co
Original Assignee
Midway Manufacturing Co
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Publication date
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Publication of EP0392658A2 publication Critical patent/EP0392658A2/de
Publication of EP0392658A3 publication Critical patent/EP0392658A3/de
Application granted granted Critical
Publication of EP0392658B1 publication Critical patent/EP0392658B1/de
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F17/00—Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32—Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements

Definitions

  • the invention relates to microprocessor controlled coin operated amusement games and in particular to circuits for controlling various electrically actuated devices such as lamps and solenoids and for determining the status of switches in coin operated amusement games.
  • coin operated amusement or arcade-type games of the ball rolling type such as pinball machines
  • include a number of electrically actuated devices such as solenoid actuated kickers and thumper bumpers as well as a large number of lights.
  • these devices are typically under the control of a microprocessor.
  • coin operated games of this type usually include a large number of ball activated switches which provide information to the microprocessor as to the location of the ball for scoring purposes as well as the activation of various lights and other electrically actuated devices.
  • Object of the invention is to overcome the drawbacks of the prior art, especially to reduce the amount of wiring in an amusement machine.
  • an amusement game control system comprising the features of claim 1.
  • a preferred embodiment of the invention provides a circuit for controlling a number of electrically actuated devices in a coin operated amusement game that includes a cable connected to a processor that in turn connects in series a number of the devices.
  • Each device has associated with it a memory element that is connected to a clock signal line and a data line along with a power line which is connected to a power supply and each of the devices. Data is transmitted to the memory elements during a zero-crossing time portion of the power application.
  • the memory elements in turn control the electrically actuated devices.
  • a preferred embodiment of the invention to provides a cable that connects a number of electrically actuated devices in a coin operated amusement game with a processor and a power supply in series such that a memory element associated with each one of the devices responds to a clock signal on the cable to receive and retransmit a series of data signals over the cable in synchronism with the clock signals from the microprocessor. Also included in the cable is a power line which is connected to each of the devices.
  • a preferred embodiment of the invention provides a system for determining the status of switches in a coin operated amusement game wherein a cable connects each of the switches in series and a memory element is associated with each of the switches.
  • a load signal is transmitted from a processor to each memory element which causes the status of that switch to be loaded in the memory element and in response to clock signals from the processor, data is transmitted via the cable to the processor in serial form representing the status of each of the switches.
  • FIG. 1 provides a perspective view of a simplified portion of a typical coin actuated pinball machine 10 including a playfield 12 upon which a ball (not shown) rolls. Attached to the surface of the playfield 12 are various electrically actuated devices such as solenoid actuated kickers 14-20 and thumper bumpers 22-26. Also included are a number of lights 28-40 aligned in the plane of the playfield 12. The lights 28-40 are normally lit in a selective manner according to the scoring logic of the game 10.
  • the playfield 12 additionally includes a number of ball activated switches that are located about the playfield 12 such as the switches indicated at 42-46.
  • the switches shown at 42-46 are secured flush with the playfield surface 12 and can be, as is well-known in the art, pressure or electromagnetically activated.
  • the game 10 also includes a pair of player activated flippers 48 and 50 for propelling the ball up the playfield 12. As is conventional the flippers 48 and 50 are controlled by buttons such as 52 located on the sides of the game 10.
  • FIG. 2 is an illustration of method of connecting lamps such as 28-40 and devices such as 14-20 and 22-26 to both a game control microprocessor 54 and a power supply 56.
  • each lamp and each electrically actuated device will have associated with it an assembly board indicated by 58A-C for the lamps and by 60A-C for the electrically actuated devices.
  • Each of the lamp assembly boards 58A-C are of generally similar construction and include a flip-flop memory element 62A-C, a switching transistor 64A-C and a mass termination connector 66A-C.
  • lamps 68A-C which represent the lights or lamps 28-40 of FIG. 2.
  • each of the transistors 64A-C is connected to a ground wire 70 by means of a line 72A-C connected to a first terminal on the connectors 66A-C.
  • the lamps 68A-C are connected to a 12 volt DC power line 74, from the power supply 56, by lines 76A-C connected to a second terminal of the connectors 66A-C.
  • Power is supplied to the flip-flop 66A-C by a 5 volt power line from the power supply 56 which is connected from a third terminal of the connectors 66A-C that in turn is connected to each flip flop 66A-C by lines 80A-C.
  • Clock signals from the processor 54 are provided to the clock inputs C of each of the flip-flops 66A-C by a clock signal line 82.
  • Clock line 82 is attached to a fourth terminal of each connector 66A-C and lines 84A-C in turn are connected to the C terminals of each flip-flop 62A-C.
  • a data or state input D of each flip-flop 62A-C is connected to a fifth terminal on each connector 66A-C by lines 86A-C.
  • Each of the connectors 66A-C includes a sixth terminal which is connected by lines 88A-C to a noninverting logic output Q of each of the flip-flops 62A-C.
  • the inverting logic output Q of each flip-flop 62A-C is applied to the base of the corresponding transistors 64A-C by lines 90A-C which includes resistors 92A-C.
  • the first assembly board 58A differs from the boards following it in that the fifth terminal of the connector 66A is connected to a DATA 1 line 94 that in turn is connected to the processor 54.
  • a logic line 96 then connects the sixth terminal of connector 66A with the fifth terminal of connector 66B.
  • each sixth terminal of connectors 66A through 66C of a series of assembly boards such as 58A-C is connected to the fifth terminal of the connector 66B through 66C of the following assembly board.
  • the object of the arrangement shown in FIG. 2 is to light the lamps 68A-C in accordance with game play which is under control of the microprocessor 54.
  • the status of each lamp 68A-C is reset. In the preferred embodiment of the invention these intervals will correspond to the zero crossing point of the 12 volt power supply voltage on line 74.
  • the power on line 74 can be either a full or a half wave rectified DC voltage.
  • the relative merits or criteria for selecting various reset intervals will be discussed in connection with FIGS. 5-7.
  • the processor 56 will generate a data stream on the DATA 1 line 94 in synchronism with the CLOCK signal on line 82.
  • each of the flip-flops 62A-C outputs Q and Q will be set to the logic states reflecting the desired on-off conditions of the lamps 68A-C at the end of the number CLOCK cycles corresponding to the number of lamps 68A-C.
  • the non-inverting output Q will be effective to control the flow of current through the lamps 68A-C by applying a switching voltage to the base of each of the transistors 64A-C.
  • the flip-flop or memory elements 62A-C will serve to maintain the lamps 68A-C in a predetermined on or off condition until the next reset interval when a new series of CLOCK signals and corresponding DATA 1 signals are generated by the processor 54.
  • the device assembly boards 60A-C are constructed and operate in essentially the same manner as the lamp assembly boards 58A-C.
  • the principal differences are that a 40 volt half or full wave DC voltage is applied over a line 97 from the power supply 56 to each electrically actuated device 98A-C on the boards 60A-C and a DATA 2 signal is applied from the processor 54 over a line 100 to the data input D of each flip-flop 102A-C on the boards 60A-C. Otherwise the elements on the boards 60A-C correspond to the elements on the boards 58A-C.
  • switching transistors 106A-C correspond in function to the transistor 64A-C in that they serve to apply power to the devices 98A-C in response to the Q outputs of the flip-flops 102A-C.
  • mass termination connectors 104A-C are configured with six terminals as are the connectors 66A-C with lines 78 and 82 attached to corresponding terminals.
  • the logic output Q of the flip-flops 104A-C are transmitted for example by lines 108 and 110 to the following boards 60B through 60C.
  • DATA 2 signals from processor 54 on line 100 are transmitted in synchronism with CLOCK signals on line 82 to board 60A during a reset interval.
  • DATA 2 signals represent the desired operating condition of the devices 98A-C.
  • operation of the devices 98A-C can be controlled by the processor 54 in accordance with a game play program.
  • the sequence of the DATA 2 signal represent the desired operating condition of the devices 98A-C.
  • FIG. 2 illustrates an arrangement whereby lamp assembly boards 58A-C are connected in series to the processor 54 and power supply 56 and the electrically actuated device assembly boards 60A-C are likewise connected in series to the processor 54 and power supply 56.
  • the connectors 66A-C and 104A-C would have one additional terminal to accommodate both the 12 volt power line 74 or the 40 volt power line.
  • the lamps 68A-C and the electrically actuated devices 106A-C would be connected to the appropriate terminal on the connectors 66A-C or 104A-C.
  • FIG. 3 illustrates a circuit for providing information to the processor 54 of the condition of a number of switches or ball sensing devices such as 112A-C.
  • a sensor board assembly 114A-C Associated with each switch 112A-C is a sensor board assembly 114A-C.
  • Each sensor board includes a memory element or flip-flop 116A-C, an OR gate 118A-C, a first AND gate 120A-C configured with an inverting input terminal 122A-C, a second AND gate 124A-C, and a mass termination connector 126A-C.
  • the output of the first AND gate 120A-C is connected to one input of the OR gate 118A-C by a line 128A-C and the output of the OR gate 118A-C is connected to the data input terminal D of the flip-flops 116A-C by a line 130A-C.
  • Each of the switches 112A-C is connected by a line 132A-C to a noninverting terminal of the first AND gate 120A-C and the inverting inputs 122A-C are connected to the fourth terminal of the connector 126A-C by a line 134A-C.
  • each flip-flop 116A-C is connected to the second terminal of the connector 126A-C by a line 136A-C; the clock terminal C is connected to the first terminal of the connectors 126A-C by a line 138A-C; and the inverted outputs Q are connected by lines 140A-C to the third terminal of the connectors 126A-C.
  • Connecting the output of each of the second AND gates 124A-C to a second input of the OR gate 118A-C are lines 142A-C and the two inputs to the second AND gate 124A-C are connected to the fourth and fifth terminals of connectors 126A-C by lines 144A-C and 146A-C respectively.
  • the processor 54 receives data from each of the connectors 114A-C via a data line 148 connected to the third terminal of connector 126A and applies a LOAD signal over a line 150 to the fourth terminal of each connector 126A-C.
  • the CLOCK signal is transmitted over the line 82 to the first terminal of connectors 126A-C and a 5 volt voltage is supplied to the second terminal of each connector 126A-C by the line 78.
  • each of the connectors 126A-C has its fifth terminal connected to the third terminal of the following terminal as shown by lines 152 and 154.
  • the processor 54 will generate a LOAD signal on line 150 in synchronism with a first CLOCK signal on line 82 as illustrated by 156 and 158 of FIG. 4.
  • the low LOAD signal 156 applied to input terminal 122A-C which permits signals on lines 132A-C representing the status of switches 112A-C to be transmitted through AND gates 120A-C and OR gates 118A-C to the data input terminals D of flip-flops 116A-C.
  • the simultaneous CLOCK signal 158 applied to terminal C will result in a logic output signal on terminal Q of the flip-flops 116A-C representing the status of each switch 112A-C.
  • FIGS. 5 and 6 provide an illustration of the flexibility of the invention with respect to the construction of game apparatus.
  • the lamp assembly boards 58A-C and device assembly boards 60A-C of FIG. 5 are represented generally by the block denoted by reference numerals 164A-C and 166A-C.
  • the boards 164A-C and 166A-C can be either the lamp assembly boards 58A-C or the electrically activated device boards 60A-C or mixture of the two types of assembly boards.
  • the boards in the blocks 164A-C and 166A-C are referred to as Device 1 through Device N.
  • FIG. 5 The operation of the circuit shown in FIG. 5 is generally similar to the operation of the circuit of FIG.2.
  • One of the objects of FIG.5 is to illustrate the fact that the assembly boards such as 164A-C and 166A-C can effectively be arranged in a number of different parallel string configurations. For example some games may only require a limited number of lamps or electrically actuated devices so that only a single string such as 164A-C may be necessary. On the other hand, some games may require more devices than can be readily accommodated on a single string. For instance in the case of a string of lamps such as 58A-C of FIG.
  • FIG. 6 is a block diagram illustrating an embodiment of the invention combining a string of device assembly boards 176A-C and a string of switch boards 178A-C.
  • the diagram of FIG. 6 is simplified with respect to the schematic diagrams of FIGS. 2 and 3 in that the power supply lines 74, 78, 82 and 96 along with ground line 70 are omitted. Operation of the arrangement of FIG.6 is similar to the circuits of FIGS. 2 and 3.
  • Device control data is transmitted from the processor 54 over a line 180 to the devices 176A-C in synchronism with CLOCK signals on a line 182.
  • the switch boards 178A-C will respond to a LOAD signal on line 150 and CLOCK signals on line 180 to transmit data to the processor 54 representing the condition of the switches such as 112A-C associated with the boards 178.
  • switch boards such as 178A-C in a string with device boards such as 164A-C. Such a combination would require additional terminals on the mass termination connectors such as 126A-C of FIG. 2 in order to accommodate the load line 150 and the return data line 148.
  • FIG. 7 Illustrated in FIG. 7 is a full wave rectified D.C. voltage indicated at 184 along with corresponding half wave rectified D.C. voltages indicated at 186 and 188 for phases A and B respectively of the D.C. voltage 184.
  • a single full wave rectified power supply D.C. voltage such as 184 can be applied to the devices 164A-C and 166A-C or alternatively two half wave rectified D.C. voltages such as 186 and 188 can be used on lines 172 and 174 of FIG. 5.
  • An advantage of using two half wave rectified voltages 186 and 188 instead of a single full wave rectified voltage 184 is that it would permit more time to transmit the data pulses on line 168 to the devices 164A-C and 166A-C.
  • the data on line 172 would be loaded into devices 164A-C during phase B and the data on line 174 would be loaded into devices 166A-C during phase A.
  • this approach may require separate sources of clock signals for the two sets of devices 164A-C and 166A-C as indicated by a dashed line 185 in FIG. 5 to avoid interfering with the operation of the devices that currently have power applied on lines 172 or 174.
  • the processor 54 would have an entire half phase to load the devices with data on line 168 many more devices could be attached to a string without the previously discussed potential flicker problem.
  • the data loading preferably should be accomplished in a very small time interval near the zero crossing point such as indicated at 189 of FIG. 7.
  • a zero crossing detector circuit 190 is connected to an A.C. power source 191.
  • the A.C. power source 191 provides A.C. power to the D.C. power supply 56 and the zero crossing detector 190 indicates to the microprocessor 54 the zero crossing points of the A.C. power and hence the zero crossing points such as 189 of the D.C. voltages on lines 172 and 174.
  • FIG. 8 Provided in FIG. 8 is an illustration a lamp assembly indicated generally by 192 that can be used to secure an electronically actuated device such as the lamp of 68A of FIG. 2 to the underside of the playfield 12.
  • a bracket 194 which can be used to attach the assembly 192 to the playfield 12 is secured to a lamp socket 196 and a printed circuit board 198.
  • the transistor 64A and the mass termination connector 66A are connected to the printed circuit board 198.
  • an integrated circuit 200 which contains the flip flop 62A.
  • the electrical connections on the printed circuit board 198 are not shown in FIG. 8 but would in practice conform to the connections shown in FIG. 2.
  • the arrangement of FIG. 8 provides an illustration of a preferred physical embodiment of the assembly boards 58A-C of FIG. 2 and it will be appreciated that similar structures can be used for the device assembly boards 60A-C.
  • the invention as discussed above has a number of very substantial advantages including the ability to connect a large number of electrically actuated devices such as lamps and solenoid actuated devices to a microprocessor in a flexible manner while using a minimum of electrical wiring.
  • the use of assembly boards of the type shown in FIG. 8 makes it possible to further reduce costs by essentially using a single assembly with standard components to connect the devices to a microprocessor in a coin operated amusement game.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Pinball Game Machines (AREA)
  • Coin-Freed Apparatuses For Hiring Articles (AREA)

Claims (9)

  1. Spielautomat-Steuersystem, welches folgendes umfaßt: einen Mikroprozessor (54), eine Mehrzahl elektrischer Spielfeldmerkmale (22-26, 28-40, 42-48), eine Mehrzahl diskreter Steuerstromkreise (58, 104), wobei sich jeder der Steuerstromkreise (58, 104) physisch in der Nähe eines jeweiligen der Spielfeldmerkmale befindet, einen Datenbus (94, 100), der an den Mikroprozessor (54) angeschlossen ist und an den die Steuerstromkreise (58, 104) in einer vorgegebenen Reihe angeschlossen sind, und Mittel zum Aufschalten von Datensignalen auf den Datenbus (90, 100), wobei jedes Datensignal Steuerinformationen darstellt, die ein jeweiliges der Spielfeldmerkmale betreffen, wobei die Datensignale in einer Reihe, deren Reihenfolge der Reihenfolge der Steuerstromkreise (58, 104) in der vorgegebenen Reihe entspricht, ohne Adresseninformationen auf den Datenbus (90, 100) aufgeschaltet werden und wobei das System dazu angeordnet ist, dasjenige Spielfeldmerkmal, auf welches ein Datensignal bezogen ist, anhand der Position dieses Datensignals in der Reihe von Signalen zu identifizieren, die auf den Datenbus aufgeschaltet sind.
  2. System nach Anspruch 1, bei dem die Steuerstromkreise (58, 104) mittels einer Taktsignalleitung (82) parallel an den Mikroprozessor (54) angeschlossen sind und Mittel dazu vorgesehen sind, ansprechend auf das Aufschalten eines Taktsignals auf die Taktsignalleitung (82) Datensignale über den Datenbus (94, 100) von einem Steuerstromkreis (54, 104) zu einem in der vorgegebenen Reihe danebenliegenden Steuerstromkreis (54, 104) zu übertragen.
  3. System nach Anspruch 1 oder 2, bei dem der Mikroprozessor (54) ein Mittel zum Erzeugen eines Stroms der Datensignale und zum Aufschalten des Stroms von Datensignalen auf den Datenbus (94, 100) umfaßt, wobei jedes der Datensignale eine Steuereingabe für ein jeweiliges der Spielfeldmerkmale darstellt und jedes Spielfeldmerkmal nur von dem entsprechenden der Datensignale in jedem Strom gesteuert wird.
  4. System nach Anspruch 3, bei dem jeder Steuerstromkreis (58, 104) ein Steuerschaltermittel (64, 106) zum Aufschalten von Strom von einer Stromversorgungseinheit auf das jeweilige Spielfeldmerkmal umfaßt.
  5. System nach Anspruch 4, bei dem das Steuerschaltermittel einen Transistor (64, 106) umfaßt.
  6. System nach Anspruch 3, 4 oder 5, bei dem jeder Steuerstromkreis (58, 104) Verriegelungsmittel (62, 102) zum Speichern des Datensignals umfaßt, das dem zugeordneten Spielfeldmerkmal (68, 98) entspricht.
  7. System nach Anspruch 6, bei dem das Mittel zum Verriegeln ein Flipflop (62, 102) umfaßt.
  8. System nach einem der Ansprüche 3 bis 7, bei dem das Mittel zum Aufschalten von Datensignalen die Datensignale derart überträgt, daß das n-te Spielfeldmerkmal vom (N+1-n)-ten Datensignal in der bestimmten Folge gesteuert wird, wobei N die Gesamtzahl der Spielfeldmerkmale ist.
  9. System nach einem der vorhergehenden Ansprüche, welches eine Mehrzahl von Spielfeldmerkmalen in Gestalt von Spielfeldschaltern (42-46) umfaßt, die jeweils an einen jeweiligen Steuerstromkreis (104) angeschlossen sind, wobei jeder Steuerstromkreis (104) dazu angeordnet ist, durch Übertragen eines Datensignals ohne Adresseninformationen über den Datenbus (100) dem Mikroprozessor (54) den Status seines entsprechenden Schalters (42-46) mitzuteilen, wobei der Mikroprozessor (54) die Übertragung von Datensignalen von den Steuerstromkreisen (104) an den Mikroprozessor (54) derart steuert, daß jedes Datensignal seinem entsprechenden Schalter (42-46) zugeordnet werden kann.
EP19900302480 1989-04-13 1990-03-08 Steuerstromkreis für münzbetätigte Spielautomaten Expired - Lifetime EP0392658B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33732489A 1989-04-13 1989-04-13
US337324 1999-06-21

Publications (3)

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EP0392658A2 EP0392658A2 (de) 1990-10-17
EP0392658A3 EP0392658A3 (de) 1991-09-25
EP0392658B1 true EP0392658B1 (de) 1994-10-12

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EP19900302480 Expired - Lifetime EP0392658B1 (de) 1989-04-13 1990-03-08 Steuerstromkreis für münzbetätigte Spielautomaten

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EP (1) EP0392658B1 (de)
JP (1) JPH0380882A (de)
AU (1) AU619100B2 (de)
CA (1) CA2012031A1 (de)
DE (1) DE69013207T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5074558A (en) * 1990-12-10 1991-12-24 Williams Electronics Games, Inc. Matrix address decoder for pinball games
US5137278A (en) * 1991-03-14 1992-08-11 Williams Electronics Games, Inc. Amusement device with trading card dispenser
US5257179A (en) * 1991-10-11 1993-10-26 Williams Electronics Games, Inc. Audit and pricing system for coin-operated games
JP6062998B2 (ja) * 2015-05-15 2017-01-18 株式会社ニューギン 遊技機

Family Cites Families (10)

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Publication number Priority date Publication date Assignee Title
AU6387369A (en) * 1969-11-17 1971-05-20 Davidson Holdings Pty. Limited Control units for ball gates of automatic gaming tables
US4198051A (en) * 1975-11-19 1980-04-15 Bally Manufacturing Corporation Computerized pin ball machine
US4335809A (en) * 1979-02-13 1982-06-22 Barcrest Limited Entertainment machines
ES8507274A1 (es) * 1983-05-02 1985-09-16 Ainsworth Nominees Pty Ltd Perfeccionamientos en los sistemas de maquinas de juego
US4575622A (en) * 1983-07-29 1986-03-11 Esac, Inc. Electronic access control system for coin-operated games and like selectively accessible devices
US4652998A (en) * 1984-01-04 1987-03-24 Bally Manufacturing Corporation Video gaming system with pool prize structures
CA1245361A (en) * 1984-06-27 1988-11-22 Kerry E. Thacher Tournament data system
WO1986005113A1 (en) * 1985-03-08 1986-09-12 Sigma Enterprises, Incorporated Slot machine
ES2001771A6 (es) * 1986-09-02 1988-06-16 Maquinas Automaticas Computeri Sistema de control de baterias de maquinas en juego
AU606454B1 (en) * 1988-09-07 1991-02-07 Kabushiki Kaisha Sophia Game system

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DE69013207D1 (de) 1994-11-17
CA2012031A1 (en) 1990-10-13
DE69013207T2 (de) 1995-03-30
AU619100B2 (en) 1992-01-16
EP0392658A2 (de) 1990-10-17
AU5311590A (en) 1990-10-18
EP0392658A3 (de) 1991-09-25
JPH0380882A (ja) 1991-04-05

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