EP0388798B1 - Dispositif pour emmagasiner l'adresse d'une unité processeur de surveillance en service - Google Patents

Dispositif pour emmagasiner l'adresse d'une unité processeur de surveillance en service Download PDF

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Publication number
EP0388798B1
EP0388798B1 EP90104914A EP90104914A EP0388798B1 EP 0388798 B1 EP0388798 B1 EP 0388798B1 EP 90104914 A EP90104914 A EP 90104914A EP 90104914 A EP90104914 A EP 90104914A EP 0388798 B1 EP0388798 B1 EP 0388798B1
Authority
EP
European Patent Office
Prior art keywords
unit
address
processor unit
eeprom
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP90104914A
Other languages
German (de)
English (en)
Other versions
EP0388798A1 (fr
Inventor
Karl Dr. Herrmann
Gerhard Musil
Ferdinand Narjes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Siemens AG
Philips Patentverwaltung GmbH
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Philips Patentverwaltung GmbH, Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Siemens AG
Priority to AT90104914T priority Critical patent/ATE102413T1/de
Publication of EP0388798A1 publication Critical patent/EP0388798A1/fr
Application granted granted Critical
Publication of EP0388798B1 publication Critical patent/EP0388798B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/40—Monitoring; Testing of relay systems
    • H04B17/401—Monitoring; Testing of relay systems with selective localization
    • H04B17/406—Monitoring; Testing of relay systems with selective localization using coded addresses

Definitions

  • the invention relates to an in-operation monitoring processor unit as specified in the preamble of claim 1.
  • the arrangement for in-service monitoring works according to a call procedure that allows central monitoring of digital signal transmission networks with line, branch and star structure and offers the advantages of self-addressing of the entire network, so that an expensive and error-intensive manual presetting of addresses not applicable.
  • the processor units which are connected to one another via a telegram transmission network, are automatically set to different addresses.
  • a memory which is contained in the relevant processor unit, is used to store the address.
  • the addressing method can be used to re-address all processor units of the device for in-service monitoring.
  • the object of the invention is to provide the newly used processor unit with the address of the replaced processor unit in the event of an exchange of an already addressed processor unit, without it being necessary to address the entire route again.
  • the arrangement for solving this problem is designed in the manner specified in the characterizing part of patent claim 1.
  • the units with which the processor unit is housed in one and the same insert are, in particular, intermediate regenerators of a digital signal transmission path, line terminals or the like.
  • the measures according to the invention result in the subscriber address being secured, so that a processor unit which has just been inserted advantageously takes on the address which the processor unit previously located at this point advantageously takes. This ensures that there are not two processor units or monitoring modules with the same address in the network.
  • the locating section shown in FIG. 1 comprises a message transmission link with two digital signal ground line sections connected in chain A and B, hereinafter referred to as line sections A and B.
  • the line section A extends from the line terminal device 31 via the intermediate regenerators 41 and 42 to the line terminal device 32.
  • the line section B comprises the line terminal devices 33 and 34 and the intermediate regenerators 43 and 44 arranged therebetween.
  • the broken line representation of the four-wire transmission path between the intermediate regenerators 41 and 42 and 43 and 44 expresses that line sections A and B may optionally contain further intermediate regenerators.
  • the line network shown can be supplemented in particular to form a star network.
  • the functionality and transmission properties of the message transmission link can be monitored.
  • a processor unit is provided in the line terminals 31 ... 34 and the intermediate regenerators 41 ... 44, which can be operated as a master or as a slave.
  • the processor unit 1 in the line terminal 31 is set as a central call or control unit or master.
  • the other processor units 2A1 ... 2B4 are each set as a substation or slave and each receive monitoring data from the individual devices of the message transmission link to be monitored via an internal bus.
  • the processor unit 1 forms a device for sequence control, which calls the further processor units 2A1... 2B4 one after the other by means of call telegrams with their addresses, the monitoring data of which is received by response telegram and evaluated.
  • a location module can be provided, with the aid of which errors that occur can be located.
  • the processor units are expediently by controlled a microprocessor. They have one connection in the line terminal 31 ... 34 and two connections in the intermediate regenerator 41 ... 44 - one for each direction - for coupling and decoupling into the auxiliary channel superimposed on the useful signal. In addition, they each have a connection a for a network node.
  • the monitoring data of the line terminals and the intermediate regenerators are each transmitted from one processor unit to the next processor unit via a telemetry channel, which is an auxiliary channel superimposed on the useful signal.
  • the transmission link belongs in particular to a transmission device in the synchronous digital hierarchy.
  • the line terminals 31 ... 34 are synchronous line multiplexers and the intermediate regenerators 41 ... 44 are synchronous line regenerators.
  • the telemetry channel is one of the so-called overhead channels reserved for national use.
  • connection between the line sections A and B takes place via a bidirectional data bus a, which connects the line terminals 32 and 33 to one another.
  • a personal computer can be connected to the line terminals 31 ... 34 and intermediate regenerators 41 ... 44, with the aid of which the monitoring data of the entire location area can be evaluated and displayed.
  • the in-service monitoring process works according to the polling principle.
  • the master asks the devices to be monitored - intermediate regenerators and line end devices - cyclically with their Address by sending a request telegram. Within this cycle, it also calls its own station and then sends out the data of its station like a slave. It receives the response telegrams sent by the devices called up, compares the incoming data with entered threshold values and triggers alarms when the threshold values are exceeded.
  • the addresses are assigned to the individual devices using an automatic addressing procedure.
  • the address assignment of the devices is hierarchical.
  • An address byte is provided for the addressing of line sections, a further address byte for the addressing of the processor units within a line section.
  • This type of addressing is expressed in FIG. 1 by adding the address, consisting of an indication of the line section and a counting number within the line section, to the reference number 2 used for the processor units.
  • the addressing of the processor units can proceed in accordance with the older proposal mentioned at the outset such that a processor unit connected to one of the two ends of the transmission section and serving as an addressing unit in addressing mode issues an addressing telegram containing an address to the transmission section and that the processor units of the transmission section transmit the addressing telegrams and / or pass on a new addressing message after an incrementation of the address contained in the addressing message and that the processor unit of the transmission section stores the address of the received or sent addressing message as its own address.
  • FIG. 2 shows a block diagram of an insert in which, in addition to the processor module 60, the further modules 61, 62 and 63 are accommodated.
  • the modules 61 ... 63 contain functional units 81 ... 83, each of which is provided with an EEPROM (not shown).
  • the processor assembly 60 and the modules 61, 62 and 63 are connected to one another via the bidirectional bus d.
  • the exchange of information via the bus d is controlled by the central station 70 contained in the processor module 60 and assigned to the processor unit 2, specifically by a so-called bus master.
  • the control center 70 exchanges information via the bus d with the substations, so-called bus slaves 71, 72 and 73, which are arranged in the modules 61, 62 and 63.
  • the individual modules 61 ... 63 contain EEPROMs in order to use them to identify characteristic data of the modules such as. B. permanent storage of manufacturer identification, module designations or settings.
  • the modules 61 ... 63 are connected to each other by an internal network, in particular by one or more buses.
  • One of these is the internal device bus d, via which the processor unit 2 can interrogate faults in the modules 61 ... 63.
  • Device settings are expediently also made via this bus, which are then stored locally in the EEPROMs.
  • the address of the processor unit 2 is stored in a RAM of the processor unit 2 itself and additionally outside of the processor unit 2 in at least one EEPROM. It can be useful to arrange the EEPROM on a circuit board that is located on the back of the insert and is permanently connected to it.
  • the EEPROMs are on other modules 61 ... 63 of the same use.
  • the EEPROMS's each belong to an interchangeable unit that can be easily replaced in the event of a defect.
  • the modules 61 ... 63 are connected to the processor unit 2 such that the EEPROMs of the modules 61 ... 63 could be written and read from the processor unit 2.
  • This network is generally the monitoring bus, which can also be used to make settings that are permanently saved in the EEPROM modules.
  • Another advantage of storing the address on the modules 61 ... 63 is that when replacing such a module, the last place of use is recorded and thus the diagnosis of errors is made easier.
  • the processor unit 2 Before inserting a processor unit or before switching on the operating voltage, one or more of the other assemblies 61 ... 63 of the insert may have been replaced.
  • the processor unit 2 therefore expediently carries out a plausibility check after it has been started up and the addresses have been read from the EEPROMs of the modules 61 ... 63. In the simplest case, this is a majority decision.
  • the security of the control can be further increased by the fact that when there are different addresses, a corresponding message is issued and the result is confirmed by another body, e.g. B. is requested via a locally connected computer or other control unit.
  • the monitoring module of the insert or that part of a module that is responsible for its monitoring in the event of a detected defect in this module, which is likely to lead to its replacement, deletes the processor unit address stored on the module concerned or for declared invalid.
  • the measures mentioned ensure that there are not two slaves with the same address in the network.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Electromagnetism (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)
  • Communication Control (AREA)
  • Selective Calling Equipment (AREA)

Claims (8)

  1. Dispositif pour mémoriser l'adresse d'une unité à processeur, qui fait partie d'un dispositif servant à contrôler en fonctionnement un dispositif de transmission d'informations, et dans lequel une unité d'appel et des unités à processeur (2) pourvues d'adresses échangent entre elles des informations par l'intermédiaire d'un réseau de transmission de télégrammes de telle sorte que des télégrammes d'interrogation de l'unité d'appel et des télégrammes de réponse des unités à processeur (2) sont transmis, et dans lequel les unités à processeur (2) sont pourvues d'adresses, qui peuvent être respectivement mémorisées, au cours d'un procédé d'adressage, caractérisé par le fait
    que l'unité à processeur (2) est réalisée sous la forme d'un module et peut être enfichée avec d'autres modules (61, 62, 63) dans un insert commun et que l'adresse de l'unité à processeur (2) peut être mémorisée dans une mémoire EEPROM, qui, dans l'insert, est disposée sur une plaquette à circuits imprimés, qui ne fait pas partie du module de l'unité à processeur (2), et est raccordée électriquement à l'unité à processeur (2) de telle sorte que la mémoire EEPROM peut être enregistrée et lue à partir de l'unité à processeur (2).
  2. Dispositif suivant la revendication 1, caractérisé par le fait que la mémoire EEPROM est disposée sur une plaquette à circuits imprimés, qui est disposée sur la face arrière de l'insert et est raccordée de façon fixe à ce dernier.
  3. Dispositif suivant la revendication 1, caractérisé par le fait qu'au moins l'un des autres modules (61, 62, 63) de l'insert contient une mémoire EEPROM, dans laquelle peut être mémorisée l'adresse de l'unité à processeur.
  4. Dispositif suivant la revendication 3, caractérisé par le fait que l'insert contient un bus de contrôle (d), au moyen duquel l'unité à processeur échange des informations avec au moins une partie des modules et que la mémoire EEPROM peut être enregistrée et lue par l'intermédiaire du bus.
  5. Dispositif suivant la revendication 3 ou 4, caractérisé par le fait que lors de l'insertion de l'un des modules (61, 62, 63), dans l'insert en fonctionnement, l'unité à processeur (2) déclenche la mémorisation de son adresse dans la mémoire EEPROM de ce module.
  6. Dispositif suivant la revendication 5, caractérisé par le fait qu'après sa mise en service et après la lecture des adresses mémorisées dans l'insert, l'unité à processeur (2) exécute un contrôle de vraisemblance.
  7. Dispositif suivant l'une des revendications 2 à 6, caractérisé par le fait que lors de l'identification de défauts prédéterminés d'un module, l'unité à processeur (2) efface ou bloque respectivement l'adresse mémorisée dans la mémoire EEPROM de ce module.
  8. Dispositif suivant la revendication 1 à 6, caractérisé par le fait qu'au moins l'un des modules contient un dispositif de contrôle qui, dans le cas de l'identification de défauts prédéterminés, efface ou bloque l'adresse mémorisée dans la mémoire EEPROM de ce module.
EP90104914A 1989-03-21 1990-03-15 Dispositif pour emmagasiner l'adresse d'une unité processeur de surveillance en service Expired - Lifetime EP0388798B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT90104914T ATE102413T1 (de) 1989-03-21 1990-03-15 Anordnung zum speichern der adresse einer inbetrieb-¨berwachung-prozessoreinheit.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3909266A DE3909266A1 (de) 1989-03-21 1989-03-21 Anordnung zum speichern der adresse einer in-betrieb-ueberwachung-prozessoreinheit
DE3909266 1989-03-21

Publications (2)

Publication Number Publication Date
EP0388798A1 EP0388798A1 (fr) 1990-09-26
EP0388798B1 true EP0388798B1 (fr) 1994-03-02

Family

ID=6376867

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90104914A Expired - Lifetime EP0388798B1 (fr) 1989-03-21 1990-03-15 Dispositif pour emmagasiner l'adresse d'une unité processeur de surveillance en service

Country Status (5)

Country Link
US (1) US5495575A (fr)
EP (1) EP0388798B1 (fr)
JP (1) JP2825598B2 (fr)
AT (1) ATE102413T1 (fr)
DE (2) DE3909266A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5845095A (en) * 1995-07-21 1998-12-01 Motorola Inc. Method and apparatus for storing and restoring controller configuration information in a data communication system
DE19810646C2 (de) * 1998-03-12 2000-12-21 Stefan Jaegers Vorrichtung zum Einrichten und Erkennen elektronischer Adressen von Netzwerkanschlüssen
US6240478B1 (en) 1998-10-30 2001-05-29 Eaton Corporation Apparatus and method for addressing electronic modules
US6738920B1 (en) 2000-11-28 2004-05-18 Eaton Corporation Method for deriving addresses for a plurality of system components in response to measurement of times of receipt of two signals by each component
JP4185142B2 (ja) * 2007-02-06 2008-11-26 ファナック株式会社 数値制御装置
DE102016220197A1 (de) * 2016-10-17 2018-04-19 Robert Bosch Gmbh Verfahren zum Verarbeiten von Daten für ein automatisiertes Fahrzeug

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1128896B (it) * 1980-07-03 1986-06-04 Olivetti & Co Spa Apparecchiatura di elaborazione dati con memoria permanente programmabile
NL8303944A (nl) * 1983-11-17 1985-06-17 Philips Nv Werkwijze voor het besturen van een bewakingsinrichting in een digitaal transmissiesysteem.
US4788657A (en) * 1983-12-27 1988-11-29 American Telephone And Telegraph Company Communication system having reconfigurable data terminals
DE3347357A1 (de) * 1983-12-28 1985-07-11 Siemens AG, 1000 Berlin und 8000 München Einrichtung zum vergeben von adressen an steckbare baugruppen
US4941201A (en) * 1985-01-13 1990-07-10 Abbott Laboratories Electronic data storage and retrieval apparatus and method
US4752871A (en) * 1985-09-30 1988-06-21 Motorola, Inc. Single-chip microcomputer having a program register for controlling two EEPROM arrays
US4750136A (en) * 1986-01-10 1988-06-07 American Telephone And Telegraph, At&T Information Systems Inc. Communication system having automatic circuit board initialization capability
US4700340A (en) * 1986-05-20 1987-10-13 American Telephone And Telegraph Company, At&T Bell Laboratories Method and apparatus for providing variable reliability in a telecommunication switching system
DE3622988A1 (de) * 1986-07-09 1988-01-28 Ant Nachrichtentech Fernwirksystem
US4811287A (en) * 1986-10-27 1989-03-07 United Technologies Corporation EEPROM mounting device
US4755985A (en) * 1986-12-09 1988-07-05 Racal Data Communications Inc. Method and apparatus for facilitating moves and changes in a communication system
US5038320A (en) * 1987-03-13 1991-08-06 International Business Machines Corp. Computer system with automatic initialization of pluggable option cards
US5084816A (en) * 1987-11-25 1992-01-28 Bell Communications Research, Inc. Real time fault tolerant transaction processing system
DE3806948A1 (de) * 1988-03-03 1989-09-14 Siemens Ag Verfahren zum adressieren von prozessoreinheiten
US5040111A (en) * 1988-04-11 1991-08-13 At&T Bell Laboratories Personal computer based non-interactive monitoring of communication links
US5089954A (en) * 1988-08-08 1992-02-18 Bell Communications Research, Inc. Method for handling conversational transactions in a distributed processing environment
US5088089A (en) * 1989-12-15 1992-02-11 Alcatel Na Network Systems Corp. Apparatus for programmably accessing and assigning time slots in a time division multiplexed communication system

Also Published As

Publication number Publication date
JP2825598B2 (ja) 1998-11-18
DE59004715D1 (de) 1994-04-07
JPH0327642A (ja) 1991-02-06
DE3909266A1 (de) 1990-09-27
ATE102413T1 (de) 1994-03-15
EP0388798A1 (fr) 1990-09-26
US5495575A (en) 1996-02-27

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