EP0346898A2 - Power supply switching circuit - Google Patents
Power supply switching circuit Download PDFInfo
- Publication number
- EP0346898A2 EP0346898A2 EP89110882A EP89110882A EP0346898A2 EP 0346898 A2 EP0346898 A2 EP 0346898A2 EP 89110882 A EP89110882 A EP 89110882A EP 89110882 A EP89110882 A EP 89110882A EP 0346898 A2 EP0346898 A2 EP 0346898A2
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- European Patent Office
- Prior art keywords
- mos transistor
- potential
- level
- power supply
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Definitions
- This invention relates to a CMOS, and more particularly, to a power supply switching circuit.
- This conventional circuit includes a first p-channel MOS transistor P1 and a second p-channel MOS transistor P2 which are connected in series, and a high potential V PP is supplied from IN2 to the source of the first p-channel MOS transistor P1, and a standard potential (V DD ) is supplied from a terminal 10 to the drain of the second p-channel MOS transistor P2.
- An input terminal IN1 to which control signals are input, is connected to the input of a level shifter 8, through which the gate of the first p-channel MOS transistor P1 is connected.
- the input terminal IN1 is also connected to the gate of an inverter circuit 7 which comprises a p-channel MOS transistor P4 and an n-channel MOS transistor N5.
- An output terminal OUT1 is connected to a connection point of the drain of the first MOS transistor and the source of the second MOS transistor, and grounded at GND0 via the p-channel MOS transistor P4 and the n-channel MOS transistor N5.
- the gate of the second MOS transistor P2 is connected to a connection point of the p-channel MOS transistor P4 and the n-channel MOS transistor N5.
- An input signal is applied to the input terminal IN2 at the potential level V PP which is higher than the standard potential (V DD ).
- the level shifter 8 is inserted for completely turning off the first p-channel MOS transistor P1 when the level “V DD " is input to the input terminal IN1, and is a circuit which outputs the level IN2 when the level “V DD " is input to the input terminal IN1, and outputs the level “GND” when the level “GND” is input.
- the level “GND” is input to the input terminal IN1
- the level “GND” which is an output of the level shifter 8
- the first p-channel MOS transistor P1 is turned on. Accordingly, a connection point 6 (node) of the drain of the first MOS transistor P1 and the source of the second MOS transistor P2 becomes at the level "V PP ".
- the level "GND” is applied to the gate of the n-channel MOS transistor N5 of the inverter 7 connected to the input terminal IN1, the n-channel MOS transistor N5 is turned off.
- the level “GND” is also applied to the gate of the p-channel MOS transistor P4 connected to the input terminal IN1, and since the node 6 is at the level “V PP ", the p-channel MOS transistor P4 is turned on.
- the gate of the second MOS transistor P2 becomes at the level "V PP " via the turned-on p-channel MOS transistor P4, and the second MOS transistor P2 is completely turned off. Consequently, the level "V PP " is output from the output terminal OUT1.
- the level “V DD " When the level “V DD " is input to the input terminal IN1, the level “V PP ", which is an output of the level shifter 8, is applied to the gate of the first p-channel MOS transistor P1, and the first p-channel MOS transistor P1 is turned off. Furthermore, since the level “V DD " is applied to the gate of the n-channel MOS transistor N5 of the inverter 7 connected to the input terminal IN1, the n-channel MOS transistor N5 is turned on. The gate of the second p-channel MOS transistor P2 then becomes at the level "GND", and the second p-channel MOS transistor P2 is turned on. Hence, the node 6 becomes at the level "V DD ".
- the gate and the source of the p-channel MOS transistor P4 are both at the level “V DD ", the p-channel MOS transistor P4 is turned off. Hence, the level “V DD " of the node 6 is output as it is from the output terminal OUT1.
- the level “V PP” is output when the level “GND” is input to the input terminal IN1
- the level “V DD” is output from the output terminal OUT1 when the level "V DD " is input to the input terminal IN1.
- the present invention has been made on the basis of the above-described background. It is an object of the present invention to provide a power supply switching circuit in which an input terminal can be used in common for other input signals, in a semiconductor device, such as a CMOS ⁇ LSI and the like, having inputs of many potential levels.
- the inventor After performing research and development for solving the above-described problems, the inventor has found that, by further providing a third MOS transistor between a first MOS transistor and an output terminal OUT, the third MOS transistor is turned off even when a potential applied from an input terminal is lower than the level "V DD ", a reverse bias is applied to a parasitic diode to suppress the above-described conduction and securely maintain an output level from the output terminal OUT without decreasing the level, and it is possible to use the input terminal in common for other input signals, and thus completed the present invention.
- a power supply switching circuit of the present invention is a power supply switching circuit comprising first and second MOS transistors which are connected in series, and for output of a power supply potential by switching using a standard potential and at least one kind of potential which is different from the standard potential, characterized in that it comprises a third MOS transistor between the first and second MOS transistors, and the source of the third MOS transistor is connected to the drain of the first MOS transistor, the drain of the third MOS transistor is connected to the source of the second MOS transistor, the back gate of the third MOS transistor is connected to an output, a connection point of the drain of the third MOS transistor and the source of the second MOS transistor is made an output, a high potential or a low potential is supplied to the source of the first MOS transistor, and a standard potential is supplied to the drain of the second MOS transistor.
- the first, second and third MOS transistors may be p-channel transistors, and a high potential may be supplied to the source of the first MOS transistor.
- a gate signal of the second MOS transistor may be made an output signal of an inverter comprising MOS transistors in which an output is from a source.
- a gate signal of the first MOS transistor may be supplied from a level shifter which outputs a high potential or a ground potential.
- the first, second and third MOS transistors may be n-channel transistors, and a low potential may be supplied to the source of the first MOS transistor.
- the third MOS transistor is newly provided between the first and second MOS transistors. That is, the third MOS transistor is provided between the first MOS transistor and the output terminal OUT. Hence, the third MOS transistor is turned off even when a potential applied from the input terminal is lower than the level "V DD " of the standard potential, and a reverse bias is applied to a parasitic diode which exists between a source diffusion region and an n-well of the third MOS transistor to suppress conduction between the standard potential and the input terminal.
- FIG. 1 is a circuit configuration diagram of an embodiment according to the present invention
- FIG. 2 is a circuit configuration diagram for explaining the function of the circuit of the embodiment.
- a power supply switching circuit of the embodiment comprises a first MOS transistor P1 and a second MOS transistor P2 which are connected in series, and a third MOS transistor P3 between the first and second MOS transistors P1 and P2.
- the drain of the first MOS transistor P1 is connected to the source of the third MOS transistor P3, the source of the second MOS transistor P2 is connected to the drain of the third MOS transistor P3, and the back gate of the third MOS transistor is connected to an output OUT1.
- a connection point 6 of the drain of the third MOS transistor P3 and the source of the second MOS transistor P2 is made the output OUT1, a high potential V PP is supplied to the source of the first MOS transistor P1, and a standard potential V DD is supplied to the drain of the second MOS transistor P2.
- the output OUT1 is connected to IN2 via the transistors P3 and P1, to a standard potential V DD 10 via the transistor P2, and also to GND0 via transistors P4 and N5 which constitute an inverter circuit 7.
- an input terminal IN1 for control signals is connected to the input of a level shifter 8, to the gate of the third p-channel MOS transistor P3, and also to the gate of the inverter circuit comprising the transistors P4 and N5.
- the gate of the first p-channel MOS transistor P1 is connected to the output of the level shifter 8
- the gate of the second p-channel MOS transistor P2 is connected to a connection point of the p-channel MOS transistor P4 and the n-channel MOS transistor N5.
- the level shifter 8 is inserted for completely turning off the first p-channel MOS transistor P1 when the level “V DD " is input to the input terminal IN1, and is a circuit which outputs the level IN2 when the level “V DD " is input to the input terminal IN1, and outputs the level “GND” when the level “GND” is input.
- the gate of the first p-channel MOS transistor P1 becomes at the level "V PP ", and the transistor P1 is turned off. Since the gate of the n-channel MOS transistor N5 becomes at the level "V DD ", the transistor N5 is turned on, and since the gate of the second p-channel MOS transistor P2 becomes at the level "GND", the second p-channel MOS transistor P2 is turned on. Hence, the node 6 becomes at the level "V DD ". At this time, since both the gate of the p-channel MOS transistor P4 and the node 6 become at the level "V DD ", the transistor P3 is turned off.
- the present invention can be applied to an aspect in which a low potential, such as a negative power supply or the like, is used instead of a high-potential power supply.
- a low potential such as a negative power supply or the like
- p-channel and n-channel transistors may be replaced by n-channel and p-channel transistors, respectively, as shown in FIG. 3.
- the level shifter 8 may be of any type provided that it can completely turn off the first MOS transistor P1.
- the third MOS transistor P3 may also have an arbitrary structure, provided that it effectively interrupts a current path between the level "V DD " 10 of the standard potential and the high-potential or low-potential input terminal IN2.
- the power supply switching circuit of the present invention has the following effects.
- a third MOS transistor is provided between a first MOS transistor and an output terminal OUT.
- the third MOS transistor is turned off even when a potential applied from an input terminal IN2 is lower than the level "V DD " of a standard potential.
- a reverse bias is applied to a parasitic diode which exists between a source diffusion region and an n-well of the third MOS transistor to suppress a conduction between the standard potential and the input terminal. Accordingly, it makes it possible to securely output the level "V DD " at the OUT1, even when the potential applied from the input terminal is lower than the level "V DD " of the standard potential.
- an exclusive terminal for applying a high potential is necessary in a conventional circuit
- an input terminal for the high-potential level "V PP " and other input terminals for different potentials can be used in common in a power supply switching circuit according to claims 2, 3 and 4.
- the present invention is effective in reducing the number of pins.
- the present invention can also be applied to an aspect in which a low potential, such as a negative potential and the like, is used, and an input terminal for a low potential level and other input terminals for different potentials can be used in common.
- a low potential such as a negative potential and the like
- an input terminal for a low potential level and other input terminals for different potentials can be used in common.
- the present invention is similarly effective in reducing the number of pins.
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Abstract
Description
- This invention relates to a CMOS, and more particularly, to a power supply switching circuit.
- In an LSI using an EPROM and the like, it is necessary to apply a potential which is higher than a power supply potential (VDD) for write while in the write mode, and to use the standard potential and a potential which is higher than the standard potential as power supplies and to switch them.
- Heretofore, as a circuit for switching power supplies as described above, there is, for example, a power supply switching circuit shown in FIG. 4.
- This conventional circuit includes a first p-channel MOS transistor P1 and a second p-channel MOS transistor P2 which are connected in series, and a high potential VPP is supplied from IN2 to the source of the first p-channel MOS transistor P1, and a standard potential (VDD) is supplied from a
terminal 10 to the drain of the second p-channel MOS transistor P2. - An input terminal IN1, to which control signals are input, is connected to the input of a
level shifter 8, through which the gate of the first p-channel MOS transistor P1 is connected. The input terminal IN1 is also connected to the gate of aninverter circuit 7 which comprises a p-channel MOS transistor P4 and an n-channel MOS transistor N5. - An output terminal OUT1 is connected to a connection point of the drain of the first MOS transistor and the source of the second MOS transistor, and grounded at GND0 via the p-channel MOS transistor P4 and the n-channel MOS transistor N5. The gate of the second MOS transistor P2 is connected to a connection point of the p-channel MOS transistor P4 and the n-channel MOS transistor N5.
- Now, the operation of this power supply switching circuit of the prior art will be explained.
- An input signal is applied to the input terminal IN2 at the potential level VPP which is higher than the standard potential (VDD).
- The
level shifter 8 is inserted for completely turning off the first p-channel MOS transistor P1 when the level "VDD" is input to the input terminal IN1, and is a circuit which outputs the level IN2 when the level "VDD" is input to the input terminal IN1, and outputs the level "GND" when the level "GND" is input. - First, when the level "GND" is input to the input terminal IN1, the level "GND", which is an output of the
level shifter 8, is applied to the gate of the first p-channel MOS transistor P1, and the first p-channel MOS transistor P1 is turned on. Accordingly, a connection point 6 (node) of the drain of the first MOS transistor P1 and the source of the second MOS transistor P2 becomes at the level "VPP". - Furthermore, since the level "GND" is applied to the gate of the n-channel MOS transistor N5 of the
inverter 7 connected to the input terminal IN1, the n-channel MOS transistor N5 is turned off. The level "GND" is also applied to the gate of the p-channel MOS transistor P4 connected to the input terminal IN1, and since thenode 6 is at the level "VPP", the p-channel MOS transistor P4 is turned on. The gate of the second MOS transistor P2 becomes at the level "VPP" via the turned-on p-channel MOS transistor P4, and the second MOS transistor P2 is completely turned off. Consequently, the level "VPP" is output from the output terminal OUT1. - When the level "VDD" is input to the input terminal IN1, the level "VPP", which is an output of the
level shifter 8, is applied to the gate of the first p-channel MOS transistor P1, and the first p-channel MOS transistor P1 is turned off. Furthermore, since the level "VDD" is applied to the gate of the n-channel MOS transistor N5 of theinverter 7 connected to the input terminal IN1, the n-channel MOS transistor N5 is turned on. The gate of the second p-channel MOS transistor P2 then becomes at the level "GND", and the second p-channel MOS transistor P2 is turned on. Hence, thenode 6 becomes at the level "VDD". Since the gate and the source of the p-channel MOS transistor P4 are both at the level "VDD", the p-channel MOS transistor P4 is turned off. Hence, the level "VDD" of thenode 6 is output as it is from the output terminal OUT1. - As described above, in the power supply switching circuit of the prior art shown in FIG. 4, the level "VPP" is output when the level "GND" is input to the input terminal IN1, and the level "VDD" is output from the output terminal OUT1 when the level "VDD" is input to the input terminal IN1.
- When a potential applied to the high-potential input terminal IN2 is at a level equivalent to or higher than the level "VDD", no forward-direction bias is applied to a parasitic diode D1 which exists between a source diffusion region (p-type) and an n-well of the first p-channel MOS transistor P1 as shown in FIG. 5, and so no current flows.
- However, when a potential applied from the input terminal IN2 is lower than the level "VDD", although the first p-channel MOS transistor P1 is turned off, a forward-direction bias is applied to the parasitic diode D1 to conduct it. Hence, a current path is formed between the VDD and the IN2 via the first and second p-channel MOS transistors P1 and P2, and the output level from the output terminal OUT1 decreases.
- Since there exists the above-described inconvenience when a potential applied from the input terminal IN2 is lower than the level "VDD", a high-potential input signal and other input signals can not use the terminal IN2 in common, and it is necessary to provide exclusive terminals for respective inputs.
-
- The present invention has been made on the basis of the above-described background. It is an object of the present invention to provide a power supply switching circuit in which an input terminal can be used in common for other input signals, in a semiconductor device, such as a CMOS·LSI and the like, having inputs of many potential levels.
- After performing research and development for solving the above-described problems, the inventor has found that, by further providing a third MOS transistor between a first MOS transistor and an output terminal OUT, the third MOS transistor is turned off even when a potential applied from an input terminal is lower than the level "VDD", a reverse bias is applied to a parasitic diode to suppress the above-described conduction and securely maintain an output level from the output terminal OUT without decreasing the level, and it is possible to use the input terminal in common for other input signals, and thus completed the present invention.
- That is, a power supply switching circuit of the present invention is a power supply switching circuit comprising first and second MOS transistors which are connected in series, and for output of a power supply potential by switching using a standard potential and at least one kind of potential which is different from the standard potential, characterized in that
it comprises a third MOS transistor between the first and second MOS transistors, and the source of the third MOS transistor is connected to the drain of the first MOS transistor, the drain of the third MOS transistor is connected to the source of the second MOS transistor, the back gate of the third MOS transistor is connected to an output,
a connection point of the drain of the third MOS transistor and the source of the second MOS transistor is made an output,
a high potential or a low potential is supplied to the source of the first MOS transistor, and a standard potential is supplied to the drain of the second MOS transistor. - In a preferred aspect of the present invention, the first, second and third MOS transistors may be p-channel transistors, and a high potential may be supplied to the source of the first MOS transistor.
- In the aspect of providing p-channel transistors and supplying a high potential to the source of the first MOS transistor, a gate signal of the second MOS transistor may be made an output signal of an inverter comprising MOS transistors in which an output is from a source.
- Furthermore, in the aspect of providing p-channel transistors and supplying a high potential to the source of the first MOS transistor, a gate signal of the first MOS transistor may be supplied from a level shifter which outputs a high potential or a ground potential.
- In another aspect of the present invention, the first, second and third MOS transistors may be n-channel transistors, and a low potential may be supplied to the source of the first MOS transistor.
- The function of the power supply switching circuit according to the present invention will be schematically explained.
- In the power supply switching circuit of the present invention, the third MOS transistor is newly provided between the first and second MOS transistors. That is, the third MOS transistor is provided between the first MOS transistor and the output terminal OUT. Hence, the third MOS transistor is turned off even when a potential applied from the input terminal is lower than the level "VDD" of the standard potential, and a reverse bias is applied to a parasitic diode which exists between a source diffusion region and an n-well of the third MOS transistor to suppress conduction between the standard potential and the input terminal.
-
- FIG. 1 is a circuit configuration diagram showing an embodiment of a power supply switching circuit according to the present invention;
- FIG. 2 is an explanatory diagram of the circuit shown in FIG. 1;
- FIG. 3 is a circuit configuration diagram showing a modified example of a power supply switching circuit according to the present invention;
- FIG. 4 is a circuit configuration diagram showing an example of a power supply switching circuit of the prior art; and
- FIG. 5 is an explanatory diagram for explaining disadvantages of the circuit example shown in FIG. 4.
- The present invention will be more concretely explained with reference to the drawings.
- FIG. 1 is a circuit configuration diagram of an embodiment according to the present invention, and FIG. 2 is a circuit configuration diagram for explaining the function of the circuit of the embodiment.
- A power supply switching circuit of the embodiment comprises a first MOS transistor P1 and a second MOS transistor P2 which are connected in series, and a third MOS transistor P3 between the first and second MOS transistors P1 and P2. The drain of the first MOS transistor P1 is connected to the source of the third MOS transistor P3, the source of the second MOS transistor P2 is connected to the drain of the third MOS transistor P3, and the back gate of the third MOS transistor is connected to an output OUT1. A
connection point 6 of the drain of the third MOS transistor P3 and the source of the second MOS transistor P2 is made the output OUT1, a high potential VPP is supplied to the source of the first MOS transistor P1, and a standard potential VDD is supplied to the drain of the second MOS transistor P2. - Accordingly, the output OUT1 is connected to IN2 via the transistors P3 and P1, to a
standard potential V DD 10 via the transistor P2, and also to GND0 via transistors P4 and N5 which constitute aninverter circuit 7. - On the other hand, an input terminal IN1 for control signals is connected to the input of a
level shifter 8, to the gate of the third p-channel MOS transistor P3, and also to the gate of the inverter circuit comprising the transistors P4 and N5. - Furthermore, the gate of the first p-channel MOS transistor P1 is connected to the output of the
level shifter 8, and the gate of the second p-channel MOS transistor P2 is connected to a connection point of the p-channel MOS transistor P4 and the n-channel MOS transistor N5. - The
level shifter 8 is inserted for completely turning off the first p-channel MOS transistor P1 when the level "VDD" is input to the input terminal IN1, and is a circuit which outputs the level IN2 when the level "VDD" is input to the input terminal IN1, and outputs the level "GND" when the level "GND" is input. - Next, the operation of the circuit of the embodiment according to the present invention will be explained.
- When a potential "VPP" which is no lower than the level "VDD" is applied to the IN2, the operation is as follows.
- First, when a potential of the level "GND" is applied to the IN1, the gates of the first p-channel MOS transistor and the third p-channel MOS transistor P3 both becomes at the level "GND", the both transistors are turned on, and the
node 6 becomes at the "VPP". At this time, since a potential of the level "GND" is applied to the gate of the n-channel MOS transistor N5, the transistor N5 is turned off. Since a potential of the level "GND" is also applied to the gate of the p-channel MOS transistor P4, and thenode 6 is at the level "VPP", the transistor P4 is turned on. The gate of the second p-channel MOS transistor P2 becomes at the level "VPP", and the transistor P2 is completely turned off. Hence, the level "VPP" is output at the output terminal OUT1. - Next, when the level "VDD" is applied to the IN1, the gate of the first p-channel MOS transistor P1 becomes at the level "VPP", and the transistor P1 is turned off. Since the gate of the n-channel MOS transistor N5 becomes at the level "VDD", the transistor N5 is turned on, and since the gate of the second p-channel MOS transistor P2 becomes at the level "GND", the second p-channel MOS transistor P2 is turned on. Hence, the
node 6 becomes at the level "VDD". At this time, since both the gate of the p-channel MOS transistor P4 and thenode 6 become at the level "VDD", the transistor P3 is turned off. - Furthermore, since both the gate of the third p-channel MOS transistor P3 and the
node 6 become at the level "VDD", the third p-channel MOS transistor P3 is turned off. Hence, a potential of the level "VDD" is output at the OUT1. - A case in which a potential which is lower than the level "VDD" is applied to the IN1 will be hereinafter explained with reference to FIG. 2.
- When a potential of the level "VDD" is applied to the IN1, the gate of the n-channel MOS transistor N5 becomes at the level "VDD", the transistor N5 is turned on, and the gate of the second p-channel MOS transistor P2 becomes at the level "GND". Hence, the second p-channel MOS transistor P2 is turned on. Consequently, the
node 6 becomes at the level "VDD", and since the gate of the transistor P4 is at the level "VDD", the transistor P4 is turned off. In this aspect, the gate of the third p-channel MOS transistor P3 is at the level "VDD", the transistor P3 is turned off. Furthermore, since a potential which is lower than the level "VDD" is applied to the IN2, and thenode 6 is at the level "VDD", a parasitic diode D2 which exists between a source diffusion region (p-type) and n-well of the transistor P3 is reverse-biased, and the transistor P3 is not conducting. Hence, irrespective of the condition of the MOS transistor P1, it is possible to interrupt by the transistor P3 a current path between the level "VDD" 10 of the standard potential and the high-potential input terminal IN2 via the transistors P1, P3 and P2. Accordingly, it becomes possible to suppress a decrease in the output level at the output terminal OUT1 which is a disadvantage of the conventional power supply switching circuit, and to securely output the level "VDD" at the OUT1. - The present invention is not limited to the above-described aspects, but various modified aspects are possible within the scope of the invention.
- For example, the present invention can be applied to an aspect in which a low potential, such as a negative power supply or the like, is used instead of a high-potential power supply. As an example thereof, p-channel and n-channel transistors may be replaced by n-channel and p-channel transistors, respectively, as shown in FIG. 3.
- Furthermore, the
level shifter 8 may be of any type provided that it can completely turn off the first MOS transistor P1. The third MOS transistor P3 may also have an arbitrary structure, provided that it effectively interrupts a current path between the level "VDD" 10 of the standard potential and the high-potential or low-potential input terminal IN2. - The power supply switching circuit of the present invention has the following effects.
- In a power supply switching circuit according to claim 1, a third MOS transistor is provided between a first MOS transistor and an output terminal OUT. Hence, the third MOS transistor is turned off even when a potential applied from an input terminal IN2 is lower than the level "VDD" of a standard potential. Furthermore, a reverse bias is applied to a parasitic diode which exists between a source diffusion region and an n-well of the third MOS transistor to suppress a conduction between the standard potential and the input terminal. Accordingly, it makes it possible to securely output the level "VDD" at the OUT1, even when the potential applied from the input terminal is lower than the level "VDD" of the standard potential.
- Although an exclusive terminal for applying a high potential is necessary in a conventional circuit, an input terminal for the high-potential level "VPP" and other input terminals for different potentials can be used in common in a power supply switching circuit according to
claims 2, 3 and 4. Hence, the present invention is effective in reducing the number of pins. - In a power supply switching circuit according to claim 5, the present invention can also be applied to an aspect in which a low potential, such as a negative potential and the like, is used, and an input terminal for a low potential level and other input terminals for different potentials can be used in common. Hence, the present invention is similarly effective in reducing the number of pins.
Claims (5)
said power supply switching circuit comprises a third MOS transistor between said first and second MOS transistors, and the source of the third MOS transistor is connected to the drain of the first MOS transistor, the drain of the third MOS transistor is connected to the source of the second MOS transistor, the back gate of the third MOS transistor is connected to an output,
a connection point of the drain of the third MOS transistor and the source of the second MOS transistor is made an output,
a high potential or a low potential is supplied to the source of the first MOS transistor, and a standard potential is supplied to the drain of the second MOS transistor.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP149156/88 | 1988-06-16 | ||
JP63149156A JPH01317022A (en) | 1988-06-16 | 1988-06-16 | Power supply switching circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0346898A2 true EP0346898A2 (en) | 1989-12-20 |
EP0346898A3 EP0346898A3 (en) | 1991-02-27 |
EP0346898B1 EP0346898B1 (en) | 1994-08-31 |
Family
ID=15469015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP89110882A Expired - Lifetime EP0346898B1 (en) | 1988-06-16 | 1989-06-15 | Power supply switching circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US4988894A (en) |
EP (1) | EP0346898B1 (en) |
JP (1) | JPH01317022A (en) |
KR (1) | KR920004340B1 (en) |
DE (1) | DE68917801T2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0644656A2 (en) * | 1993-09-16 | 1995-03-22 | Nec Corporation | Transistor circuits with a terminal for receiving high voltages and signals |
EP0729232A1 (en) * | 1995-02-22 | 1996-08-28 | Texas Instruments Incorporated | A high voltage analog switch |
EP0747957A2 (en) * | 1995-06-07 | 1996-12-11 | STMicroelectronics, Inc. | Power supply isolation and switching circuit |
EP0889591A1 (en) * | 1997-06-30 | 1999-01-07 | STMicroelectronics S.r.l. | Method and corresponding circuit to prevent a parasitic transistor turn on in an output stage of an electronic circuit |
EP0663727B1 (en) * | 1993-12-24 | 1999-04-21 | Kawasaki Steel Corporation | Output buffer circuit, input buffer circuit and bi-directional buffer circuit for plural voltage systems |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0793019B2 (en) * | 1988-09-02 | 1995-10-09 | 株式会社東芝 | Semiconductor integrated circuit |
JPH03148827A (en) * | 1989-11-06 | 1991-06-25 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
JPH07111826B2 (en) * | 1990-09-12 | 1995-11-29 | 株式会社東芝 | Semiconductor memory device |
KR0124046B1 (en) * | 1993-11-18 | 1997-11-25 | 김광호 | Vpp detector of semiconductor memory device |
US5493244A (en) * | 1994-01-13 | 1996-02-20 | Atmel Corporation | Breakdown protection circuit using high voltage detection |
US5594381A (en) * | 1994-04-29 | 1997-01-14 | Maxim Integrated Products | Reverse current prevention method and apparatus and reverse current guarded low dropout circuits |
GB2327544B (en) * | 1997-07-16 | 2001-02-07 | Ericsson Telefon Ab L M | Electronic analogue switch |
JP3746273B2 (en) * | 2003-02-12 | 2006-02-15 | 株式会社東芝 | Signal level conversion circuit |
JP3984222B2 (en) * | 2003-12-15 | 2007-10-03 | 株式会社東芝 | Signal level conversion circuit |
JP2006301840A (en) * | 2005-04-19 | 2006-11-02 | Toshiba Corp | Signal level conversion bus switch |
JP4199765B2 (en) * | 2005-12-02 | 2008-12-17 | マイクロン テクノロジー,インコーポレイテッド | High voltage switching circuit |
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US4477742A (en) * | 1982-06-21 | 1984-10-16 | Eaton Corporation | Three terminal bidirectional drain to drain FET circuit |
FR2607338A1 (en) * | 1986-11-21 | 1988-05-27 | Eurotechnique Sa | VOLTAGE SWITCHING CIRCUIT IN MOS TECHNOLOGY |
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US3936676A (en) * | 1974-05-16 | 1976-02-03 | Hitachi, Ltd. | Multi-level voltage supply circuit for liquid crystal display device |
US4441172A (en) * | 1981-12-28 | 1984-04-03 | National Semiconductor Corporation | Semiconductor memory core program control circuit |
JPS6052112A (en) * | 1983-08-31 | 1985-03-25 | Toshiba Corp | Logical circuit |
JPS60124124A (en) * | 1983-12-08 | 1985-07-03 | Nec Corp | Input circuit |
JPH01123522A (en) * | 1987-11-07 | 1989-05-16 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1988
- 1988-06-16 JP JP63149156A patent/JPH01317022A/en active Granted
-
1989
- 1989-06-14 US US07/365,739 patent/US4988894A/en not_active Expired - Lifetime
- 1989-06-15 EP EP89110882A patent/EP0346898B1/en not_active Expired - Lifetime
- 1989-06-15 DE DE68917801T patent/DE68917801T2/en not_active Expired - Fee Related
- 1989-06-16 KR KR1019890008314A patent/KR920004340B1/en not_active IP Right Cessation
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US4477742A (en) * | 1982-06-21 | 1984-10-16 | Eaton Corporation | Three terminal bidirectional drain to drain FET circuit |
FR2607338A1 (en) * | 1986-11-21 | 1988-05-27 | Eurotechnique Sa | VOLTAGE SWITCHING CIRCUIT IN MOS TECHNOLOGY |
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PROCEEDINGS OF THE IEEE 1987 CUSTOM INTEGRATED CIRCUITS CONFERENCE, Portland, Oregon, 4th - 7th May 1987, pages 439-442; H.-Y. TSOI et al.: "A multichannel 300V level translator chip" * |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0644656A2 (en) * | 1993-09-16 | 1995-03-22 | Nec Corporation | Transistor circuits with a terminal for receiving high voltages and signals |
EP0644656A3 (en) * | 1993-09-16 | 1995-11-22 | Nec Corp | Transistor circuits with a terminal for receiving high voltages and signals. |
US5508654A (en) * | 1993-09-16 | 1996-04-16 | Nec Corporation | Transistor circuits with a terminal for receiving high voltages and signals |
EP0663727B1 (en) * | 1993-12-24 | 1999-04-21 | Kawasaki Steel Corporation | Output buffer circuit, input buffer circuit and bi-directional buffer circuit for plural voltage systems |
EP0729232A1 (en) * | 1995-02-22 | 1996-08-28 | Texas Instruments Incorporated | A high voltage analog switch |
EP0747957A2 (en) * | 1995-06-07 | 1996-12-11 | STMicroelectronics, Inc. | Power supply isolation and switching circuit |
EP0747957A3 (en) * | 1995-06-07 | 1998-09-09 | STMicroelectronics, Inc. | Power supply isolation and switching circuit |
EP0889591A1 (en) * | 1997-06-30 | 1999-01-07 | STMicroelectronics S.r.l. | Method and corresponding circuit to prevent a parasitic transistor turn on in an output stage of an electronic circuit |
US6194948B1 (en) | 1997-06-30 | 2001-02-27 | Stmicroelectronics S.R.L. | Method and an auxiliary circuit for preventing the triggering of a parasitic transistor in an output stage of an electronic circuit |
Also Published As
Publication number | Publication date |
---|---|
DE68917801T2 (en) | 1995-02-16 |
EP0346898A3 (en) | 1991-02-27 |
EP0346898B1 (en) | 1994-08-31 |
DE68917801D1 (en) | 1994-10-06 |
KR910002127A (en) | 1991-01-31 |
KR920004340B1 (en) | 1992-06-01 |
US4988894A (en) | 1991-01-29 |
JPH01317022A (en) | 1989-12-21 |
JPH056373B2 (en) | 1993-01-26 |
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