EP0324063A2 - Automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system - Google Patents
Automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system Download PDFInfo
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- EP0324063A2 EP0324063A2 EP88116134A EP88116134A EP0324063A2 EP 0324063 A2 EP0324063 A2 EP 0324063A2 EP 88116134 A EP88116134 A EP 88116134A EP 88116134 A EP88116134 A EP 88116134A EP 0324063 A2 EP0324063 A2 EP 0324063A2
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- zero
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R17/00—Measuring arrangements involving comparison with a reference value, e.g. bridge
- G01R17/02—Arrangements in which the value to be measured is automatically compared with a reference value
- G01R17/06—Automatic balancing arrangements
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- the present invention is directed toward an ionizing radiation spectroscopy system having a circuit which provides for automatic pole-zero adjustment of that system.
- incident X-ray, ⁇ -ray or alpha-ray radiation from a radiation source 12 is directed toward an ionizing radiation detector 14.
- the ionized radiation liberates charge in the form of electron-hole pairs in an electric field within detector 14, which preferably is of a solid state variety.
- system 10 includes a preamplifier 16, a high pass filter 18, which includes a capacitor C[1] and a resistor R[1], an amplifier section 20, including an amplifier stage 22 having a feedback resistor and a second stage amplifier/filter 24, and a display 26.
- the output of detector 14 is coupled to an input of preamplifier 16, whereas the output of preamplifier 16 is connected, through high pass filter 18, to a summing input of amplifier 22, the output of which is connected to the input of amplifier/filter 24.
- the output of amplifier/filter 24 is connected to the input of display 26.
- Display 26 comprises a multichannel pluse-height analyzer (MCA) which analyzes and displays the output of amplifier section 20.
- MCA multichannel pluse-height analyzer
- charge is collected to the detector electrodes of detector 14 to produce an output current pulse with a total charge which is proportional to the energy of the radiation absorbed by detector 14.
- Preamplifier 16 is charge sensitive and integrates this current pluse to produce a corresponding voltage pulse e[pa](t).
- Succeeding amplifier 22 and amplifier/filter 24 provide shaping for signal-to-noise enhancement.
- the peak amplitudes of the processed pulses are digitalized by an analog-to-digital converter within display 26 and a resultant pulse-height distribution is displayed by display 26. This pulse-height distribution may also be sotred in memory for later analysis.
- the value of capacitor C[1] and/or resistor R[1] may be charged to alter the time constant of filter 18.
- System 10 of Fig. 1 must add minimum noise to the signal output from detector 14 and must be able to process that signal in the shortest possible time.
- Preamplifier 16 is optimized for minimum noise.
- Amplifier 20 provides additional gain and optimized filtering in order to achieve maximum reduction of the preamplifier and detector noise contributions with minimum processing time.
- Preamplifier 16 represents a low pass filter with a typical time constant of 50 ⁇ s to 1 ms.
- the impulse response of preamplifier 16 is, therefore, a voltage step followed by a decaying exponential, e[pa](t) as shown in Fig. 2.
- the subsequent high pass filter 18 and amplifier 20 act to differentiate the preamplifier pulse and introduce additional poles at relatively short time constants.
- the simpliest differentiating network, a high pass filter comprising capacitor C[1] and R[1], has a zero at the origin of the S plane.
- high pass filter 18 with an exponentially decaying preamplifier signal, such as e[pa](t), produces an undesirable undershoot in the resultant signal E(1)(t), as shown in Fig. 3. Undershoot, as shown in Fig. 3, results in a very long pulse processing times, thus aggrevating pulse-pile up, i.e. , the interference by one pulse on the system amplitude determination of successive pulses.
- uncompensated signularities namely the pole of preamplifier 16 and the zero of high pass filter 18, can have a detrimental effect on the noise performance of the overall spectroscopy chain of system 10.
- Fig. 4 One illustrative network often used for pole-zero cancellation is illustrated in Fig. 4 as comprising resistor R[2] and resistor R[3] coupled to a high pass filter comprising capacitor C[1] and resistor R[1].
- an attenuated replica of the output signal from preamplifier 16 may be added to the differentiated signal from the output of high pass filter 18 to exactly cancel the undershoot illustrated in Fig. 3.
- the resultant output voltage from high pass filter 18, e[1](t) is illustrated in Fig. 5.
- the high pass filter 18 of Fig. 1 with capacitor C[1] and resistor R[1] in series, is electrically equivalent to the high pass filter illustrated in Fig. 4 also comprising capacitor C[1] and resistor R[1].
- the pole-zero adjustment is critical. This adjustment is typically performed by a skilled operator by means of an oscilloscope as evidenced by the above-mentioned Casoli et al. article.
- the pole-zero adjustment is made difficult due to the follow factors: (1) the noise at the output of the amplifier obscures the effects of any adjustment for undershoot; (2) the vertical gain of the oscilloscope must be limited to avoid distortion caused by overload or the input signal must be limited by a resistor-diode clamping network; and (3) the statistical amplitude distribution of the amplifier output pulses masks effects of the pole-zero adjustments. Considerable operator skill is required to make a pole-zero adjustment which results in adequate system performance.
- the circuit comprises a boxcar averager, two light-emitting diodes (LEDs), and associated control circuitry.
- the boxcar averager is used to sample the base line at the output of the amplifier, such as the output of amplifier 20 of Fig. 1, after each pulse which is validly detected by detector 14.
- the LEDs are then used to indicate whether the resultant pulse, e[1](t), possesses an undershoot as shown in Fig.
- An object of the present invention is to provide an automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system.
- an automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system comprising a pole-zero network circuit, coupled to the system and having an electrical characteristic which varies as a function of an input control signal, for permitting pole-zero adjustment of the system, a sampling circuit, coupled to the system, for sampling a segment of the trailing edge of random pulses passing through the system, and a control signal circuit, coupled to the sampling circuit, for generating the input control signal as a function of the sampling to permit cancellation of undershoot in the system by the pole-zero network circuit.
- the sampling circuit comprises a boxcar averager circuit
- the electrical characteristic of the pole-zero network circuit is resistance
- the pole-zero network circuit comprises a Multiplying Digital-To-Analog Converter (MDAC).
- MDAC Multiplying Digital-To-Analog Converter
- the pole-zero network circuit includes an input buffer amplifier coupled to the input of the MDAC and an output buffer coupled to the output of the MDAC.
- the pole-zero network circuit of the subject invention includes a circuit coupled to the input amplifier, having a time constant equal to the time constant of the high pass filter.
- prior art ionization spectroscopy systems have a real pole of a high pass filter in the signal path of the system.
- a pole-zero network circuit coupled to the system, for permitting pole-zero adjustment of the system in response to an input control signal, with the network circuit including a real pole in the signal path of the network circuit set coincident with the real pole of the high pass filter.
- the pole-zero network circuit of the subject invention also preferably comprises an input buffer amplifier, a multiplying digital-to-analog converter (MDAC) and an output buffer amplifier connected in series with one another, wherein the input buffer amplifier includes a circuit to establish the above-mentioned real pole in the signal path of the network circuit.
- MDAC multiplying digital-to-analog converter
- system of the subject invention preferivelyably includes a first mechanism for changing the real pole of the high pass filter and the network circuit includes a second mechanism, responsive to operation of the first mechanism, for correspondingly changing the real pole of the signal path of the network circuit.
- the Laplace Transform of e[pa](t) yields E[pa](s), wherein:
- system 10 at the output of high pass filter 18 has one "zero” represented by “s” in the numerator and two “poles” represented by the terms (s + 1/T[pa]) and (s + 1/t[1]) in the denominator.
- An object of the pole-zero cancellation network illustrated in Fig. 4 is to provide pole-zero cancellation with regard to the poles and zeros present in Equation 3.
- Control circuit 40 has an input line 50 coupled from amplifier/filter 24 which receives a sampled output of amplifier 24 prior to any low pass filtering by amplifier/filter 24 so as to provide an identification pulse for operation within control circuit 40.
- Sampling circuit 42 has an input line 52 from amplifier/filter 24 which receives output signal provided by amplifier/filter 24 but which, preferably has been clamped.
- Control circuit 40 has output lines 54 and 56 coupled to control sampling circuit 42 and control signal circuit 44, respectively, as is described in more detail below.
- the output of sampling circuit 42 is provided to the input of control signal circuit 44.
- the output of control signal circuit 44 is provided over line 58, in the form of an input control signal, to pole-zero network 46.
- Pole-zero network 46 is, in the preferred embodiment of Fig. 6, coupled across high pass filter 18 of system 10.
- pole-zero network 46 includes an electrical characteristic, such as resistance, which varies as a function of the input control signal on line 58, to permit pole-zero adjustment of system 10.
- Sampling circuit 42 operates to sample a segment of the trailing edge of random pulses passing through system 10.
- Sampling circuit 42 in the preferred embodiment of the present invention, comprises a standard boxcar averager circuit of the type illustrated in the Cova et al. article and the Giardinelli patent referred to above.
- the output of sampling circuit 42 accordingly, has an amplitude representative of the sampled preselected intervals of the trailing edge for a plurality of validly detected random pulses from system 10. This output signal amplitude is a weighted average of the trailing edges in these sampled intervals.
- Control circuit 40 operates, as should be apparent to one skilled in the art, to govern the timing of sampling circuit 42 to assure that only a predetermined segment of the trailing edge of each validly detected random pulse is sampled by sampling circuit 42.
- the operation of the present invention is not dependent upon the particular configuration of sampling circuit 42, or the particular manner in which sampling circuit 42 is connected to the amplifier/filter chain of system 10. All that is required is that sampling circuit 42 operate to sample a segment of the trailing edge of valid events detected by system 10.
- Pole-zero network 46 comprises an electronically controlled attenuation element. Although pole-zero network 46 might be implemented in several different ways, two preferred embodiments of pole-zero network 46 are illustrated in Figs. 7 and 8.
- the embodiment of pole-zero network 46 illustrated in Fig.7 comprises a Multiplying Digital To Analog Converter (MDAC) 60, input buffer amplifier 62, output buffer amplifier 64, and resistors R[a], R[z], and R[x].
- MDAC Multiplying Digital To Analog Converter
- Resistor R[a] is coupled between the input of high pass filter 18 and the summing input of buffer amplifier 62.
- Resistor R[x] is provided as a feedback resister for buffer amplifier 62.
- Buffer amplifier 62 is connected as an input buffer amplifier to MDAC 60, the output of which is coupled to the summing input terminal of output buffer amplifier 64.
- the output of buffer amplifier 64 is coupled through resistor R[z], to the summing input of amplifier 22.
- the attenuation value "K" of MDAC 60 namely the resistance of MDAC 60, is controlled by a digital signal from control signal circuit 44 over line 58.
- the input control signal over line 58 to MDAC 60 must operate to adjust the value K of MDAC 60 to meet the criteria of equation 16 or 17. This is achieved by developing the input control signal over line 58 as a function of the sampling performed by sampling circuit 42, which in turn represents the mean average of the undershoot and overshoot of the trailing edges of the random pulses validly detected by system 10.
- high pass filter 18′ includes a switch 70 and a plurality of additional capacitors 72, 74, 76, 78 and 80 which may be selectively coupled by switch 70 to change the effective real pole of high pass filter 18′.
- system 10 in this configuration includes a first stage for changing the real pole of the high pass filter of that system.
- a second mechanism is provided, responsive to operation of the first mechanism, for correspondingly changing the real pole in the signal path of the pole-zero network. As shown in Fig.
- a double pole, switch 90 is provided along with a plurality of capacitors 92, 94, 96, 98, 100 and a plurality of corresponding resistors 102, 104, 106, 108 and 110.
- Switches 70 and 90 are ganged together so that a change in the position of switch 70 results in a corresponding change of both poles of switch 90.
- resistor R1 set at approximately 700 ohms
- capacitor C[1] set at 150 pF the resultant time constant is approximately 0,5 ⁇ s.
- R[x] may be set at 80 kOhm and C[x] set at 240 pF.
- capacitor 72 may have a value of 1 000 pF for a time constant of 1 ⁇ s and corresponding capacitor 92 and resistor 102 may have values of 510 pF and 40 kOhm.
- capacitors 74, 76, 78 and 80 have corresponding values of 2 000 pF, 3 000 pF, 6 000 pF and 10 000 pF; capacitors 94, 96, 98 and 100 have corresponding values of 1 000 pF, 1 500 pF, 3 000 pF, and 5 100 pF; and resistors 102, 104, 108 and 100 have corresponding values of 20 kOhm , 10,87 kOhm , 4,17 kOhm and 1,47 kOhm.
- buffer amplifiers 62 and 64 may comprise model OP-27 operational amplifiers and MDAC 60 may comprise a model AD 7541A.
- Figs. 9, 10 and 11 illustrate three alternative preferred embodiments of the control circuit 40, sampling circuit 42 and control signal circuit 44 of Fig. 6.
- sampling circuit 42 is represented by boxcar averager 42′ and control signal circuit 44 is illustrated as comprising analog-to-digital converter 120 and latch 124.
- the output of boxcar averager 42′ is coupled to the input of analog-to-digital converter 120, the output of analog-to-digital converter 120 is coupled, over line 122, to the input of latch 124, and the output of latch 124 is coupled, over line 58, to the input of MDAC 60.
- Analog-to-digital converter 120 requires a control signal CONV from control circuit 40′ which indicates when an analog-to-digital conversion is required.
- Analog-to-digital converter 120 provides a control signal EOC to control circuit 40′ indicating when analog-to-digital converter 120 has completed the requisite analog-to-digital conversion.
- Control circuit 40′ must also provide a control signal ENA to latch 124 which enables latch 124 at the appropriate time for operation of MDAC 60.
- Analog-to-digital converter 120 converts the digital value of the error voltage produced from boxcar averager 42′. The resultant digital output from analog-to-digital converter 120 is fed through transparent latch 124 to MDAC 60. Latch 124 holds the last digital value when the pole-zero cancellation process terminates.
- MDAC 60 is provided digital data from the output of latch 124, which data operates to set MDAC 60 at a value which tends to cancel, by operation of pole-zero network 46, undershoot in system 10.
- LED indicator may be provided to show that an error signal is continued to be generated by boxcar averager 42′ and this indicator may be turned off when no additional processing is required to complete cancellation, namely, when network 46 has operated to cancel undershoot in system 10.
- network 46 may be made operational by manual closure of a switch (not shown) by the system operator. When the switch is closed, boxcar averager 42′ is operational to control the setting of MDAC 46 and, with the switch open, the continued adjustment of MDAC is terminated.
- This switch may, for example, be located in the connecting line 122 between analog-to-digital converter 120 and latch 124. In the embodiment of Fig.
- control signal circuit 44 comprises a comparator 126 and a successive approximation register (SAR) 128.
- the output of boxcar averager 42′ is connected to an input of comparator 126, whereas a second input of comparator 126 is provided with a reference signal.
- the output of comparator 126 is coupled to an input of SAR 128 and the output of SAR 128 is coupled, by line 58, to the input of MDAC 60.
- Comparator 126 samples the error voltage produced by boxcar averager 42′ and compares this voltage to a reference.
- SAR 128 is used to test a "one" in each bit position of MDAC 60, successivelysively, from the most significant bit to the least significant bit of MDAC 60. Depending upon the level of the quantized error signal from comparator 126, the present bit being tested is either maintained at a "one” or is set to a "zero” for the next trial. The process terminates when each bit in the MDAC has been tested once.
- Control circuit 40 ⁇ is simply required to generate a control signal CONV indicating when SAR 128 is to sample the output of comparator 126, and SAR 128 provides an end of conversion, EOC control signal, back to control circuitry 40′.
- Signal CK is a clock signal from circuit 40 ⁇ to SAR 128.
- control signal circuit 44 illustrated in Fig. 11 includes an upper lever comparator 130, a lower level comparator 132, and an up/down counter 134.
- the output of boxcar averager 42′ is coupled to the positive input of upper level comparator 130 and to the negative input of lower level comparator 132.
- An upper level reference is provided to the negative input terminal of comparator 130 and a lower level reference is provided to the positive input terminal of comparator 132.
- the outputs of comparators 130 and 132 are provided to control circuitry 40′′′.
- Comparators 130 and 132 together comprise a window comparator which samples the error voltage produced by boxcar averager 42′ and compares this voltage with the window reference values indicated by the upper level reference and the lower level reference provided to comparators 130 and 132, respectively. These window reference values determine the acceptable bounds of the error signal.
- Up/down counter 134 is coupled to receive an enable signal ENA for control circuit 40′′′ and a corresponding up count signal UP or a down count signal DN if the error signal generated by comparators 130 and 132 exceeds the window limits. If the error signal is within the window limits, the counter is not changed and the pole-zero process terminates, having the proper adjustment.
- Up/down counter 134 is enabled upon receipt of enable signal ENA from control circuit 40′′′ and up down counter 134 provides a completion signal CO to control circuit 40′′′ upon completion of the up/down count.
- the up/down counter 134 is provided with a clock signal CK from the control circuit 40′′′ after one or more samples of the baseline following receipt of a signal by the boxcar averager 42′.
- the control circuit 40′′′ includes a divide by n counter to allow the boxcar averager 42′ to average n samples before providing a clock signal to the up/down counter. A large value of n reduces the probability of prematurely terminating the pole-zero process when sampling a low amplitude signal with a corresponding small amplitude tail.
- the maximum time needed to complete the pole-zero process is determined by the maximum dynamic range of the MDAC 60′ divided by the count rate of the amplifier signals times the value of n in the control circuit 40′′′.
- the maximum time required with n equal one using a 12-bit MDAC and a minimum count rate of 100 counts per second is 40 seconds. As implemented a value of four was chosen to limit the maximum time of adjustment to less than 3 minutes for the given conditions.
- the output of up down counter 134 is provided as a digital input control signal over line 58 to MDAC 60.
- control circuit 40′, 40 ⁇ and 40′′′ comprises simple standard control technology necessary to operate a latch, a successive approximation register, or an up/down counter in a conventional manner.
- Control circuit 40 of Fig. 6 and the corresponding control circuits 40′, 40 ⁇ and 40′′′, of Figs. 9, 10 and 11 preferably contain logic circuitry to determine if an event was valid, i.e. , not overloaded and not piled up. This logic circuitry also determines the timing and duration of the sampling process for sampling circuit 42, namely, boxcar averager 42′ of Figs. 9, 10 and 11. In addition, the control circuits preferably control the number of valid boxcar averager samples required prior to the next incremental trial value for appropriate attentuation in pole-zero network 46, and these circuits determine when the pole-zero process terminates.
- an LED indicator may be employed to indicate when the pole-zero cancellation process is in effect and the indicator may be turned off when that process is completed.
- the automatic pole-zero adjustment circuit described above employs use of digital conversion which permits the requisite fine adjustment of a pole-zero network to achieve pole-zero cancellation.
- the amplitude of the resultant random pulses in system 10 preferably are measured to an accuracy on the order of one part in ten thousand and adjustment of undershoot may be achieved, in accordance with the teachings of the subject invention, on this same order of accuracy.
- pole-zero network which includes a real pole corresponding to the real pole of the high pass filter of the system itself permits the utilization of relatively inexpensive amplifiers as input and output buffers to an MDAC, resulting in a sufficiently stable and fast pole-zero network to achieve the objective of automatically cancelling undershoot in the resultant random pulses of the system.
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Abstract
Description
- The present invention is directed toward an ionizing radiation spectroscopy system having a circuit which provides for automatic pole-zero adjustment of that system.
- In a typical ionizing radiation spectroscopy system, such as a
prior art system 10 illustrated in Fig. 1, incident X-ray, α-ray or alpha-ray radiation from aradiation source 12 is directed toward anionizing radiation detector 14. The ionized radiation liberates charge in the form of electron-hole pairs in an electric field withindetector 14, which preferably is of a solid state variety. - In addition to
detector 14,system 10 includes apreamplifier 16, ahigh pass filter 18, which includes a capacitor C[1] and a resistor R[1], anamplifier section 20, including anamplifier stage 22 having a feedback resistor and a second stage amplifier/filter 24, and adisplay 26. The output ofdetector 14 is coupled to an input ofpreamplifier 16, whereas the output ofpreamplifier 16 is connected, throughhigh pass filter 18, to a summing input ofamplifier 22, the output of which is connected to the input of amplifier/filter 24. The output of amplifier/filter 24 is connected to the input ofdisplay 26.Display 26 comprises a multichannel pluse-height analyzer (MCA) which analyzes and displays the output ofamplifier section 20. - In operation of
system 10, charge is collected to the detector electrodes ofdetector 14 to produce an output current pulse with a total charge which is proportional to the energy of the radiation absorbed bydetector 14.Preamplifier 16 is charge sensitive and integrates this current pluse to produce a corresponding voltage pulse e[pa](t).Succeeding amplifier 22 and amplifier/filter 24 provide shaping for signal-to-noise enhancement. The peak amplitudes of the processed pulses are digitalized by an analog-to-digital converter withindisplay 26 and a resultant pulse-height distribution is displayed bydisplay 26. This pulse-height distribution may also be sotred in memory for later analysis. The value of capacitor C[1] and/or resistor R[1] may be charged to alter the time constant offilter 18. -
System 10 of Fig. 1 must add minimum noise to the signal output fromdetector 14 and must be able to process that signal in the shortest possible time.Preamplifier 16 is optimized for minimum noise.Amplifier 20 provides additional gain and optimized filtering in order to achieve maximum reduction of the preamplifier and detector noise contributions with minimum processing time. -
Preamplifier 16 represents a low pass filter with a typical time constant of 50 µs to 1 ms. The impulse response ofpreamplifier 16 is, therefore, a voltage step followed by a decaying exponential, e[pa](t) as shown in Fig. 2. The subsequenthigh pass filter 18 and amplifier 20 act to differentiate the preamplifier pulse and introduce additional poles at relatively short time constants. The simpliest differentiating network, a high pass filter comprising capacitor C[1] and R[1], has a zero at the origin of the S plane. The use ofhigh pass filter 18 with an exponentially decaying preamplifier signal, such as e[pa](t), produces an undesirable undershoot in the resultant signal E(1)(t), as shown in Fig. 3. Undershoot, as shown in Fig. 3, results in a very long pulse processing times, thus aggrevating pulse-pile up, i.e., the interference by one pulse on the system amplitude determination of successive pulses. In addition, uncompensated signularities, namely the pole ofpreamplifier 16 and the zero ofhigh pass filter 18, can have a detrimental effect on the noise performance of the overall spectroscopy chain ofsystem 10. - A technique to completely cancel undershoot resulting from high pass filtering of a preamplifier outout signal is disclosed by Nowlin et al. in an article entitled "Elimination of Undesirable Undershoot in the Operation and Testing of Nuclear Pulse Amplifiers," Rev. Sci. Instr., Vol. 36, No. 12, December 1965, pp. 1830-1839, the contents of which are incorporated herein by reference. This technique is commonly called pole-zero cancellation. In the differentiation network comprising
high pass filter 18, or the electrical equivalent thereof, the zero at the origin of the S-plane is shifted to a location coincident with the pole from the preamplifier. One illustrative network often used for pole-zero cancellation is illustrated in Fig. 4 as comprising resistor R[2] and resistor R[3] coupled to a high pass filter comprising capacitor C[1] and resistor R[1]. As should be apparent to one skilled in the art, by using the network of Fig. 4, an attenuated replica of the output signal frompreamplifier 16 may be added to the differentiated signal from the output ofhigh pass filter 18 to exactly cancel the undershoot illustrated in Fig. 3. The resultant output voltage fromhigh pass filter 18, e[1](t) is illustrated in Fig. 5. It should also be apparent to one skilled in the art that thehigh pass filter 18 of Fig. 1, with capacitor C[1] and resistor R[1] in series, is electrically equivalent to the high pass filter illustrated in Fig. 4 also comprising capacitor C[1] and resistor R[1]. - Other configurations have been used in the prior art to accomplish pole-zero cancellation, as is evidenced by the article by Casoli et al. entitled "Active Pole-Zero Cancellation Feedback Loop to Enhance High-Rate Performances of Nuclear Spectroscopy System," Nucl. Inst. and Meth., Vol. 156, 1978, pp. 559-566, the contents of which is also incorporated herein by reference.
- In order to optimize system performance for a given preamplifier-filter-amplifier combination, the pole-zero adjustment is critical. This adjustment is typically performed by a skilled operator by means of an oscilloscope as evidenced by the above-mentioned Casoli et al. article. The pole-zero adjustment is made difficult due to the follow factors: (1) the noise at the output of the amplifier obscures the effects of any adjustment for undershoot; (2) the vertical gain of the oscilloscope must be limited to avoid distortion caused by overload or the input signal must be limited by a resistor-diode clamping network; and (3) the statistical amplitude distribution of the amplifier output pulses masks effects of the pole-zero adjustments. Considerable operator skill is required to make a pole-zero adjustment which results in adequate system performance.
- In 1982, in an article by Cova et al. entitled "Automated Regulation of Critical Parameters and Related Design Aspects of Spectroscopy Amplifiers with Time-Invariant Filters," I.E.E.E. Trans. on Nucl. Sci., NS-29(1), Feb. 1982, pp. 609-613, a circuit was introduced for assisting in manually adjusting a pole-zero cancellation circuit. A similar disclosure appears in U.S. Patent No. 4,491,799 issued to Giardinelli. The content of both these documents is incorported herein by reference.
- The circuit disclosed by Cova et al. and Giardinelli eliminates the need for an oscilloscope, eliminates the need for a limiting network and reduces the skill required in pole-zero adjustment of the system. The circuit comprises a boxcar averager, two light-emitting diodes (LEDs), and associated control circuitry. The boxcar averager is used to sample the base line at the output of the amplifier, such as the output of
amplifier 20 of Fig. 1, after each pulse which is validly detected bydetector 14. The LEDs are then used to indicate whether the resultant pulse, e[1](t), possesses an undershoot as shown in Fig. 3 or an overshoot, with one of the LEDs being lit in the presence of an undershoot, and the other of the LEDs being lit in the presence of an overshoot. Adjustment is then made in a pole-zero compensation circuit of the type illustrated in Fig. 4, until both LEDs are turned off. However, with this technique the setting of pole-zero compensation is still a manual adjustment, requiring the operator to turn a potentiameter until proper compensation is achieved. - An object of the present invention is to provide an automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system.
- Additional objects and advantages of the present invention will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention.
- To achieve the foregoing objects, and in accordance with the purposes of the invention, as embodied and broadly described herein, an automatic pole-zero adjustment circuit is provided for an ionizing radiation spectroscopy system comprising a pole-zero network circuit, coupled to the system and having an electrical characteristic which varies as a function of an input control signal, for permitting pole-zero adjustment of the system, a sampling circuit, coupled to the system, for sampling a segment of the trailing edge of random pulses passing through the system, and a control signal circuit, coupled to the sampling circuit, for generating the input control signal as a function of the sampling to permit cancellation of undershoot in the system by the pole-zero network circuit. Preferably the sampling circuit comprises a boxcar averager circuit, the electrical characteristic of the pole-zero network circuit is resistance, and the pole-zero network circuit comprises a Multiplying Digital-To-Analog Converter (MDAC).
- More specifically, and preferably, the pole-zero network circuit includes an input buffer amplifier coupled to the input of the MDAC and an output buffer coupled to the output of the MDAC. As noted above, prior art systems include a high pass filter and, preferably, the pole-zero network circuit of the subject invention includes a circuit coupled to the input amplifier, having a time constant equal to the time constant of the high pass filter.
- As was also noted above, prior art ionization spectroscopy systems have a real pole of a high pass filter in the signal path of the system. In accordance with the present invention there is preferably a pole-zero network circuit, coupled to the system, for permitting pole-zero adjustment of the system in response to an input control signal, with the network circuit including a real pole in the signal path of the network circuit set coincident with the real pole of the high pass filter. The pole-zero network circuit of the subject invention also preferably comprises an input buffer amplifier, a multiplying digital-to-analog converter (MDAC) and an output buffer amplifier connected in series with one another, wherein the input buffer amplifier includes a circuit to establish the above-mentioned real pole in the signal path of the network circuit.
- Still further, the system of the subject invention preferably includes a first mechanism for changing the real pole of the high pass filter and the network circuit includes a second mechanism, responsive to operation of the first mechanism, for correspondingly changing the real pole of the signal path of the network circuit.
- The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate examples of the preferred embodiment of the invention and, together with the general description of the invention given above and a detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
- Fig. 1 is a block diagram of a prior art ionizing radiation spectroscopy system;
- Fig. 2 is a diagram of the voltage step output of the preamplifier of the prior art system of Fig. 1;
- Fig. 3 is a diagram of the voltage step output of the amplifier of the prior art system of Fig. 1;
- Fig. 4 is a circuit diagram of a prior art pole-zero compensation circuit;
- Fig. 5 is a diagram of the voltage step output of the amplifier of the prior art system of Fig. 1 using the pole-zero compensation circuit of Fig. 4;
- Fig. 6 is a block diagram of an automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system incorporating the teachings of the present invention;
- Fig. 7 is a circuit diagram of a preferred embodiment of the pole-zero network of Fig. 6;
- Fig. 8 is a circuit diagram of a still further preferred embodiment of the pole-zero network of Fig. 6;
- Fig. 9 is a block diagram of one embodiment of the control signal circuit illustrated in Fig. 6;
- Fig. 10 is a block diagram of an alternative embodiment of the control signal circuit illustrated in Fig. 6;
- Fig. 11 is still a further preferred embodiment of the control signal circuit of Fig. 6.
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- As indicated in
Equation 3,system 10 at the output ofhigh pass filter 18 has one "zero" represented by "s" in the numerator and two "poles" represented by the terms (s + 1/T[pa]) and (s + 1/t[1]) in the denominator. - An object of the pole-zero cancellation network illustrated in Fig. 4 is to provide pole-zero cancellation with regard to the poles and zeros present in
Equation 3. Specifically, with regard to the network illustrated in Fig. 4 E[1](s) may be represented as:
T[pa] = R[2] * C[1]/K. (8)
Thus,
e[1](t) = E[max] * exp(-t/T[p]). (10) - As may be seen by a comparison of E[1](s) in
Equation 3 and in Equation 9, one pole and one zero have been cancelled using the network of Fig. 4. - Reference will now be made in detail to the present preferred embodiment of the subject invention as illustrated in the accompanying drawings.
- In Fig. 6, a
control circuit 40,sampling circuit 42, control signal circuit 44, and pole-zeronetwork 46 are shown coupled to a prior art ionizingradiation spectroscopy system 10 of they type illustrated in Fig. 1.Control circuit 40 has aninput line 50 coupled from amplifier/filter 24 which receives a sampled output ofamplifier 24 prior to any low pass filtering by amplifier/filter 24 so as to provide an identification pulse for operation withincontrol circuit 40. Samplingcircuit 42 has aninput line 52 from amplifier/filter 24 which receives output signal provided by amplifier/filter 24 but which, preferably has been clamped.Control circuit 40 hasoutput lines sampling circuit 42 and control signal circuit 44, respectively, as is described in more detail below. The output ofsampling circuit 42 is provided to the input of control signal circuit 44. The output of control signal circuit 44 is provided overline 58, in the form of an input control signal, to pole-zeronetwork 46. Pole-zeronetwork 46 is, in the preferred embodiment of Fig. 6, coupled acrosshigh pass filter 18 ofsystem 10. As will be described in more detail below, pole-zeronetwork 46 includes an electrical characteristic, such as resistance, which varies as a function of the input control signal online 58, to permit pole-zero adjustment ofsystem 10. - Sampling
circuit 42 operates to sample a segment of the trailing edge of random pulses passing throughsystem 10. Samplingcircuit 42, in the preferred embodiment of the present invention, comprises a standard boxcar averager circuit of the type illustrated in the Cova et al. article and the Giardinelli patent referred to above. The output ofsampling circuit 42, accordingly, has an amplitude representative of the sampled preselected intervals of the trailing edge for a plurality of validly detected random pulses fromsystem 10. This output signal amplitude is a weighted average of the trailing edges in these sampled intervals. -
Control circuit 40 operates, as should be apparent to one skilled in the art, to govern the timing ofsampling circuit 42 to assure that only a predetermined segment of the trailing edge of each validly detected random pulse is sampled by samplingcircuit 42. The operation of the present invention is not dependent upon the particular configuration ofsampling circuit 42, or the particular manner in whichsampling circuit 42 is connected to the amplifier/filter chain ofsystem 10. All that is required is that samplingcircuit 42 operate to sample a segment of the trailing edge of valid events detected bysystem 10. - Pole-zero
network 46 comprises an electronically controlled attenuation element. Although pole-zeronetwork 46 might be implemented in several different ways, two preferred embodiments of pole-zeronetwork 46 are illustrated in Figs. 7 and 8. The embodiment of pole-zeronetwork 46 illustrated in Fig.7 comprises a Multiplying Digital To Analog Converter (MDAC) 60,input buffer amplifier 62,output buffer amplifier 64, and resistors R[a], R[z], and R[x]. Resistor R[a] is coupled between the input ofhigh pass filter 18 and the summing input ofbuffer amplifier 62. Resistor R[x] is provided as a feedback resister forbuffer amplifier 62.Buffer amplifier 62 is connected as an input buffer amplifier toMDAC 60, the output of which is coupled to the summing input terminal ofoutput buffer amplifier 64. The output ofbuffer amplifier 64 is coupled through resistor R[z], to the summing input ofamplifier 22. The attenuation value "K" ofMDAC 60, namely the resistance ofMDAC 60, is controlled by a digital signal from control signal circuit 44 overline 58. -
-
- Thus, the input control signal over
line 58 toMDAC 60 must operate to adjust the value K ofMDAC 60 to meet the criteria ofequation 16 or 17. This is achieved by developing the input control signal overline 58 as a function of the sampling performed by samplingcircuit 42, which in turn represents the mean average of the undershoot and overshoot of the trailing edges of the random pulses validly detected bysystem 10. -
- The preferred embodiment of pole-zero
network 46 illustrated in Fig. 8 includes the addition of a capacitor C[x] in parallel with resistor R[x]. The existence of this capacitor establishes a real pole T[x] = R[x] * C[x] in the signal path ofnetwork 46. This pole may be set to coincide with the real pole inhigh pass filter 18′. This configuration allows the use of relatively slow, commercially available low noiseoperational amplifiers - In the embodiment of
network 46 illustrated in Fig. 8,high pass filter 18′ includes a switch 70 and a plurality ofadditional capacitors high pass filter 18′. Thus,system 10 in this configuration includes a first mecanism for changing the real pole of the high pass filter of that system. In accordance with the present invention, a second mechanism is provided, responsive to operation of the first mechanism, for correspondingly changing the real pole in the signal path of the pole-zero network. As shown in Fig. 8, by way of example and not limitation, a double pole, switch 90 is provided along with a plurality ofcapacitors corresponding resistors 102, 104, 106, 108 and 110. Switches 70 and 90 are ganged together so that a change in the position of switch 70 results in a corresponding change of both poles of switch 90. With resistor R1 set at approximately 700 ohms and capacitor C[1] set at 150 pF, the resultant time constant is approximately 0,5 µs. With these settings, R[x] may be set at 80 kOhm and C[x] set at 240 pF. Corresponding,capacitor 72 may have a value of 1 000 pF for a time constant of 1 µs and corresponding capacitor 92 andresistor 102 may have values of 510 pF and 40 kOhm. - For time constants of 2 µs, 3 µs, 6 µs and 10 µs,
capacitors capacitors resistors 102, 104, 108 and 100 have corresponding values of 20 kOhm , 10,87 kOhm , 4,17 kOhm and 1,47 kOhm. With these illustrative values,buffer amplifiers MDAC 60 may comprise a model AD 7541A. - Figs. 9, 10 and 11 illustrate three alternative preferred embodiments of the
control circuit 40,sampling circuit 42 and control signal circuit 44 of Fig. 6. In the embodiment of Fig. 9,sampling circuit 42 is represented byboxcar averager 42′ and control signal circuit 44 is illustrated as comprising analog-to-digital converter 120 and latch 124. The output ofboxcar averager 42′ is coupled to the input of analog-to-digital converter 120, the output of analog-to-digital converter 120 is coupled, overline 122, to the input of latch 124, and the output of latch 124 is coupled, overline 58, to the input ofMDAC 60. Analog-to-digital converter 120 requires a control signal CONV fromcontrol circuit 40′ which indicates when an analog-to-digital conversion is required. Analog-to-digital converter 120 provides a control signal EOC to controlcircuit 40′ indicating when analog-to-digital converter 120 has completed the requisite analog-to-digital conversion.Control circuit 40′ must also provide a control signal ENA to latch 124 which enables latch 124 at the appropriate time for operation ofMDAC 60. Analog-to-digital converter 120 converts the digital value of the error voltage produced fromboxcar averager 42′. The resultant digital output from analog-to-digital converter 120 is fed through transparent latch 124 toMDAC 60. Latch 124 holds the last digital value when the pole-zero cancellation process terminates. Thus,MDAC 60 is provided digital data from the output of latch 124, which data operates to setMDAC 60 at a value which tends to cancel, by operation of pole-zeronetwork 46, undershoot insystem 10. - As LED indicator (not shown) may be provided to show that an error signal is continued to be generated by
boxcar averager 42′ and this indicator may be turned off when no additional processing is required to complete cancellation, namely, whennetwork 46 has operated to cancel undershoot insystem 10. In the alternative,network 46 may be made operational by manual closure of a switch (not shown) by the system operator. When the switch is closed,boxcar averager 42′ is operational to control the setting ofMDAC 46 and, with the switch open, the continued adjustment of MDAC is terminated. This switch may, for example, be located in the connectingline 122 between analog-to-digital converter 120 and latch 124. In the embodiment of Fig. 10, control signal circuit 44 comprises acomparator 126 and a successive approximation register (SAR) 128. The output ofboxcar averager 42′ is connected to an input ofcomparator 126, whereas a second input ofcomparator 126 is provided with a reference signal. The output ofcomparator 126 is coupled to an input ofSAR 128 and the output ofSAR 128 is coupled, byline 58, to the input ofMDAC 60. -
Comparator 126 samples the error voltage produced byboxcar averager 42′ and compares this voltage to a reference.SAR 128 is used to test a "one" in each bit position ofMDAC 60, successively, from the most significant bit to the least significant bit ofMDAC 60. Depending upon the level of the quantized error signal fromcomparator 126, the present bit being tested is either maintained at a "one" or is set to a "zero" for the next trial. The process terminates when each bit in the MDAC has been tested once.Control circuit 40˝ is simply required to generate a control signal CONV indicating whenSAR 128 is to sample the output ofcomparator 126, andSAR 128 provides an end of conversion, EOC control signal, back tocontrol circuitry 40′. Signal CK is a clock signal fromcircuit 40˝ toSAR 128. - The embodiment of control signal circuit 44 illustrated in Fig. 11 includes an
upper lever comparator 130, alower level comparator 132, and an up/downcounter 134. The output ofboxcar averager 42′ is coupled to the positive input ofupper level comparator 130 and to the negative input oflower level comparator 132. An upper level reference is provided to the negative input terminal ofcomparator 130 and a lower level reference is provided to the positive input terminal ofcomparator 132. The outputs ofcomparators circuitry 40‴.Comparators boxcar averager 42′ and compares this voltage with the window reference values indicated by the upper level reference and the lower level reference provided tocomparators counter 134 is coupled to receive an enable signal ENA forcontrol circuit 40‴ and a corresponding up count signal UP or a down count signal DN if the error signal generated bycomparators - Up/down
counter 134 is enabled upon receipt of enable signal ENA fromcontrol circuit 40‴ and up down counter 134 provides a completion signal CO to controlcircuit 40‴ upon completion of the up/down count. The up/downcounter 134 is provided with a clock signal CK from thecontrol circuit 40‴ after one or more samples of the baseline following receipt of a signal by theboxcar averager 42′. Thecontrol circuit 40‴ includes a divide by n counter to allow theboxcar averager 42′ to average n samples before providing a clock signal to the up/down counter. A large value of n reduces the probability of prematurely terminating the pole-zero process when sampling a low amplitude signal with a corresponding small amplitude tail. The maximum time needed to complete the pole-zero process is determined by the maximum dynamic range of theMDAC 60′ divided by the count rate of the amplifier signals times the value of n in thecontrol circuit 40‴. The maximum time required with n equal one using a 12-bit MDAC and a minimum count rate of 100 counts per second is 40 seconds. As implemented a value of four was chosen to limit the maximum time of adjustment to less than 3 minutes for the given conditions. The output of up downcounter 134 is provided as a digital input control signal overline 58 toMDAC 60. - As should be readily apparent to one skilled in the art given the above descriptions, the actual content of
control circuit 40′, 40˝ and 40‴, comprises simple standard control technology necessary to operate a latch, a successive approximation register, or an up/down counter in a conventional manner. -
Control circuit 40 of Fig. 6 and thecorresponding control circuits 40′, 40˝ and 40‴, of Figs. 9, 10 and 11 preferably contain logic circuitry to determine if an event was valid, i.e., not overloaded and not piled up. This logic circuitry also determines the timing and duration of the sampling process for samplingcircuit 42, namely,boxcar averager 42′ of Figs. 9, 10 and 11. In addition, the control circuits preferably control the number of valid boxcar averager samples required prior to the next incremental trial value for appropriate attentuation in pole-zeronetwork 46, and these circuits determine when the pole-zero process terminates. As noted above, an LED indicator may be employed to indicate when the pole-zero cancellation process is in effect and the indicator may be turned off when that process is completed. Again, the specific implementation of this type circuitry should be well undershoot to one skilled in the art, given the foregoing descriptions. - The automatic pole-zero adjustment circuit described above employs use of digital conversion which permits the requisite fine adjustment of a pole-zero network to achieve pole-zero cancellation. The amplitude of the resultant random pulses in
system 10 preferably are measured to an accuracy on the order of one part in ten thousand and adjustment of undershoot may be achieved, in accordance with the teachings of the subject invention, on this same order of accuracy. The use of a pole-zero network which includes a real pole corresponding to the real pole of the high pass filter of the system itself permits the utilization of relatively inexpensive amplifiers as input and output buffers to an MDAC, resulting in a sufficiently stable and fast pole-zero network to achieve the objective of automatically cancelling undershoot in the resultant random pulses of the system. - Additional advantages and modifications will readily occur to those skilled in the art. The invention in its broader aspects is not, therefore, limited to the specific details, representative methods and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of applicant's generic inventive concept.
Claims (14)
pole-zero network means (46), coupled to said system (10) and having an electrical characteristic which varies as a function of an input control signal, for permitting pole-zero adjustment of said system;
sampling means (42), coupled to said system for sampling a segment of the trailing edge of random pulses passing through said system; and
control signal means (40, 40′, 40˝, 40‴) coupled to said signal means for generating said input control signal as a function of said sampling to permit cancellation by said pole-zero network (46) of undershoot in said system.
pole-zero network means (46), coupled to said system, for permitting pole-zero adjustment of said system in response to an input control signal, said network means including a real pole in the signal path of said network means set coincident with said real pole of said high pass filter;
sampling means (42), coupled to said system, for sampling a segment of the trailing edge of random pulses passing through said system; and
control signal means (40, 40′, 40˝, 40‴), coupled to said sampling means (42), for generating said input control signal as a function of said sampling to permit cancellation by said pole-zero network means of undershoot in said system.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US144119 | 1988-01-15 | ||
US07144119 US4866400B1 (en) | 1988-01-15 | 1988-01-15 | Automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system |
Publications (3)
Publication Number | Publication Date |
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EP0324063A2 true EP0324063A2 (en) | 1989-07-19 |
EP0324063A3 EP0324063A3 (en) | 1990-12-05 |
EP0324063B1 EP0324063B1 (en) | 1994-06-22 |
Family
ID=22507139
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP88116134A Expired - Lifetime EP0324063B1 (en) | 1988-01-15 | 1988-09-29 | Automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system |
Country Status (4)
Country | Link |
---|---|
US (1) | US4866400B1 (en) |
EP (1) | EP0324063B1 (en) |
JP (1) | JPH01239440A (en) |
DE (1) | DE3850380T2 (en) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
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US5140146A (en) * | 1989-11-20 | 1992-08-18 | Symbol Technologies, Inc. | Bar code symbol reader with modulation enhancement |
DK168676B1 (en) * | 1989-12-22 | 1994-05-16 | Adac Lab A S | Circuit for processing pulse signals |
US5187445A (en) * | 1991-10-28 | 1993-02-16 | Motorola, Inc. | Tuning circuit for continuous-time filters and method therefor |
US5461223A (en) * | 1992-10-09 | 1995-10-24 | Eastman Kodak Company | Bar code detecting circuitry |
DE19638204C1 (en) * | 1996-09-19 | 1998-01-15 | Bosch Gmbh Robert | Air quality meter esp. for CO and NOx |
US5821533A (en) * | 1997-01-14 | 1998-10-13 | Eg&G Instruments, Inc. | Automatic pulse top optimization circuit for an ionizing radiation spectroscopy system |
US5912825A (en) * | 1997-02-27 | 1999-06-15 | Eg&G Instruments, Inc. | Gated base line restorer system |
US5872363A (en) * | 1997-01-14 | 1999-02-16 | Eg&G Instruments, Inc. | Automatic pole zero adjustment circuit for an ionizing radiation spectroscopy system |
US6522984B1 (en) | 1999-07-01 | 2003-02-18 | Canberra Industries, Inc. | Instant pole-zero corrector for digital radiation spectrometers and the same with automatic attenuator calibration |
US6295508B1 (en) | 1999-09-01 | 2001-09-25 | Perkinelmer Instruments, Inc. | Automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system and method |
AU6053399A (en) * | 1999-09-23 | 2001-04-24 | Constellation Technology Corporation | Apparatus and method for automatic correction of pole-zero error in a spectroscopy system |
US6374192B1 (en) | 1999-09-23 | 2002-04-16 | Constellation Technology Corp. | Apparatus and method for automatic correction of pole-zero error in a spectroscopy system |
GB0201260D0 (en) * | 2002-01-21 | 2002-03-06 | Europ Org For Nuclear Research | A sensing and imaging device |
US7385448B2 (en) * | 2006-05-17 | 2008-06-10 | Intelleflex Corporation | Circuitry for adaptively generating and using a reference voltage |
EP1956393A3 (en) | 2006-12-21 | 2014-02-26 | Canberra Industries, Inc. | Method for pole-zero adjustment in radiation measurement systems |
TWI393349B (en) * | 2008-12-17 | 2013-04-11 | Ind Tech Res Inst | Signal transceiver apparatus and system |
JP6574582B2 (en) | 2015-03-13 | 2019-09-11 | キヤノンメディカルシステムズ株式会社 | Waveform shaping filter, integrated circuit, radiation detection apparatus, time shaping method and gain adjustment method for waveform shaping filter |
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EP0081875A2 (en) * | 1981-12-04 | 1983-06-22 | Philips Electronics Uk Limited | Electrical data pulse processing |
US4491799A (en) * | 1981-06-12 | 1985-01-01 | Silena S.P.A. | Device for indicating pole-zero cancellation, in particular for amplifiers for ionizing radiation spectroscopy |
DE3429854A1 (en) * | 1983-08-23 | 1985-03-14 | Zahnradfabrik Friedrichshafen Ag, 7990 Friedrichshafen | Direct-voltage measuring device with offset voltage compensation |
Family Cites Families (1)
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US4481466A (en) * | 1980-11-03 | 1984-11-06 | Coulter Electronics, Inc. | Pulse amplifying system |
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1988
- 1988-01-15 US US07144119 patent/US4866400B1/en not_active Expired - Lifetime
- 1988-09-29 EP EP88116134A patent/EP0324063B1/en not_active Expired - Lifetime
- 1988-09-29 DE DE3850380T patent/DE3850380T2/en not_active Expired - Fee Related
- 1988-09-29 JP JP63245877A patent/JPH01239440A/en active Pending
Patent Citations (3)
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US4491799A (en) * | 1981-06-12 | 1985-01-01 | Silena S.P.A. | Device for indicating pole-zero cancellation, in particular for amplifiers for ionizing radiation spectroscopy |
EP0081875A2 (en) * | 1981-12-04 | 1983-06-22 | Philips Electronics Uk Limited | Electrical data pulse processing |
DE3429854A1 (en) * | 1983-08-23 | 1985-03-14 | Zahnradfabrik Friedrichshafen Ag, 7990 Friedrichshafen | Direct-voltage measuring device with offset voltage compensation |
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Also Published As
Publication number | Publication date |
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DE3850380D1 (en) | 1994-07-28 |
US4866400B1 (en) | 1999-08-31 |
US4866400A (en) | 1989-09-12 |
EP0324063A3 (en) | 1990-12-05 |
JPH01239440A (en) | 1989-09-25 |
DE3850380T2 (en) | 1995-01-19 |
EP0324063B1 (en) | 1994-06-22 |
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