EP0295621A3 - Fast summing circuit - Google Patents

Fast summing circuit Download PDF

Info

Publication number
EP0295621A3
EP0295621A3 EP19880109438 EP88109438A EP0295621A3 EP 0295621 A3 EP0295621 A3 EP 0295621A3 EP 19880109438 EP19880109438 EP 19880109438 EP 88109438 A EP88109438 A EP 88109438A EP 0295621 A3 EP0295621 A3 EP 0295621A3
Authority
EP
European Patent Office
Prior art keywords
zeroth
input data
data signals
natural number
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19880109438
Other languages
German (de)
French (fr)
Other versions
EP0295621A2 (en
Inventor
Akira Ishizuka
Toshihiko Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62148792A external-priority patent/JPH0743644B2/en
Priority claimed from JP62148791A external-priority patent/JPH0743643B2/en
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0295621A2 publication Critical patent/EP0295621A2/en
Publication of EP0295621A3 publication Critical patent/EP0295621A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49994—Sign extension

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Image Processing (AREA)

Abstract

A summing circuit (20) is for summing up zeroth through n-th input data signals A(0) to A(n) to produce a sum signal S consisting of zeroth through m-th output bits s(0) to s(m) where n represents a first predetermined natural number and m represents a second predetermined natural number which is not less than the first predetermined natural number. A preprocessing circuit (22) preprocesses the zeroth through the n-th input data signals A(0) to A(n) into a preprocessed signal which is (n + 1) bits long. A logic circuit (24) carries out a logical operation on the preprocessed signal to produce the sum signal S. For example, each of the zeroth through the n-th input data signals A(0) to A(n) is given by an equation: where a(d) represents a d-th coefficient having one of logic zero and one values, k represents a predetermined integer which is not less than zero, and A represents a common coefficient having the logic zero value. Each of the zeroth through the n-th input data signals A(0) to A(n) may be given by another equation:
EP19880109438 1987-06-15 1988-06-14 Fast summing circuit Withdrawn EP0295621A3 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP148792/87 1987-06-15
JP62148792A JPH0743644B2 (en) 1987-06-15 1987-06-15 Adder
JP148791/87 1987-06-15
JP62148791A JPH0743643B2 (en) 1987-06-15 1987-06-15 Adder

Publications (2)

Publication Number Publication Date
EP0295621A2 EP0295621A2 (en) 1988-12-21
EP0295621A3 true EP0295621A3 (en) 1991-01-09

Family

ID=26478864

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19880109438 Withdrawn EP0295621A3 (en) 1987-06-15 1988-06-14 Fast summing circuit

Country Status (4)

Country Link
US (1) US4884233A (en)
EP (1) EP0295621A3 (en)
AU (1) AU601592B2 (en)
CA (1) CA1283981C (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0428942B1 (en) * 1989-11-13 1998-06-10 Harris Corporation Plural-bit recoding multiplier
TW421757B (en) * 1996-06-06 2001-02-11 Matsushita Electric Ind Co Ltd Arithmetic processor
US20050228845A1 (en) * 2004-04-12 2005-10-13 Mathstar, Inc. Shift and recode multiplier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0206762A2 (en) * 1985-06-19 1986-12-30 Advanced Micro Devices, Inc. Digital electronic multiplier circuits

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4041296A (en) * 1975-12-03 1977-08-09 International Business Machines Incorp. High-speed digital multiply-by-device
JPS5949640A (en) * 1982-09-16 1984-03-22 Toshiba Corp Multiplying circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0206762A2 (en) * 1985-06-19 1986-12-30 Advanced Micro Devices, Inc. Digital electronic multiplier circuits

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS LETTERS, vol. 22, no. 20, 25th September 1986, pages 1061-1062, Stevenage, Herts, GB; M. ROORDA: "Method to reduce the sign bit extension in a multiplier that uses the modified booth algorithm" *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 9, no. 2, July 1966, pages 171-173, New York, US; L.Y. LIU et al.: "Multiplication using 2's complement numbers" *

Also Published As

Publication number Publication date
AU601592B2 (en) 1990-09-13
EP0295621A2 (en) 1988-12-21
US4884233A (en) 1989-11-28
AU1768788A (en) 1988-12-15
CA1283981C (en) 1991-05-07

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