EP0285064A3 - Mehrchip-Modulstruktur - Google Patents

Mehrchip-Modulstruktur Download PDF

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Publication number
EP0285064A3
EP0285064A3 EP88104979A EP88104979A EP0285064A3 EP 0285064 A3 EP0285064 A3 EP 0285064A3 EP 88104979 A EP88104979 A EP 88104979A EP 88104979 A EP88104979 A EP 88104979A EP 0285064 A3 EP0285064 A3 EP 0285064A3
Authority
EP
European Patent Office
Prior art keywords
board
semiconductor devices
pins
chip module
module structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP88104979A
Other languages
English (en)
French (fr)
Other versions
EP0285064A2 (de
Inventor
Takaji Takenaka
Tositada Netsu
Hidetaka Shigi
Masakazu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of EP0285064A2 publication Critical patent/EP0285064A2/de
Publication of EP0285064A3 publication Critical patent/EP0285064A3/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
EP88104979A 1987-04-01 1988-03-28 Mehrchip-Modulstruktur Ceased EP0285064A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP77518/87 1987-04-01
JP62077518A JPS63245952A (ja) 1987-04-01 1987-04-01 マルチチップモジュ−ル構造体

Publications (2)

Publication Number Publication Date
EP0285064A2 EP0285064A2 (de) 1988-10-05
EP0285064A3 true EP0285064A3 (de) 1989-08-02

Family

ID=13636186

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88104979A Ceased EP0285064A3 (de) 1987-04-01 1988-03-28 Mehrchip-Modulstruktur

Country Status (4)

Country Link
US (1) US4930002A (de)
EP (1) EP0285064A3 (de)
JP (1) JPS63245952A (de)
KR (1) KR910001422B1 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63245952A (ja) * 1987-04-01 1988-10-13 Hitachi Ltd マルチチップモジュ−ル構造体
JP2507476B2 (ja) * 1987-09-28 1996-06-12 株式会社東芝 半導体集積回路装置
US4926241A (en) * 1988-02-19 1990-05-15 Microelectronics And Computer Technology Corporation Flip substrate for chip mount
FR2634340B1 (fr) * 1988-07-13 1994-06-17 Thomson Csf Dispositif d'interconnexion entre un circuit integre et un circuit electrique, application du dispositif a la connexion d'un circuit integre notamment a un circuit imprime, et procede de fabrication du dispositif
US5019997A (en) * 1989-06-05 1991-05-28 General Electric Company Adaptive lithography accommodation of tolerances in chip positioning in high density interconnection structures
JPH0378290A (ja) * 1989-08-21 1991-04-03 Hitachi Ltd 多層配線基板
JP2978511B2 (ja) * 1989-09-20 1999-11-15 株式会社日立製作所 集積回路素子実装構造体
US5157477A (en) * 1990-01-10 1992-10-20 International Business Machines Corporation Matched impedance vertical conductors in multilevel dielectric laminated wiring
JPH0716100B2 (ja) * 1990-01-10 1995-02-22 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層配線モジュール
US5200810A (en) * 1990-04-05 1993-04-06 General Electric Company High density interconnect structure with top mounted components
DE59105080D1 (de) * 1990-05-28 1995-05-11 Siemens Ag IC-Gehäuse, bestehend aus drei beschichteten dielektrischen Platten.
JP2960560B2 (ja) * 1991-02-28 1999-10-06 株式会社日立製作所 超小型電子機器
EP0516866A1 (de) * 1991-05-03 1992-12-09 International Business Machines Corporation Modulare mehrschichtige Verbindungsstruktur
JP2960276B2 (ja) * 1992-07-30 1999-10-06 株式会社東芝 多層配線基板、この基板を用いた半導体装置及び多層配線基板の製造方法
US5854534A (en) * 1992-08-05 1998-12-29 Fujitsu Limited Controlled impedence interposer substrate
DE69330450T2 (de) * 1992-08-05 2001-11-08 Fujitsu Ltd., Kawasaki Dreidimensionaler Multichipmodul
US5508938A (en) * 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
JP3228589B2 (ja) * 1993-03-15 2001-11-12 株式会社東芝 マルチチップモジュール
US5391914A (en) * 1994-03-16 1995-02-21 The United States Of America As Represented By The Secretary Of The Navy Diamond multilayer multichip module substrate
US5544174A (en) * 1994-03-17 1996-08-06 The United States Of America As Represented By The Secretary Of The Air Force Programmable boundary scan and input output parameter device for testing integrated circuits
JP3412942B2 (ja) * 1995-01-11 2003-06-03 株式会社東芝 半導体装置
DE19507547C2 (de) * 1995-03-03 1997-12-11 Siemens Ag Verfahren zur Montage von Chips
TW299564B (de) * 1995-10-04 1997-03-01 Ibm
US5691569A (en) * 1995-12-20 1997-11-25 Intel Corporation Integrated circuit package that has a plurality of staggered pins
US5825628A (en) * 1996-10-03 1998-10-20 International Business Machines Corporation Electronic package with enhanced pad design
JP3063687B2 (ja) * 1997-06-30 2000-07-12 日本電気株式会社 マルチチップモジュール
US6111756A (en) * 1998-09-11 2000-08-29 Fujitsu Limited Universal multichip interconnect systems
KR100341077B1 (en) * 1998-12-31 2002-09-27 Simm Tech Co Ltd Structure of multi-layered module in pcb
JP3558595B2 (ja) * 2000-12-22 2004-08-25 松下電器産業株式会社 半導体チップ，半導体チップ群及びマルチチップモジュール
KR100734290B1 (ko) 2005-11-28 2007-07-02 삼성전자주식회사 출력 채널이 공유되는 테스트 패드를 구비하는 필름형반도체 패키지 및 필름형 반도체 패키지의 테스트 방법,테스트 채널이 공유되는 패턴을 구비하는 테스트 장치 및반도체 장치 그리고 반도체 장치에서의 테스트 방법
US8952540B2 (en) * 2011-06-30 2015-02-10 Intel Corporation In situ-built pin-grid arrays for coreless substrates, and methods of making same
KR101672640B1 (ko) * 2015-06-23 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US11647582B1 (en) 2020-08-26 2023-05-09 Ian Getreu Rapid implementation of high-temperature analog interface electronics

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0070533A2 (de) * 1981-07-22 1983-01-26 International Business Machines Corporation Substrat für Halbleiterchips
FR2549641A1 (fr) * 1983-07-19 1985-01-25 Nec Corp Ensemble a integration a grande echelle comportant un substrat en ceramique multicouche

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231154A (en) * 1979-01-10 1980-11-04 International Business Machines Corporation Electronic package assembly method
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
JPS5815264A (ja) * 1981-07-21 1983-01-28 Nec Corp マルチチツプパツケ−ジ
US4602271A (en) * 1981-07-22 1986-07-22 International Business Machines Corporation Personalizable masterslice substrate for semiconductor chips
JPS6014494A (ja) * 1983-07-04 1985-01-25 株式会社日立製作所 セラミツク多層配線基板およびその製造方法
US4649417A (en) * 1983-09-22 1987-03-10 International Business Machines Corporation Multiple voltage integrated circuit packaging substrate
JPS6124255A (ja) * 1984-07-13 1986-02-01 Hitachi Ltd 半導体パツケ−ジ構造
JPS6127667A (ja) * 1984-07-17 1986-02-07 Mitsubishi Electric Corp 半導体装置
JPS621258A (ja) * 1985-06-26 1987-01-07 Nec Corp マルチチツプパツケ−ジ
US4811082A (en) * 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
JPS63245952A (ja) * 1987-04-01 1988-10-13 Hitachi Ltd マルチチップモジュ−ル構造体

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0070533A2 (de) * 1981-07-22 1983-01-26 International Business Machines Corporation Substrat für Halbleiterchips
FR2549641A1 (fr) * 1983-07-19 1985-01-25 Nec Corp Ensemble a integration a grande echelle comportant un substrat en ceramique multicouche

Also Published As

Publication number Publication date
JPS63245952A (ja) 1988-10-13
KR880013241A (ko) 1988-11-30
US4930002A (en) 1990-05-29
EP0285064A2 (de) 1988-10-05
KR910001422B1 (ko) 1991-03-05

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