EP0274942A2 - Flat panel matrix visualisation system with protected display of primary data for exploitation - Google Patents

Flat panel matrix visualisation system with protected display of primary data for exploitation Download PDF

Info

Publication number
EP0274942A2
EP0274942A2 EP87402822A EP87402822A EP0274942A2 EP 0274942 A2 EP0274942 A2 EP 0274942A2 EP 87402822 A EP87402822 A EP 87402822A EP 87402822 A EP87402822 A EP 87402822A EP 0274942 A2 EP0274942 A2 EP 0274942A2
Authority
EP
European Patent Office
Prior art keywords
image
addressing
circuits
odd
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP87402822A
Other languages
German (de)
French (fr)
Other versions
EP0274942A3 (en
EP0274942B1 (en
Inventor
Jean-Pierre Bouron
Daniel Giroux
Pierre Rousseau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of EP0274942A2 publication Critical patent/EP0274942A2/en
Publication of EP0274942A3 publication Critical patent/EP0274942A3/en
Application granted granted Critical
Publication of EP0274942B1 publication Critical patent/EP0274942B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the present invention relates to information display systems by display on a flat screen of the matrix addressing type.
  • the invention is particularly applicable in the avionics field for the display of piloting data.
  • the display can be of the head-up or head-down type.
  • the amount of information to be displayed on the display devices fitted to the dashboard of modern aircraft is becoming more and more important, with conventional electromechanical instrumentation disappearing.
  • a certain amount of information to be displayed is essential for flight safety or operation and must therefore be safe and always displayed, or viewable.
  • the object of the invention is to satisfy these requirements by implementing a specific structuring of the display system.
  • a display system on a flat matrix screen comprising, a display device composed of the flat screen and matrix addressing means controlled to obtain an image resulting from an even image and from an interlaced odd image, these means comprising four groups of circuits for addressing respectively the even lines and columns forming the even image and the odd lines and columns forming the odd image, graphic processor means for developing the video signals to be displayed by addressing columns and scanning signals by addressing lines, the system being characterized in that the graphics processor means are distributed in two subsets, a first subset for developing the even image and a second subset for developing the odd image.
  • the resulting advantages translate into enhanced security by a reduced probability of viewing the erroneous information, the proposed structure allowing the detection of such information by observation of the screen.
  • the structure used ensures a high level of safety compatible with the strict requirements in terms of airworthiness certification.
  • Another advantage results from the continuous availability of essential information, the solution implemented making it possible to protect the display of this data by reproducing it after a failure and thus to keep in operation a display at least restricted to this essential information for the exploitation. This also results in a reduction in maintenance costs by reducing the removal of equipment.
  • FIG. 1 we distinguish the structure of the flat screen which is briefly recalled. It essentially consists of a bottom plate 1, made of glass or ceramic, on which are arranged parallel to each other transparent electrodes 2 corresponding to the lines of the screen; a front plate 3 also transparent, made of glass or silica, which forms the front face of the screen and on which is arranged another network of electrodes 4 perpendicular to the first and corresponding to the columns. Between the two thinly spaced plates, and in contact with the two arrays of electrodes forming the matrix, a solid, liquid or gaseous electro-optical material 5, on which the image is formed. For the formation of colors it will be noted that the rows as well as the columns can be distributed successively corresponding to the colors red green and blue so as to produce the desired hues or, by simultaneous control, a monochrome image in black and white.
  • the row 2 and column 4 electrodes are connected to integrated control circuits, or addressing circuits (called drivers) which send them electrical signals.
  • the points of the screen are addressed line by line, at a rate such that all the points are reached at each image renewal; in general this rate is from 50 to 60 Hz.
  • a reaction appears at each addressed point which results in a change in appearance.
  • This can take two different forms, either an emission of light, or a change in the power of reflection or transmission of light.
  • a lighting device 6 placed at the rear, produces the luminance necessary to ensure the visualization of the data displayed on the screen.
  • the materials corresponding to the first case are based on active devices such as plasma screens, screens luminescent or light-emitting diodes, VFD (Vacum Fluorescent Display) screens, etc ...
  • the materials corresponding to the second case are based on passive devices.
  • the best known are constituted by liquid crystals which can be of several types: cholesteric, nematic, smectic, ferroelectric, etc ...
  • a first family groups together the active devices in which each picture element is placed in series with a nonlinear element of the varistor (VRD) type, thin film transistors (TFT), head-to-tail diodes.
  • the second family uses materials with an electro-optical effect with memory; mention may be made of smectic liquid crystals A operating in a mixed thermal and electrical mode and smectic ferroelectric liquid crystals.
  • the invention applies more particularly and advantageously to realizations of flat screen with liquid crystals and with a nematic electro-optical effect in a helix which, associated with an active matrix with TFT and with filters colored, make it possible to produce high resolution color matrix flat screens capable, in particular, of viewing all the piloting information of a modern aircraft.
  • High resolution liquid crystal display screens have two groups of circuits for addressing even rows and columns relating to the development of a so-called even image and two other groups for addressing rows and odd columns relating to the development of a so-called odd image.
  • This operating principle resembles that of television where the image is formed by two interlaced half-frames. But, unlike television where the two half-frames are drawn successively in time, the even and odd images are drawn simultaneously, all the points of the image being reached at each image renewal.
  • These four groups are visible in FIG. 1, the connections to the electrodes of the two groups are shown relative to an even image; the connections of the other two groups have not been shown to simplify the representation. To obtain a high resolution image these four groups present an additional partition of the circuits.
  • each column addressing group is divided into three circuits 7A, 7B, 7C for the even columns, 9A, 9B, 9C for the odd columns and each row addressing group is divided into two blocks 10A and 10B for even lines, 12A and 12B for odd lines.
  • the partition values 2 and 3 considered have been taken as a non-limiting example.
  • An additional graphics processor assembly produces the video signals SV1, SV2, SV3, which are applied respectively to the different addressing circuits columns 7 and 9, and a clock signal H which increments the line counters located in the line addressing circuits 10 and 12.
  • this additional graphics processor assembly consists of a first graphics processor 21 which produces the signals intended for circuits 7 and 10 which make it possible to form the even image, and a second graphics processor 22 which produces the signals for the circuits 9 and 12 used to obtain the odd image.
  • Each of these processors comprises, as indicated for block 21, at least one symbol generator circuit 211 associated with an image memory 212.
  • the control signals and those corresponding to the information to be displayed reach the processors 21 and 22 through interface circuits, respectively 23 and 24.
  • Circuits indicated by circles can for example be sensors whose signals are to be translated by a determined symbology. It can be considered, for example, that the circuit C2A concerns an altitude detector whose signal is after processing applied via the interface 24 to the processor 22.
  • Another device for measuring altitude C2B distinct from the previous one is used to provide the same information through the interface 23 to the processor 21.
  • This redundancy with different multiple sources to translate the same information to be viewed is frequent on airborne or other equipment, for security reasons; it is used in the proposed system when it is classified information which is essential for operation and whose display must be preserved.
  • Each graphics processor comprises, in addition to the symbol generator and the image memory, the essential elements indicated in FIG. 2, namely a video controller circuit 213 which manages the accesses of the symbol generator to the image memory and supplies the signals. scanning the screen for reading in television mode; the circuit 214 represents a management and calculation circuit such as a microprocessor assembly which receives by a bus and the interface 23 not shown the information to be displayed on the screen.
  • the layout of the two even and odd images having to be done simultaneously the subsets 21 and 22 are coordinated from the synchronization point of view; one of the video controller circuits, for example 213, is declared master and supplies the synchronization signals to the other video controller which is declared slave.
  • the synchronization signals are: a clock signal at the point rate and the line and image synchronization signals.
  • FIG. 2 represents the simplest organization envisaged which uses the two graphics processors 21 and 22 and which allows, in the event of a channel failure, the maintenance of display of the image with a resolution half by the another way. Information can therefore always be available and usable.
  • This solution also has a certain flexibility the two channels corresponding to the even image and the odd image can be made asymmetrical, the information coming as it was said from different data sources, the difference can also be made at the level of the symbol generator, the generator 211 at 21 being different from that used at 22.
  • the two interlaced images become different which visually alerts the operator who can no longer do trust the information displayed. This involves on the part of the operator, the pilot on board an aircraft, a verification and control procedure on other instruments available for the same information so as to eliminate, if necessary, the faulty lane and to reconfigure its visualization on the remaining channel.
  • the reconfiguration will cause, if necessary, a change in the master-slave allocation of the remaining video controller.
  • This reconfiguration can be done simply by a mechanical switch device actuated by the operator. It can also be envisaged to program the control of this switch to automatically respond to the different cases.
  • processors specialized in signal processing called DSP (abbreviation of Digital Signal Processor). These graphics processors make it possible to calculate the plot of the symbologies to be stored in the image memories.
  • DSP abbreviation of Digital Signal Processor
  • each processor instead of having a single symbol generator comprises several which work in parallel, each of them being associated to his image memory.
  • the processor 214 is detailed by these main elements a microprocessor 214A, a program memory 214B and a data memory 214C. The program and data buses are shown.
  • the chain A is master and imposes on the other slave chains B, C, D the synchronizations of the write and read modes (pixel, line and frame synchronization).
  • the video signals delivered by the image memories are applied to a video multiplexer 215, then through an output interface circuit 216 are sent, as well as the clock signal, to the even column addressing circuits and to the circuits of addressing even lines as shown in the previous figures.
  • the complementary circuits shown are produced according to known techniques and include smoothing circuits 217A, 217B, 217C, a surfacing circuit 218, a color palette circuit 219A and a pixel storage circuit 219B.
  • smoothing circuits 217A, 217B, 217C a surfacing circuit 218, a color palette circuit 219A and a pixel storage circuit 219B.
  • the master chain A produces the symbology relating to the static image
  • the chain B the symbology relating to the dynamic image
  • the chain C the surface symbology
  • the chain D relates to symbols from a weather radar.
  • the 217C smoothing circuit is not compulsory.
  • the smoothing circuit 217A, B or C gives the displayed trace an analog appearance. It especially removes the steps of stairs which are due to the discretization of the image memory and of the screen 5.
  • the smoothing is obtained by weighting the level of the video signal of the points of the image through which the trace passes as well as that of the adjacent points.
  • the smoothing circuit can, for example, consist of a set of read-only memories which, depending on the position and the direction of the trace, provide the coefficients to be applied to the points of the trace.
  • the surfacing circuit 218 allows the interior of surfaces to be filled with a certain color.
  • the color codes of the points of each surface are stored in the image memory.
  • the color palette circuit 219A makes it possible to code the levels of the video R, G, B from the color codes provided by the image memory. Transcoding is obtained by a table which can be loaded dynamically by the processor. This allows to have an infinity of colors.
  • the pixel arrangement circuit 219A from the knowledge of the distribution of the color points of the screen (stored in read-only memory for example) ensures the selection of the right video to the screen 5.
  • FIG. 4 represents a third embodiment according to which the display screen 5 is divided into several bands, for example into three vertical bands 5A, 5B, 5C.
  • Each band is controlled through the associated column addressing circuits 9A, 9B, 9C, 11A, 11B, 11C by a pair of graphics processors 21A and 22A for the first band 5A, 21B and 22B for the second band 5B and 21C and 22C for the third band 5C.
  • Each processor comprises as symbolized in block 21B a generator of symbols and an associated image memory.
  • the two graphics processors associated with a strip trace all the information to be displayed in this strip.
  • the synchronization switch circuit 29A is derived from that 29 of FIG. 2; it brings together the various switches useful for performing the necessary reconfigurations in the event of channel failures, each channel corresponding to a strip of the screen and to the associated graphics processors.
  • the advantages of this third embodiment are that, in the event of a channel failure, either at the level of the symbol generator, column addressing circuits or even of the screen, or even upstream of the processor, the processing and the visualization of the essential information lost can be taken into account by another channel or by several of the other channels. We can thus present with the remaining elements a complete image with a reduced format usable by the pilot.
  • FIG. 5 illustrates the case where the channel corresponding to the band 5A breaks down.
  • the programming is such that the symbology which existed in this surface band A A1 C C1 is transferred to the level of the assembly remaining delimited by the surface A1 B C1 D of the screen with compression in the direction of the lines.
  • Programming can also be provided to maintain homothety to the new figure by also reducing the height of the image; under these conditions, the complete image occurs in the area A2 B2 C2 D2 indicated with a reduction of a third compared to the case where the entire screen is viewed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

Système permettant d'assurer une grande sécurité d'exploitation par une protection poussée de l'affichage des données primordiales.Il comporte un écran plat (5) matriciel, par exemple à cristaux liquides, avec des circuits d'adressage pour obtenir une image entrelacée type télévision. Les circuits sont divisés en plusieurs blocs aussi bien pour l'adressage des colonnes paires et impaires que celui des lignes paires et impaires afin de produire une image à haute résolution. Les moyens processeurs graphiques utilisés comportent deux sous-ensembles (21 et 22), un pour chaque image, chacun d'eux ayant au moins un générateur de symboles(211), associé à une mémoire d'image (212). L'invention s'applique notamment en avionique pour assurer la sécurité de vol.System for ensuring high operational security by providing extensive protection for the display of essential data. It comprises a matrix flat screen (5), for example with liquid crystal, with addressing circuits for obtaining an interlaced image. television type. The circuits are divided into several blocks for addressing the even and odd columns as well as that of the even and odd lines in order to produce a high resolution image. The graphics processor means used comprise two sub-assemblies (21 and 22), one for each image, each of them having at least one symbol generator (211), associated with an image memory (212). The invention is particularly applicable in avionics to ensure flight safety.

Description

La présente invention concerne des systèmes de visualisation d'informations par affichage sur écran plat de type à adressage matriciel.The present invention relates to information display systems by display on a flat screen of the matrix addressing type.

L'invention s'applique notamment dans le domaine avionique pour l'affichage de données de pilotage. La visualisation peut être du type tête haute ou tête basse.The invention is particularly applicable in the avionics field for the display of piloting data. The display can be of the head-up or head-down type.

La quantité d'informations à afficher sur les appareils de visualisation équipant le tableau de bord des aéronefs modernes devient de plus en plus importante, l'instrumentation électromécanique conventionnelle disparaissant. Un certain nombre des informations à visualiser sont essentielles pour la sécurité de vol ou l'exploitation et doivent donc être sûres et toujours visualisées, ou visualisables.The amount of information to be displayed on the display devices fitted to the dashboard of modern aircraft is becoming more and more important, with conventional electromechanical instrumentation disappearing. A certain amount of information to be displayed is essential for flight safety or operation and must therefore be safe and always displayed, or viewable.

Le but de l'invention est de satisfaire à ces impératifs en mettant en oeuvre une structuration particulière du système de visualisation.The object of the invention is to satisfy these requirements by implementing a specific structuring of the display system.

Suivant l'invention il est proposé de réaliser un système de visualisation sur écran plat matriciel comportant, un dispositif de visualisation composé de l'écran plat et de moyens d'adressage matriciel commandés pour obtenir une image résultant d'une image paire et d'une image impaire entrelacées, ces moyens comportant quatre groupes de circuits pour l'adressage respectivement des lignes et colonnes paires formant l'image paire et des lignes et colonnes impaires formant l'image impaire, des moyens processeurs graphiques pour élaborer les signaux vidéo à visualiser par adressage des colonnes et des signaux de balayage par adressage lignes, le système étant caractérisé en ce que les moyens processeurs graphiques sont répartis en deux sous-ensembles, un premier sous-ensemble permettant d'élaborer l'image paire et un deuxième sous-ensemble permettant d'élaborer l'image impaire.According to the invention, it is proposed to produce a display system on a flat matrix screen comprising, a display device composed of the flat screen and matrix addressing means controlled to obtain an image resulting from an even image and from an interlaced odd image, these means comprising four groups of circuits for addressing respectively the even lines and columns forming the even image and the odd lines and columns forming the odd image, graphic processor means for developing the video signals to be displayed by addressing columns and scanning signals by addressing lines, the system being characterized in that the graphics processor means are distributed in two subsets, a first subset for developing the even image and a second subset for developing the odd image.

Les avantages qui en résultent se traduisent au niveau de la sécurité renforcée par une probabilité réduite de visualiser les informations erronées, la structure proposée permettant la détection de telles informations par observation de l'écran. En ce sens la structure utilisée assure un haut niveau de sécurité compatible avec les exigences sévères en matière de certification de navigabilité. Un autre avantage résulte de la disponibilité continuelle des informations essentielles, la solution mise en oeuvre permettant de protéger l'affichage de ces données en les reproduisant après une panne et ainsi de garder en fonctionnement un affichage au moins restreint à ces informations essentielles pour l'exploitation. Il en résulte également une diminution des coûts de maintenance par réduction des déposes d'équipement.The resulting advantages translate into enhanced security by a reduced probability of viewing the erroneous information, the proposed structure allowing the detection of such information by observation of the screen. In this sense, the structure used ensures a high level of safety compatible with the strict requirements in terms of airworthiness certification. Another advantage results from the continuous availability of essential information, the solution implemented making it possible to protect the display of this data by reproducing it after a failure and thus to keep in operation a display at least restricted to this essential information for the exploitation. This also results in a reduction in maintenance costs by reducing the removal of equipment.

Il est connu par le brevet français FR-A-2 571 571 de réaliser un générateur d'images qui, grâce à une mémoire d'image, peut commander des visualisations utilisant des balayages différents, soit le balayage cavalier produit directement par un générateur de symboles, soit d'autres types de balayage par l'intermédiaire de la mémoire d'image tel que le balayage tramé ou entrelacé dit de télévision, ou le balayage matriciel.It is known from French patent FR-A-2 571 571 to produce an image generator which, thanks to an image memory, can control displays using different scans, namely the jumper scan produced directly by a generator. symbols, or other types of scanning via the image memory such as raster or interlaced scanning called television, or matrix scanning.

Les particularités et avantages de l'invention apparaîtront dans la description qui suit donnée à titre d'exemple à l'aide des figures annexées qui représentent :

  • - Fig.1, un schéma général d'un système de visualisation conforme à l'invention ;
  • - Fig.2, un premier mode de réalisation du système ;
  • - Fig.3, un deuxième mode de réalisation du système ;
  • - Fig.4, un troisième mode de réalisation du système ;
  • - Fig.5, un schéma illustrant la protection de l'affichage dans un système selon la figure 4.
The features and advantages of the invention will appear in the description which follows, given by way of example with the aid of the appended figures which represent:
  • - Fig.1, a general diagram of a display system according to the invention;
  • - Fig.2, a first embodiment of the system;
  • - Fig.3, a second embodiment of the system;
  • - Fig.4, a third embodiment of the system;
  • - Fig.5, a diagram illustrating the protection of the display in a system according to Figure 4.

En se reportant à la figure 1 on distingue la structure de l'écran plat qui est rappelée brièvement. Il se compose essentiellement d'une plaque de fond 1, en verre ou en céramique, sur laquelle sont disposées parallèlement les unes aux autres des électrodes transparentes 2 correspondant aux lignes de l'écran ; une plaque avant 3 également transparente, en verre ou en silice, qui forme la face antérieure de l'écran et sur laquelle est disposé un autre réseau d'électrodes 4 perpendiculaire au premier et correspondant aux colonnes. Entre les deux plaques faiblement espacées, et au contact des deux réseaux d'électrodes formant la matrice, un matériau électro-optique 5 solide, liquide ou gazeux, sur lequel se forme l'image. Pour la formation de couleurs on notera que les lignes ainsi que les colonnes peuvent être réparties successivement correspondant aux couleurs rouge vert et bleu de manière à produire les teintes désirées ou, par commande simultanée, une image monochrome en noir et blanc.Referring to Figure 1 we distinguish the structure of the flat screen which is briefly recalled. It essentially consists of a bottom plate 1, made of glass or ceramic, on which are arranged parallel to each other transparent electrodes 2 corresponding to the lines of the screen; a front plate 3 also transparent, made of glass or silica, which forms the front face of the screen and on which is arranged another network of electrodes 4 perpendicular to the first and corresponding to the columns. Between the two thinly spaced plates, and in contact with the two arrays of electrodes forming the matrix, a solid, liquid or gaseous electro-optical material 5, on which the image is formed. For the formation of colors it will be noted that the rows as well as the columns can be distributed successively corresponding to the colors red green and blue so as to produce the desired hues or, by simultaneous control, a monochrome image in black and white.

Les électrodes lignes 2 et colonnes 4 sont reliées à des circuits intégrés de commande, ou circuits d'adressage (appelés drivers en anglais) qui leur envoient des signaux électriques. L'adressage des points de l'écran se fait ligne à ligne, à une cadence telle que tous les points sont atteints à chaque renouvellement d'image ; en général cette cadence est de 50 à 60 Hz.The row 2 and column 4 electrodes are connected to integrated control circuits, or addressing circuits (called drivers) which send them electrical signals. The points of the screen are addressed line by line, at a rate such that all the points are reached at each image renewal; in general this rate is from 50 to 60 Hz.

Suivant le matériau électro-optique, en réponse aux signaux électriques de commande, apparaît en chaque point adressé une réaction qui se traduit par un changement d'aspect. Celui-ci peut revêtir deux formes différentes, soit une émission de lumière, soit un changement du pouvoir de réflexion ou de transmission de la lumière. Pour les systèmes qui modulent la transmission de la lumière un dispositif d'éclairage 6, placé à l'arrière produit la luminance nécessaire pour assurer la visualisation des données affichées sur l'écran.Depending on the electro-optical material, in response to the electrical control signals, a reaction appears at each addressed point which results in a change in appearance. This can take two different forms, either an emission of light, or a change in the power of reflection or transmission of light. For systems which modulate the transmission of light, a lighting device 6, placed at the rear, produces the luminance necessary to ensure the visualization of the data displayed on the screen.

Les matériaux correspondant au premier cas sont à base de dispositifs actifs tels que les écrans à plasma, les écrans luminescents ou à diodes électro-luminescentes, les écrans VFD (Vacum Fluorescent Display), etc ...The materials corresponding to the first case are based on active devices such as plasma screens, screens luminescent or light-emitting diodes, VFD (Vacum Fluorescent Display) screens, etc ...

Les matériaux correspondant au deuxième cas sont à base de dispositifs passifs. Les plus connus sont constitués par des cristaux liquides qui peuvent être de plusieurs types : cholestériques, nématiques, smectiques, ferro-électriques, etc ...The materials corresponding to the second case are based on passive devices. The best known are constituted by liquid crystals which can be of several types: cholesteric, nematic, smectic, ferroelectric, etc ...

Ces différents matériaux peuvent être répertoriés selon deux familles. Une première famille regroupe les dispositifs actifs dans lesquels chaque éléments d'image est mis en série avec un élément non linéaire du type varistance (VRD), transistors couche mince (TFT), diodes tête-bêche. La seconde famille fait appel à des matériaux possédant un effet électro-optique à mémoire ; on peut citer les cristaux liquides smectiques A fonctionnant suivant un mode mixte thermique et électrique et les cristaux liquides smectiques ferro-électriques.These different materials can be classified according to two families. A first family groups together the active devices in which each picture element is placed in series with a nonlinear element of the varistor (VRD) type, thin film transistors (TFT), head-to-tail diodes. The second family uses materials with an electro-optical effect with memory; mention may be made of smectic liquid crystals A operating in a mixed thermal and electrical mode and smectic ferroelectric liquid crystals.

Dans l'état présent de la technique l'invention s'applique plus particulièrement et avantageusement à des réalisations d'écran plat à cristaux liquides et à effet électro-optique nématique en hélice qui, associés à une matrice active à TFT et à des filtres colorés, permettent de réaliser des écrans plats matriciels couleur à haute résolution capables, notamment, de visualiser toutes les informations de pilotage d'un aéronef moderne.In the present state of the art the invention applies more particularly and advantageously to realizations of flat screen with liquid crystals and with a nematic electro-optical effect in a helix which, associated with an active matrix with TFT and with filters colored, make it possible to produce high resolution color matrix flat screens capable, in particular, of viewing all the piloting information of a modern aircraft.

Les écrans de visualisation à cristaux liquides dits LCD (Liquid Cristal Display) à haute résolution comportent deux groupes de circuits pour adresser les lignes et colonnes paires relatives à l'élaboration d'une image dite paire et deux autres groupes pour adresser les lignes et les colonnes impaires relatives à l'élaboration d'une image dite impaire. Ce principe de fonctionnement ressemble à celui de la télévision où l'image est formée de deux demi-trames entrelacées. Mais, contrairement à la télévision où les deux demi-trames sont tracées successivement dans le temps, les images paires et impaires sont tracées simultanément, tous les points de l'image étant atteints à chaque renouvellement d'image. Ces quatre groupes sont visibles sur la figure 1, on a représenté les connexions aux électrodes des deux groupes relatives à une image paire ; les connexions des deux autres groupes n'ont pas été figurées pour simplifier la représentation. Pour obtenir une image à haute résolution ces quatre groupes présentent une partition supplémentaire des circuits. Ainsi, dans l'exemple représenté, chaque groupe d'adressage des colonnes est divisé en trois circuits 7A, 7B, 7C pour les colonnes paires, 9A, 9B, 9C pour les colonnes impaires et chaque groupe d'adressage des lignes est divisé en deux blocs 10A et 10B pour les lignes paires, 12A et 12B pour les lignes impaires. Les valeurs de partition 2 et 3 considérées ont été prises à titre d'exemple non limitatif.High resolution liquid crystal display screens (LCD) have two groups of circuits for addressing even rows and columns relating to the development of a so-called even image and two other groups for addressing rows and odd columns relating to the development of a so-called odd image. This operating principle resembles that of television where the image is formed by two interlaced half-frames. But, unlike television where the two half-frames are drawn successively in time, the even and odd images are drawn simultaneously, all the points of the image being reached at each image renewal. These four groups are visible in FIG. 1, the connections to the electrodes of the two groups are shown relative to an even image; the connections of the other two groups have not been shown to simplify the representation. To obtain a high resolution image these four groups present an additional partition of the circuits. Thus, in the example shown, each column addressing group is divided into three circuits 7A, 7B, 7C for the even columns, 9A, 9B, 9C for the odd columns and each row addressing group is divided into two blocks 10A and 10B for even lines, 12A and 12B for odd lines. The partition values 2 and 3 considered have been taken as a non-limiting example.

Les raisons de cette partition résultent de plusieurs facteurs qui sont : le faible pas de la connectique qui impose que les lignes et colonnes soient entrelacées du point de vue connexion avec les circuits d'adressage ; le coût élevé des circuits d'adressage qui ont un grand nombre de sorties ; le fait que l'adressage des points est tel que, à chaque ligne, trois colonnes peuvent ainsi être adressées simultanément ce qui diminue la bande passante du signal vidéo.The reasons for this partition result from several factors which are: the weak step of the connection which requires that the rows and columns are interlaced from the point of view of connection with the addressing circuits; the high cost of the addressing circuits which have a large number of outputs; the fact that the addressing of the points is such that, on each line, three columns can thus be addressed simultaneously, which decreases the bandwidth of the video signal.

Un ensemble processeur graphique annexe élabore les signaux vidéo SV1, SV2, SV3, qui sont appliqués respectivement aux différents circuits d'adressage colonnes 7 et 9, et un signal d'horloge H qui incrémente les compteurs lignes situés dans les circuits d'adressage lignes 10 et 12.An additional graphics processor assembly produces the video signals SV1, SV2, SV3, which are applied respectively to the different addressing circuits columns 7 and 9, and a clock signal H which increments the line counters located in the line addressing circuits 10 and 12.

Conformément à l'invention cet ensemble processeur graphique annexe se compose d'un premier processeur graphique 21 qui élabore les signaux destinés aux circuits 7 et 10 qui permettent de former l'image paire, et un deuxième processeur graphique 22 qui produit les signaux pour les circuits 9 et 12 servant à obtenir l'image impaire. Chacun de ces processeurs comportent comme indiqué pour le bloc 21 au moins un circuit générateur de symboles 211 associé à une mémoire d'images 212. Les signaux de commande et ceux correspondant aux informations à visualiser parviennent aux processeurs 21 et 22 à travers des circuits d'interface, respectivement 23 et 24. Des circuits indiqués par des cercles peuvent être par exemple des capteurs dont les signaux sont à traduire par une symbologie déterminée. On peut considérer, par exemple, que le circuit C2A concerne un détecteur d'altitude dont le signal est après traitement appliqué via l'interface 24 au processeur 22. Un autre dispositif de mesure d'altitude C2B distinct du précédent est utilisé pour fournir la même information à travers l'interface 23 au processeur 21. Cette redondance avec des sources multiples différentes pour traduire la même information à visualiser est fréquente sur des matériels aéroportés, ou autres, pour des raisons de sécurité ; elle est utilisée dans le système proposé lorsqu'il s'agit d'une information classifiée primordiale pour l'exploitation et dont la visualisation est à préserver.In accordance with the invention, this additional graphics processor assembly consists of a first graphics processor 21 which produces the signals intended for circuits 7 and 10 which make it possible to form the even image, and a second graphics processor 22 which produces the signals for the circuits 9 and 12 used to obtain the odd image. Each of these processors comprises, as indicated for block 21, at least one symbol generator circuit 211 associated with an image memory 212. The control signals and those corresponding to the information to be displayed reach the processors 21 and 22 through interface circuits, respectively 23 and 24. Circuits indicated by circles can for example be sensors whose signals are to be translated by a determined symbology. It can be considered, for example, that the circuit C2A concerns an altitude detector whose signal is after processing applied via the interface 24 to the processor 22. Another device for measuring altitude C2B distinct from the previous one is used to provide the same information through the interface 23 to the processor 21. This redundancy with different multiple sources to translate the same information to be viewed is frequent on airborne or other equipment, for security reasons; it is used in the proposed system when it is classified information which is essential for operation and whose display must be preserved.

Chaque processeur graphique comporte, outre le générateur de symboles et la mémoire d'image, les éléments essentiels indiqués sur la figure 2 à savoir un circuit contrôleur vidéo 213 qui gère les accès du générateur de symboles à la mémoire d' image et fournit les signaux de balayage de l'écran pour effectuer une lecture en mode télévision ; le circuit 214 représente un circuit de gestion et de calcul tel un ensemble à microprocesseur qui reçoit par un bus et l'interface 23 non figuré les informations à visualiser sur l'écran.Each graphics processor comprises, in addition to the symbol generator and the image memory, the essential elements indicated in FIG. 2, namely a video controller circuit 213 which manages the accesses of the symbol generator to the image memory and supplies the signals. scanning the screen for reading in television mode; the circuit 214 represents a management and calculation circuit such as a microprocessor assembly which receives by a bus and the interface 23 not shown the information to be displayed on the screen.

Le tracé des deux images paires et impaire devant se faire simultanément les sous-ensembles 21 et 22 sont coordonnés du point de vue synchronisation ; l'un des circuits contrôleurs vidéo, 213 par exemple, est déclaré maître et fournit les signaux de synchronisation à l'autre contrôleur vidéo qui est déclaré esclave.The layout of the two even and odd images having to be done simultaneously the subsets 21 and 22 are coordinated from the synchronization point of view; one of the video controller circuits, for example 213, is declared master and supplies the synchronization signals to the other video controller which is declared slave.

Les signaux de synchronisation sont : un signal d'horloge à la cadence point et les signaux de synchronisation de ligne et d'image.The synchronization signals are: a clock signal at the point rate and the line and image synchronization signals.

La figure 2 représente l'organisation la plus simple envisagée qui utilise les deux processeurs graphiques 21 et 22 et qui qui permet, en cas de panne d'une voie, le maintien d'affichage de l'image avec une résolution moitié par l'autre voie. Les informations peuvent donc ainsi être toujours disponibles et exploitables. Cette solution présente également une certaine souplesse les deux voies correspondant à l'image paire et à l'image impaire peuvent être rendues dissymétriques, les informations provenant comme il a été dit de sources de données différentes, la différence peut également être apportée au niveau du générateur de symboles, le générateur 211 en 21 étant différent de celui utilisé en 22. Ainsi en cas de panne, ou d'erreur sur les informations visualisées, les deux images entrelacées deviennent différentes ce qui alerte visuellement l'exploitant qui ne peut plus faire confiance aux informations visualisées. Ceci entraîne de la part de l'exploitant, le pilote à bord d'un aéronef, une procédure de vérification et de contrôle sur d'autres instruments disponibles pour la même information de manière à éliminer, le cas échéant, la voie défaillante et reconfigurer sa visualisation sur la voie restante.FIG. 2 represents the simplest organization envisaged which uses the two graphics processors 21 and 22 and which allows, in the event of a channel failure, the maintenance of display of the image with a resolution half by the another way. Information can therefore always be available and usable. This solution also has a certain flexibility the two channels corresponding to the even image and the odd image can be made asymmetrical, the information coming as it was said from different data sources, the difference can also be made at the level of the symbol generator, the generator 211 at 21 being different from that used at 22. Thus in the event of a breakdown, or an error in the information displayed, the two interlaced images become different which visually alerts the operator who can no longer do trust the information displayed. This involves on the part of the operator, the pilot on board an aircraft, a verification and control procedure on other instruments available for the same information so as to eliminate, if necessary, the faulty lane and to reconfigure its visualization on the remaining channel.

La reconfiguration va entraîner, si nécessaire, un changement de l'attribution maître-esclave du contrôleur vidéo restant.The reconfiguration will cause, if necessary, a change in the master-slave allocation of the remaining video controller.

Cette reconfiguration peut se faire simplement par un dispositif commutateur mécanique actionné par l'opérateur. Il peut être envisagé aussi de programmer la commande de ce commutateur pour répondre automatiquement aux différents cas de figure.This reconfiguration can be done simply by a mechanical switch device actuated by the operator. It can also be envisaged to program the control of this switch to automatically respond to the different cases.

Il est possible d'utiliser comme générateurs de symboles des processeurs spécialisés dans le traitement du signal dit DSP (abréviation de Digital Signal Processor). Ces processeurs graphiques permettent de calculer le tracé des symbologies à stocker dans les mémoires d'images. A titre d'exemple de processeur on peut citer le TMS 320 10 ou le TMMS 320 20 de Texas et ADSP 2100 de Analog Device.It is possible to use as symbol generators processors specialized in signal processing called DSP (abbreviation of Digital Signal Processor). These graphics processors make it possible to calculate the plot of the symbologies to be stored in the image memories. As an example of processor we can cite the TMS 320 10 or the TMMS 320 20 from Texas and ADSP 2100 from Analog Device.

Suivant un autre mode de réalisation indiqué à la figure 3 pour l'un des processeurs graphiques, par exemple le processeur 22, chaque processeur au lieu de comporter un seul générateur de symboles en comporte plusieurs qui travaillent en parallèle, chacun d'eux étant associé à sa mémoire d'images. Dans cet exemple il y a quatre générateurs de symboles 211A à 211D et leurs circuits associés composés des mémoires d'images 212A à 212D et des contrôleurs graphiques 213A à 213D. Le processeur 214, est détaillé par ces éléments principaux un micro processeur 214A, une mémoire programme 214B et une mémoire de données 214C. Les bus de programme et de données sont représentés. La chaîne A est maître et impose aux autres chaînes esclaves B, C, D les synchronisations des modes écriture et lecture (synhronisation pixel, lignes et trames). Les signaux vidéo délivrés par les mémoires d'images sont appliqués à un multiplexeur vidéo 215, puis à travers un circuit d'interface de sortie 216 sont envoyés, ainsi que le signal horloge, aux circuits d'adressage colonnes paires et aux circuits d'adressage lignes paires comme indiqué sur les figures précédentes.According to another embodiment indicated in FIG. 3 for one of the graphics processors, for example the processor 22, each processor instead of having a single symbol generator comprises several which work in parallel, each of them being associated to his image memory. In this example there are four symbol generators 211A to 211D and their associated circuits composed of image memories 212A to 212D and graphic controllers 213A to 213D. The processor 214 is detailed by these main elements a microprocessor 214A, a program memory 214B and a data memory 214C. The program and data buses are shown. The chain A is master and imposes on the other slave chains B, C, D the synchronizations of the write and read modes (pixel, line and frame synchronization). The video signals delivered by the image memories are applied to a video multiplexer 215, then through an output interface circuit 216 are sent, as well as the clock signal, to the even column addressing circuits and to the circuits of addressing even lines as shown in the previous figures.

Les circuits complémentaires représentés sont réalisés selon des techniques connues et comportent des circuits de lissage 217A, 217B, 217C, un circuit de surfaçage 218, un circuit palette de couleur 219A et un circuit à rangement de pixels 219B. A titre d'exemple, on considère que la chaîne maître A produit la symbologie relative à l'image statique, la chaîne B la symbologie relative à l'image dynamique, la chaîne C la symbologie de surface et la chaîne D est relative à des symboles provenant d'un radar météo. Le circuit de lissage 217C n'est pas obligatoire.The complementary circuits shown are produced according to known techniques and include smoothing circuits 217A, 217B, 217C, a surfacing circuit 218, a color palette circuit 219A and a pixel storage circuit 219B. For example, we consider that the master chain A produces the symbology relating to the static image, the chain B the symbology relating to the dynamic image, the chain C the surface symbology and the chain D relates to symbols from a weather radar. The 217C smoothing circuit is not compulsory.

On rappelle ci-après les fonctions de ces différents circuits :The functions of these different circuits are recalled below:

Le circuit de lissage 217A,B ou C donne au tracé visualisé un aspect analogique. Il supprime en particulier les marches d'escalier qui sont dues à la discrétisation de la mémoire image et de l'écran 5. Le lissage est obtenu en pondérant le niveau du signal vidéo despoints de l'image par lesquels passe le tracé ainsi que celui des points adjacents. Le circuit de lissage peut, par exemple, être constitué par un ensemble de mémoires mortes qui, en fonction de la position et de la direction du tracé, fournissent les coefficients à appliquer sur les points du tracé.The smoothing circuit 217A, B or C gives the displayed trace an analog appearance. It especially removes the steps of stairs which are due to the discretization of the image memory and of the screen 5. The smoothing is obtained by weighting the level of the video signal of the points of the image through which the trace passes as well as that of the adjacent points. The smoothing circuit can, for example, consist of a set of read-only memories which, depending on the position and the direction of the trace, provide the coefficients to be applied to the points of the trace.

Le circuit de surfaçage 218 permet de remplir avec une certaine couleur l'intérieur de surfaces. Les codes de couleurs des points de chaque surface sont mémorisés dans la mémoire image.The surfacing circuit 218 allows the interior of surfaces to be filled with a certain color. The color codes of the points of each surface are stored in the image memory.

Le circuit palette de couleurs 219A permet de coder les niveaux des vidéo R,V,B à partir des codes de couleurs fournis par la mémoire image. Le transcodage est obtenu par une table qui peut être chargée dynamiquement par le processeur. Ceci permet d'avoir une infinité de couleurs.The color palette circuit 219A makes it possible to code the levels of the video R, G, B from the color codes provided by the image memory. Transcoding is obtained by a table which can be loaded dynamically by the processor. This allows to have an infinity of colors.

Le long d'une ligne se balayage, contrairement à une visualisation à tube à masque où les trois vidéo R,V,B sont envoyées simultanément sur chaque point, une seule des trois vidéo est envoyée sur chaque point de l'écran 5. Le circuit d'arrangement des pixels 219A à partir de la connaissance de la répartition des points de couleur de l'écran (mémorisée en mémoire morte par exemple) assure la sélection de la bonne vidéo vers l'écran 5.Along a scanning line, unlike a mask tube display where the three videos R, G, B are sent simultaneously to each point, only one of the three videos is sent to each point of the screen 5. The pixel arrangement circuit 219A from the knowledge of the distribution of the color points of the screen (stored in read-only memory for example) ensures the selection of the right video to the screen 5.

Les avantages de ce mode de réalisation à plusieurs générateurs de symboles pour chaque image sont les suivants : partage des taches de tracé ; structure modulaire qui permet d'adapter le nombre de générateurs de symboles à la charge de tracé pour une visualisation donnée ; protection de la visualisation des données essentielles en cas de panne d'une chaîne. Ainsi, si par exemple les données essentielles sont produites par des générateurs de symboles de la chaîne maîtresse A et de la chaîne esclave B, et si la chaîne B tombe en panne, il est possible d'avoir une programmation prévue en conséquence pour faire produire par le générateur 213A de la chaîne A les données qui font défaut dans la chaîne B. Dans le cas précédent figure 2, chacun des processeurs 21 et 22 comportait les données essentielles dans un seul générateur de symboles, la panne de l'un d'eux se traduisant par une atténuation de l'image visualisée. On entend par panne une panne de voie qui peut se traduire à partir de la mémoire d'images et en amont jusqu'à la formation du signal, par exemple jusqu'au niveau du capteur 2A, ou 2B, qui avait été considéré.The advantages of this embodiment with several symbol generators for each image are the following: sharing of the trace tasks; modular structure which allows the number of symbol generators to be adapted to the drawing load for a given visualization; protection of the viewing of essential data in the event of a chain failure. Thus, if for example the essential data is produced by symbol generators of the master chain A and of the slave chain B, and if the chain B breaks down, it is possible to have a programming provided accordingly to cause production by generator 213A of the chain A the data which are lacking in chain B. In the previous case in FIG. 2, each of the processors 21 and 22 contained the essential data in a single generator of symbols, the failure of one of them resulting in an attenuation of the displayed image. Failure is understood to mean a channel failure which can result from the image memory and upstream until the signal is formed, for example up to the level of the sensor 2A, or 2B, which had been considered.

Pour l'exemple envisagé on remarquera que la technique d'élaboration d'images vidéo synthétique développée dans le brevet FR-A-2 571 571 déjà cité, qui détermine une découpe de l'image mémorisée en zones en affectant à chaque zone une mémoire de rafraîchissement périodique déterminée adaptée au caractèristiques d'évolution des éléments se trouvant dans cette zone, peut s'appliquer aux deux chaînes A et B puisque l'une est relative aux éléments statiques et l'autre aux éléments dynamiques.For the example envisaged, it will be noted that the technique for developing synthetic video images developed in patent FR-A-2,571,571 already cited, which determines a division of the image stored in zones by allocating a memory to each zone. of determined periodic refresh adapted to the characteristics of evolution of the elements being in this zone, can be applied to the two chains A and B since one relates to the static elements and the other to the dynamic elements.

La figure 4 représente un troisième mode de réalisation suivant lequel l'écran de visualisation 5 est divisé en plusieurs bandes par exemple en trois bandes verticales 5A, 5B, 5C. Chaque bande est contrôlée à travers les circuits d'adressage colonnes associés 9A, 9B, 9C, 11A, 11B, 11C par un couple de processeurs graphiques 21A et 22A pour la première bande 5A, 21B et 22B pour la deuxième bande 5B et 21C et 22C pour la troisième bande 5C. Chaque processeur comporte comme symbolisé dans le bloc 21B un générateur de symboles et une mémoire d'image associés. Suivant ce mode de réalisation les deux processeurs graphiques associés à une bande tracent toutes les informations à visualiser dans cette bande.FIG. 4 represents a third embodiment according to which the display screen 5 is divided into several bands, for example into three vertical bands 5A, 5B, 5C. Each band is controlled through the associated column addressing circuits 9A, 9B, 9C, 11A, 11B, 11C by a pair of graphics processors 21A and 22A for the first band 5A, 21B and 22B for the second band 5B and 21C and 22C for the third band 5C. Each processor comprises as symbolized in block 21B a generator of symbols and an associated image memory. According to this embodiment, the two graphics processors associated with a strip trace all the information to be displayed in this strip.

Le circuit commutateur de synchronisation 29A est dérivé de celui 29 de la figure 2 ; il regroupe les différents commutateurs utiles pour effectuer les reconfigurations nécessaires en cas de pannes de voie, chaque voie correspondant à une bande de l'écran et aux processeurs graphiques associés.The synchronization switch circuit 29A is derived from that 29 of FIG. 2; it brings together the various switches useful for performing the necessary reconfigurations in the event of channel failures, each channel corresponding to a strip of the screen and to the associated graphics processors.

Dans la variante de réalisation figure 4 il n'est pas exclu d'avoir plusieurs générateurs de symboles dans chacun des processeurs graphiques, comme dans lemode décrit à l'aide de la figure 3.In the variant embodiment in FIG. 4, it is not excluded to have several symbol generators in each of the graphics processors, as in the mode described with the aid of FIG. 3.

Les avantages de ce troisième mode de réalisation sont que, en cas de panne d'une voie, soit au niveau du générateur de symboles, des circuits d'adressage colonnes ou même de l'écran, ou encore en amont du processeur, le traitement et la visualisation des informations essentielles perdues peut être pris en compte par une autre voie ou par plusieurs des autres voies. On peut ainsi présenter avec les éléments restants une image complète avec un format réduit exploitable par le pilote.The advantages of this third embodiment are that, in the event of a channel failure, either at the level of the symbol generator, column addressing circuits or even of the screen, or even upstream of the processor, the processing and the visualization of the essential information lost can be taken into account by another channel or by several of the other channels. We can thus present with the remaining elements a complete image with a reduced format usable by the pilot.

La figure 5 illustre le cas où la voie correspondant à la bande 5A tombe en panne. La programmation est telle que la symbologie qui existait dans cette bande de surface A A1 C C1 se trouve reportée au niveau de l'ensemble restant délimité par la surface A1 B C1 D de l'écran avec une compression dans le sens des lignes. La programmation peut également être prévue pour conserver une homothétie à la nouvelle figure en réduisant également la hauteur de l'image ; dans ces conditions, l'image complète se produit dans la surface A2 B2 C2 D2 indiquée avec une réduction d'un tiers par rapport au cas où tout l'écran est visualisé.FIG. 5 illustrates the case where the channel corresponding to the band 5A breaks down. The programming is such that the symbology which existed in this surface band A A1 C C1 is transferred to the level of the assembly remaining delimited by the surface A1 B C1 D of the screen with compression in the direction of the lines. Programming can also be provided to maintain homothety to the new figure by also reducing the height of the image; under these conditions, the complete image occurs in the area A2 B2 C2 D2 indicated with a reduction of a third compared to the case where the entire screen is viewed.

Claims (8)

1. Système de visualisation sur écran plat matriciel comportant :
- un dispositif de visualisation composé dudit écran plat (1 à 6) et de moyens d'adressage matriciel (7, 9, 10, 12) pour obtenir une image résultant d'une image paire et d'une image impaire entrelacées, ces moyens comportant de quatre groupes de circuits pour adresser respectivement les lignes et colonnes paires formant l'image paire et les lignes et colonnes impaires formant l'image impaire, ;
- des moyens processeurs graphiques pour élaborer les signaux vidéo à visualiser par adressage des colonnes et des signaux de balayage appliqués aux lignes,
caractérisé en ce que les moyens processeurs graphiques sont répartis en deux sous-ensembles, un premier sous-ensemble (21) qui est relatif à l'élaboration de l'image paire et un deuxième sous-ensemble (22) relatif à l'image impaire.1. Matrix flat screen display system comprising:
a display device composed of said flat screen (1 to 6) and of matrix addressing means (7, 9, 10, 12) for obtaining an image resulting from an even image and an odd interlaced image, these means comprising four groups of circuits for addressing respectively the even lines and columns forming the even image and the odd lines and columns forming the odd image,;
- graphic processor means for developing the video signals to be displayed by addressing columns and scanning signals applied to the lines,
characterized in that the graphic processor means are divided into two sub-assemblies, a first sub-assembly (21) which relates to the production of the even image and a second sub-assembly (22) relating to the image odd. 2. Système selon la revendication 1, caractérisé en ce que chacun des sous-ensembles processeurs graphiques (21,22) comporte au moins un générateur de symboles (211) associé à une mémoire d'images (212).2. System according to claim 1, characterized in that each of the graphics processor sub-assemblies (21,22) comprises at least one symbol generator (211) associated with an image memory (212). 3. Système selon la revendication 2, caractérisé en ce que les moyens processeurs graphiques comportent des moyens de synchronisation pour effectuer l'adressage matriciel, lesdits sous-ensembles étant coordonnés, l'un (21) jouant le rôle de maître et l'autre (22) étant assujeti au rôle d'esclave.3. System according to claim 2, characterized in that the graphics processor means comprise synchronization means for performing matrix addressing, said subsets being coordinated, one (21) playing the role of master and the other (22) being subject to the role of slave. 4. Système selon la revendication 3, caractérisé en ce qu'il comporte un moyen commutateur (29,29A) interconnecté sur des connexions de synchronisation entre lesdits sous-ensembles et permettant de connecter le rôle de maître lorsque cette fonction n'est plus assurée à la suite d'une panne.4. System according to claim 3, characterized in that it comprises a switching means (29,29A) interconnected on synchronization connections between said subsets and allowing the master role to be connected when this function is no longer ensured following a failure. 5. Système selon la revendication 4, caractérisé en ce que chaque sous-ensemble processeur graphique (21,22) comporte, en outre, un processeur de gestion et de contrôle (214) et un circuit contrôleur vidéo (213) lequel est connecté au dit moyen commutateur (29,29A) pour fournir les signaux de synchronisation dans le cas de la fonction maître ou pour les recevoir dans le cas d'une fonction esclave.5. System according to claim 4, characterized in that each graphics processor sub-assembly (21,22) further comprises a management and control processor (214) and a video controller circuit (213) which is connected to the said switch means (29, 29A) for supplying the synchronization signals in the case of the master function or for receiving them in the case of a slave function. 6. Système selon l'une quelconque des revendications 2 à 5, caractérisé en ce que chaque sous-ensemble processeur graphique (21,22) comporte plusieurs générateurs de symboles (211A à 211D) travaillant en parallèle, chacun d'eux étant associé à une mémoire d'image (212A à 212D) pour y stocker les données correspondantes, les mémoires d'images étant connectées à un circuit multiplexeur vidéo (215).6. System according to any one of claims 2 to 5, characterized in that each graphics processor sub-assembly (21,22) comprises several symbol generators (211A to 211D) working in parallel, each of them being associated with an image memory (212A to 212D) for storing the corresponding data therein, the image memories being connected to a video multiplexer circuit (215). 7. Système selon l'une quelconque des revendications précédentes, appliqué à une visualisation à haute résolution, chacun des groupes (7,9,10,12) de circuits d'adressage étant composé de plusieurs circuits comprenant : m circuits d'adressage (10A,10B) des lignes paires, m circuits d'adressage (12A,12B) des lignes impaires, n circuit d'adressage (7A,7B,7C) des colonnes paires et n circuits d'adressage (9A,9B,9C) des colonnes impaires.7. System according to any one of the preceding claims, applied to a high resolution display, each of the groups (7, 9, 10, 12) of addressing circuits being composed of several circuits comprising: m addressing circuits ( 10A, 10B) of the even lines, m addressing circuits (12A, 12B) of the odd lines, n addressing circuit (7A, 7B, 7C) of the even columns and n addressing circuits (9A, 9B, 9C) odd columns. 8. Système selon la revendication 7, caractérisé en ce qu'il comporte autant de sous-ensembles processeurs graphiques (21A,21B...,22A,22B,...) qu'il y a de circuits d'adressage de colonnes (7A,7B...,9A,9B,...), afin de contrôler l'image de l'écran (5) sous forme de n bandes successives (5A,5B,...).8. System according to claim 7, characterized in that it comprises as many graphics processor sub-assemblies (21A, 21B ..., 22A, 22B, ...) as there are column addressing circuits. (7A, 7B ..., 9A, 9B, ...), in order to control the screen image (5) in the form of n successive bands (5A, 5B, ...).
EP87402822A 1986-12-16 1987-12-11 Flat panel matrix visualisation system with protected display of primary data for exploitation Expired - Lifetime EP0274942B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8617575A FR2608300B1 (en) 1986-12-16 1986-12-16 VISUALIZATION SYSTEM ON A MATRIX FLAT SCREEN WITH PROTECTED DISPLAY OF PRIMORDIAL DATA FOR OPERATION
FR8617575 1986-12-16

Publications (3)

Publication Number Publication Date
EP0274942A2 true EP0274942A2 (en) 1988-07-20
EP0274942A3 EP0274942A3 (en) 1988-07-27
EP0274942B1 EP0274942B1 (en) 1992-03-18

Family

ID=9341942

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87402822A Expired - Lifetime EP0274942B1 (en) 1986-12-16 1987-12-11 Flat panel matrix visualisation system with protected display of primary data for exploitation

Country Status (5)

Country Link
US (1) US4859997A (en)
EP (1) EP0274942B1 (en)
JP (1) JPS63163396A (en)
DE (1) DE3777606D1 (en)
FR (1) FR2608300B1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0368572A2 (en) * 1988-11-05 1990-05-16 SHARP Corporation Device and method for driving a liquid crystal panel
EP0402850A2 (en) * 1989-06-12 1990-12-19 Kabushiki Kaisha Toshiba Dot-matrix display apparatus
FR2660471A1 (en) * 1990-03-30 1991-10-04 Sextant Avionique Safety visual-display device, using a dot matrix screen and aircraft instrument panel including at least one such device
EP0506530A1 (en) * 1991-03-29 1992-09-30 Thomson-Lcd Matrix display with improved definition and addressing method of such a display
EP0673012A2 (en) * 1994-03-11 1995-09-20 Canon Information Systems Research Australia Pty Ltd. Controller for a display with multiple common lines for each pixel
US6002385A (en) * 1994-03-11 1999-12-14 Canon Kabushiki Kaisha Computer display system controller

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02157813A (en) * 1988-12-12 1990-06-18 Sharp Corp Liquid crystal display panel
US5206749A (en) 1990-12-31 1993-04-27 Kopin Corporation Liquid crystal display having essentially single crystal transistors pixels and driving circuits
US5376979A (en) * 1990-12-31 1994-12-27 Kopin Corporation Slide projector mountable light valve display
US5258320A (en) * 1990-12-31 1993-11-02 Kopin Corporation Single crystal silicon arrayed devices for display panels
US5743614A (en) * 1990-12-31 1998-04-28 Kopin Corporation Housing assembly for a matrix display
US5528397A (en) 1991-12-03 1996-06-18 Kopin Corporation Single crystal silicon transistors for display panels
US6320568B1 (en) 1990-12-31 2001-11-20 Kopin Corporation Control system for display panels
US5321505A (en) * 1991-01-11 1994-06-14 Microelectronics & Computer Technology Corporation Computer scalable visualization system
WO1994011855A1 (en) * 1992-11-06 1994-05-26 Virtual Vision, Inc. Head mounted video display system with portable video interface unit
JP3454971B2 (en) * 1995-04-27 2003-10-06 株式会社半導体エネルギー研究所 Image display device
US6025821A (en) * 1998-02-10 2000-02-15 Prince Corporation Drive system for vacuum fluorescent display and method therefor
US6140993A (en) * 1998-06-16 2000-10-31 Atmel Corporation Circuit for transferring high voltage video signal without signal loss
EP1783599A3 (en) * 1998-09-04 2007-06-13 Innovative Solutions & Support, Inc. Flat panel display using dual cpu's for an aircraft cockpit
WO2000014714A1 (en) * 1998-09-04 2000-03-16 Innovative Solutions And Support Inc. Flat panel display using dual cpu's for an aircraft cockpit
GB9902343D0 (en) * 1999-02-04 1999-03-24 Sharp Kk overnment Of The United Kingdom Of Great Britain And Northern Ireland The Addressable matrix arrays
US6671406B1 (en) * 1999-12-29 2003-12-30 Honeywell International Inc. System, method and apparatus for pattern recognition with application to symbol recognition and regeneration for a caligraphic display
JP3873139B2 (en) * 2000-06-09 2007-01-24 株式会社日立製作所 Display device
US20020112479A1 (en) * 2001-01-09 2002-08-22 Keefer Bowie G. Power plant with energy recovery from fuel storage
FR2843646B1 (en) * 2002-08-13 2004-10-29 Thales Sa VISUALIZATION DEVICE WITH SECURE ELECTRONIC ARCHITECTURE
FR2843823B1 (en) * 2002-08-20 2006-04-21 Thales Sa LIQUID CRYSTAL VISUALIZATIONS WITH RELIABLE CONTROL
WO2005035469A1 (en) * 2003-10-02 2005-04-21 Shell Internationale Research Maatschappij B.V. Production of 1-alkenes from mixed olefin streams using catalytic distillation
GB2500401B (en) 2012-03-20 2020-06-03 Ge Aviat Systems Ltd Apparatus for an aircraft cockpit display
GB2501255B (en) * 2012-04-16 2018-04-11 Ge Aviat Systems Ltd Apparatus for aircraft dual channel display
GB2507524B (en) * 2012-11-01 2016-02-24 Ge Aviat Systems Ltd Apparatus for aircraft dual channel display
EP3746877B1 (en) * 2018-01-31 2022-11-09 KONCAR - KET d.o.o. Method and device for displaying safety unit signals with information regarding reliability of displayed signals

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0177247A2 (en) * 1984-09-28 1986-04-09 Kabushiki Kaisha Toshiba Active matrix display device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468659A (en) * 1980-08-25 1984-08-28 Sharp Kabushiki Kaisha Electroluminescent display panel assembly
FR2571571B1 (en) * 1984-10-05 1986-11-28 Thomson Csf METHOD FOR PRODUCING SYNTHETIC VIDEO IMAGES FOR REAL TIME AND HIGH DENSITY INFORMATION DRAWING AND DEVICE USING THE SAME

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0177247A2 (en) * 1984-09-28 1986-04-09 Kabushiki Kaisha Toshiba Active matrix display device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRICAL DESIGN NEWS, vol. 29, no. 15, 16 juillet 1984, pages 132-144, Boston, Massachusetts, US; R. PETERSON: "High-capacity, -contrast LCDs become viable CRT alternatives" *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0368572A2 (en) * 1988-11-05 1990-05-16 SHARP Corporation Device and method for driving a liquid crystal panel
EP0368572A3 (en) * 1988-11-05 1991-08-14 SHARP Corporation Device and method for driving a liquid crystal panel
EP0402850A2 (en) * 1989-06-12 1990-12-19 Kabushiki Kaisha Toshiba Dot-matrix display apparatus
EP0402850A3 (en) * 1989-06-12 1991-10-23 Kabushiki Kaisha Toshiba Dot-matrix display apparatus
US5241304A (en) * 1989-06-12 1993-08-31 Kabushiki Kaisha Toshiba Dot-matrix display apparatus
FR2660471A1 (en) * 1990-03-30 1991-10-04 Sextant Avionique Safety visual-display device, using a dot matrix screen and aircraft instrument panel including at least one such device
EP0506530A1 (en) * 1991-03-29 1992-09-30 Thomson-Lcd Matrix display with improved definition and addressing method of such a display
FR2674663A1 (en) * 1991-03-29 1992-10-02 Thomson Lcd MATRIX SCREEN WITH IMPROVED DEFINITION AND METHOD FOR ADDRESSING SUCH SCREEN.
EP0673012A2 (en) * 1994-03-11 1995-09-20 Canon Information Systems Research Australia Pty Ltd. Controller for a display with multiple common lines for each pixel
EP0673012A3 (en) * 1994-03-11 1996-01-10 Canon Information Syst Res Controller for a display with multiple common lines for each pixel.
US6002385A (en) * 1994-03-11 1999-12-14 Canon Kabushiki Kaisha Computer display system controller

Also Published As

Publication number Publication date
FR2608300B1 (en) 1989-03-31
JPS63163396A (en) 1988-07-06
EP0274942A3 (en) 1988-07-27
DE3777606D1 (en) 1992-04-23
EP0274942B1 (en) 1992-03-18
FR2608300A1 (en) 1988-06-17
US4859997A (en) 1989-08-22

Similar Documents

Publication Publication Date Title
EP0274942B1 (en) Flat panel matrix visualisation system with protected display of primary data for exploitation
CN101432789B (en) Display, instrument panel, optical system and optical instrument
US8891032B2 (en) Multi-view display
EP0625861B1 (en) Spatial light modulator and directional display
US7573491B2 (en) Method for formatting images for angle-specific viewing in a scanning aperture display device
EP1887807A1 (en) High resolution 2D/3D switchable display apparatus
MXPA01005923A (en) Image display system.
CN101064077B (en) Electro optical device and electronic apparatus equipped with the same
EP2555108B1 (en) Smart-dual display system
EP2174315B1 (en) Integrated method of detecting an image defect in a liquid crystal screen
KR20010041711A (en) Liquid crystal display with active matrix
CN101551984A (en) Time division multiple visual display device and time division multiple visual display method
KR100362957B1 (en) Display device and display system
WO2005096261A1 (en) Device for detecting a fixed image on a liquid crystal display screen
EP0976122B1 (en) Matrix display addressing device
FR2843646A1 (en) Visual display for aircraft cockpit instrument display, has small number of large LCD screens with two independent display areas to reduce chance of failure of one set of screens
FR2989503A1 (en) DEVICE FOR DISPLAY IN THE INTERIOR OF AN AIRCRAFT
FR2499276A1 (en) MATRIX DISPLAY DEVICE HAVING SEVERAL ELECTRODE GAMES AND ITS CONTROL METHOD
JPH1195240A (en) Spatial optical modulator and display device
CN101739912A (en) Display
KR101015458B1 (en) Electro-optical transducer and jelly layer therefor, method for producing a jelly layer and a compound for carrying out said method
FR3087582A1 (en) DAY AND NIGHT DISPLAY DEVICE
EP0178219A1 (en) Synthetic video images processing method for real time visualization, and with high density information, and device using such a method
EP0472463B1 (en) Method for displaying images on a matrix screen and system for carrying out this method
US4812019A (en) Method for producing the first differential of a two-dimensional image and optical structural element for performing the method

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE GB IT

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE GB IT

17P Request for examination filed

Effective date: 19881222

RAP3 Party data changed (applicant data changed or rights of an application transferred)

Owner name: THOMSON-CSF

17Q First examination report despatched

Effective date: 19910219

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE GB IT

ITF It: translation for a ep patent filed

Owner name: JACOBACCI & PERANI S.P.A.

REF Corresponds to:

Ref document number: 3777606

Country of ref document: DE

Date of ref document: 19920423

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19981118

Year of fee payment: 12

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19991211

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19991211

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20051209

Year of fee payment: 19

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20051211

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070703