EP0247118A1 - Interface circuit. - Google Patents
Interface circuit.Info
- Publication number
- EP0247118A1 EP0247118A1 EP86906882A EP86906882A EP0247118A1 EP 0247118 A1 EP0247118 A1 EP 0247118A1 EP 86906882 A EP86906882 A EP 86906882A EP 86906882 A EP86906882 A EP 86906882A EP 0247118 A1 EP0247118 A1 EP 0247118A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- analogue
- digital
- input
- loop
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/54—Circuits using the same frequency for two directions of communication
- H04B1/58—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
- H04B1/586—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa using an electronic circuit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/005—Interface circuits for subscriber lines
Definitions
- the invention relates to an interface circuit for coding analogue signals for digital transmission and decoding digital signals for analogue transmission.
- the interface circuit is of the type comprising a processing unit, an analogue port having a pair of terminals for connection to an analogue loop, a digital output port and a digital input port, said processing unit including an input path between the digital input port and the analogue port arranged to convert digital input signls to analogue output signals, an output path between the analogue port and the digital output port arranged to convert analogue input signals to digital output signals and a cross-over path for supplying digital signals derived from analogue input signals to the input path wherein the processing unit is arranged to synthesise a component of a terminating impedance across the analogue terminals.
- An object of the present invention is to provide an interface circuit of the aforesaid type providing a plurality of terminating impedances while providing a satisfactory frequency response.
- an interface circuit of the aforesaid type characterised by a transmission path having variable resistance electrically connected across the analogue ports and means for varying both the resistance of the transmission path and characteristics of the processing unit to change the value of the impedance across the terminals of the analogue port.
- the characteristics of the processing unit are determined by a single variable (K) and the resistance of the transmission path is also varied in relation to the value of said variable.
- the transfer function of the digital filter has realisable negative delay and may be implemented as a finite impulse response digital filter.
- a digital scaling means having a numerical value equal to the resistive transmission path is in parallel with the finite impulse response filter.
- the interface circuit may be employed in a full duplex transmission system.
- a transmission system comprising an analogue loop, means for coding analogue signals from said loop to provide a digital output, means for decoding a digital input to supply analogue signals to said loop, and a digital filter for supplying a portion of the digital input to synthesise a terminating impedance for the analogue loop: characterised by a variable resistive transmission path terminating the analogue loop, and means for varying the resistance of said transmission path and for varying characteristics of the digital filter to change the value of the synthesised impedance.
- variable resistance is a variable gain amplifier.
- Figure 1 shows a schematic representation of an improved interface circuit
- Figure 2 to 12 show the steps taken from an ideal system to a working embodiment. - -
- An interface circuit 10 is shown in Figure 1, fabricated as an integrated circuit, including a processing unit 11.
- the circuit 10 also includes an analogue port having a pair of terminals 12 which are connected to an analogue loop 14. Analogue signals are received from the loop 14 and coded into digital signals which are in turn supplied to a digital output port 15. Similarly digital input signals supplied to a digital input port 16 are decoded and supplied to the analogue port.
- a cross-over path 19 supplies digital signals derived from an analogue input signal to the output path.
- the purpose of this feedback loop is to synthesise the imaginary component of the terminating impedance Zt for the analogue line.
- difference amplifier 20 has input terminals connected across the analogue terminals 12 and provides an input voltage V.
- An analogue output signal is in the form of current generated by a transdulance amplifier 21 in response to an output voltage identified as I.
- the real component of the terminating impedance Zt is provided by a resistive transmission path 22 which provides a feedback path between the input V and the output I.
- the resistance of path 22 is controlled by a digital signal from the processing unit 11 and the circuit 10 is provided with means for varying both the resistance of the transmission path 22 and characteristics of the processing unit 11 to implement changes to the desired terminating impedance seen across the terminals of the analogue port.
- An ideal interface circuit in which a terminating impedance is synthesised is shown is Figure 2.
- the analogue to digital and digital to analogue converters are not present because they are assumed ideal and have a transfer function of 1.
- the output signal Tx is supplied to an adder 50 via an inverter 51.
- the adder 50 also receives the input signal Rx and supplies an output to a sealer 52.
- Sealer 52 has a transfer function of k/ZT - where Zt is the terminating impedance.
- the converters introduce delay and the aforesaid converters have transfer functions of Z "n and Z " * 11 .
- the configuration of Figure 2 would not respond quickly enough and would therefore be unstable.
- Figure 1 provides a resistive path on the analogue side of the converters while retaining the overall transfer function thus ensuring that the required frequency response is retained without adding compensating filters.
- K/R be the zero delay component of K/Zt. The other component is then
- K/Zt - K/R K(R-Zt)/RZt and the resulting transfer alogorithm is shown in Figure 3.
- the sealer 52 has been divided into two sealers 53 and 54 the outputs from which are combined by an adder 55.
- K/R block 56 is moved to the other side of the inverter 51 so that it becomes -K/R - Figure 5.
- the delays due to the converters 14 and 16 are assumed to have a transfer function of Z and are
- Figure 10 a double delay and two negative delays are added which may be manipulated as shown in Figure 11.
- the double negative delay Z is combined with the K(R-Zt)/RZt block 54 if Z "1 represents a sufficiently small delay.
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Networks Using Active Elements (AREA)
- Interface Circuits In Exchanges (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Circuit d'interface analogique/numérique dans lequel une impédance terminale analogique est partiellement synthétisée en appliquant un signal numérique de sortie (T) à une entrée numérique (R) via un filtre numérique (17). Un chemin de transmission résistif variable est relié entre les bords analogiques, la résistance du chemin pouvant être modifiée ainsi que les caractéristiques du filtre numérique afin de simuler toute impédance terminale requise. Cette structure facilite la modification de Zt, tout en maintenant la réponse en fréquence requise et la stabilité.An analog / digital interface circuit in which an analog terminal impedance is partially synthesized by applying a digital output signal (T) to a digital input (R) through a digital filter (17). A variable resistive transmission path is connected between the analog edges, where the resistance of the path can be changed as well as the characteristics of the digital filter to simulate any terminal impedance required. This structure facilitates modification of Zt, while maintaining the required frequency response and stability.
Description
A23189/0181S
INTERFACE CIRCUIT
The invention relates to an interface circuit for coding analogue signals for digital transmission and decoding digital signals for analogue transmission.
The interface circuit is of the type comprising a processing unit, an analogue port having a pair of terminals for connection to an analogue loop, a digital output port and a digital input port, said processing unit including an input path between the digital input port and the analogue port arranged to convert digital input signls to analogue output signals, an output path between the analogue port and the digital output port arranged to convert analogue input signals to digital output signals and a cross-over path for supplying digital signals derived from analogue input signals to the input path wherein the processing unit is arranged to synthesise a component of a terminating impedance across the analogue terminals.
An interface circuit of the aforesaid type is shown in United Kingdom Patent Application 2 086 196 which discloses a circuit for coding an analogue signal from a telephone line. The resulting digital signal is processing in combination with an incoming digital signal by means of a digital filter. The output from this filter is then decoded and supplied to the telephone line via a transconductance amplifier. A problem with this circuit is that it may become unstable due to the delay introduced by the analogue to digital converter, the digital filter and the digital to analogue converter.
Another interface circuit is disclosed in the Ericsson Review of 1983, No 3, page 192 in which a digital filter synthesises a terminating impedance in combination with a
resistor placed across the analogue terminals. This arrangement is suitable for providing a fixed terminating impedance but does not solve the problem of providing a variable terminating impedance particularly if a range of values are desired for which both the real and imaginary components are to be changed. A problem is that in attempting to provide stability for such a circuit it is difficult to maintain the necessary frequency response for each of the available terminating impedances. Thus even if a relatively small number of terminating impedances are available, complex filters must be added to maintain the necessary frequency response.
An object of the present invention is to provide an interface circuit of the aforesaid type providing a plurality of terminating impedances while providing a satisfactory frequency response.
According to the present invention there is provided an interface circuit of the aforesaid type characterised by a transmission path having variable resistance electrically connected across the analogue ports and means for varying both the resistance of the transmission path and characteristics of the processing unit to change the value of the impedance across the terminals of the analogue port.
In a preferred embodiment the characteristics of the processing unit are determined by a single variable (K) and the resistance of the transmission path is also varied in relation to the value of said variable. The advantage of this embodiment is that a whole range of terminating impedances may be provided which is only restricted by the resolution of the digital circuitry.
Preferably the transfer function of the digital filter has realisable negative delay and may be implemented as a finite impulse response digital filter. Preferably a digital scaling means having a numerical value equal to the
resistive transmission path is in parallel with the finite impulse response filter.
The interface circuit may be employed in a full duplex transmission system. According to a second aspect of the present invention there is provided a transmission system comprising an analogue loop, means for coding analogue signals from said loop to provide a digital output, means for decoding a digital input to supply analogue signals to said loop, and a digital filter for supplying a portion of the digital input to synthesise a terminating impedance for the analogue loop: characterised by a variable resistive transmission path terminating the analogue loop, and means for varying the resistance of said transmission path and for varying characteristics of the digital filter to change the value of the synthesised impedance.
Preferably the variable resistance is a variable gain amplifier.
According to a third aspect of the present invention there is provided a method of interfacing a subscribers analogue loop to a digital input line and a digital output line wherein an analogue impedance is simulated by Supplying a proportion of the digital output to the digital input via a digital filter: characterised by terminating the analogue loop with a variable resistance, and varying said resistance and varying the characteristics of the digital filter to change the value of the simulated impedance.
The invention will now be described by way of example only with reference to the accompanying drawings of which: Figure 1 shows a schematic representation of an improved interface circuit, and
Figure 2 to 12 show the steps taken from an ideal system to a working embodiment.
- -
An interface circuit 10 is shown in Figure 1, fabricated as an integrated circuit, including a processing unit 11. The circuit 10 also includes an analogue port having a pair of terminals 12 which are connected to an analogue loop 14. Analogue signals are received from the loop 14 and coded into digital signals which are in turn supplied to a digital output port 15. Similarly digital input signals supplied to a digital input port 16 are decoded and supplied to the analogue port.
In addition to an output path 17, supplying an analogue signal to the analogue port in response to digital input signals, and an input path 18, supplying a digital output signal to the digital output port 15 in response to analogue input signals, a cross-over path 19 supplies digital signals derived from an analogue input signal to the output path. The purpose of this feedback loop is to synthesise the imaginary component of the terminating impedance Zt for the analogue line. difference amplifier 20 has input terminals connected across the analogue terminals 12 and provides an input voltage V. An analogue output signal is in the form of current generated by a transdulance amplifier 21 in response to an output voltage identified as I. The real component of the terminating impedance Zt is provided by a resistive transmission path 22 which provides a feedback path between the input V and the output I. The resistance of path 22 is controlled by a digital signal from the processing unit 11 and the circuit 10 is provided with means for varying both the resistance of the transmission path 22 and characteristics of the processing unit 11 to implement changes to the desired terminating impedance seen across the terminals of the analogue port.
An ideal interface circuit in which a terminating impedance is synthesised is shown is Figure 2. The analogue to digital and digital to analogue converters are not present because they are assumed ideal and have a transfer function of 1. The output signal Tx is supplied to an adder 50 via an inverter 51. The adder 50 also receives the input signal Rx and supplies an output to a sealer 52. Sealer 52 has a transfer function of k/ZT - where Zt is the terminating impedance. However in practice the converters introduce delay and the aforesaid converters have transfer functions of Z"n and Z"*11. The configuration of Figure 2 would not respond quickly enough and would therefore be unstable.
The arrangement of Figure 1 provides a resistive path on the analogue side of the converters while retaining the overall transfer function thus ensuring that the required frequency response is retained without adding compensating filters.
The detailed processing algorithm for the circuit shown in Figure 1 may be derived from the ideal arrangement of Figure 2 as follows:-
1. Let K/R be the zero delay component of K/Zt. The other component is then
K/Zt - K/R = K(R-Zt)/RZt and the resulting transfer alogorithm is shown in Figure 3. The sealer 52 has been divided into two sealers 53 and 54 the outputs from which are combined by an adder 55.
2. The K/R block 53' is moved to the other side of the adder thus necessitating another K/R block 56 -
Figure 4.
3. The input of K/R block 56 is moved to the other side of the inverter 51 so that it becomes -K/R - Figure 5.
_.6 _
4. The output from sealer 53 is removed from adder 55 by using another adder 57 - Figure 6.
5. The delays due to the converters 14 and 16 are assumed to have a transfer function of Z and are
5 inserted to the left of the -K/R block 56 along with negative delays 58, 59 having a transfer function of Z.
6. The negative delays are moved in order to incorporate them into blocks having non zero-delay components as shown in Figures 8 and then 9. In
10 " Figure 10 a double delay and two negative delays are added which may be manipulated as shown in Figure 11.
7. In Figure 11 delays Dl and D2 which are in series with the digital input and the digital output are ignored.
2
-3 8. The double negative delay Z is combined with the K(R-Zt)/RZt block 54 if Z"1 represents a sufficiently small delay.
A generalised version is shown in Figure 12 and if n+m equal 3 then K(R-Zt)/R-Zt can be realised by a finite
20 impulse respone filter having the following co-efficients:
C1=C2=C3 = 0
C4 = -0.65625
C5 = +0.296875
C6 = -0.078125
-0 C7 = +0.234375
C8 = -0.265625
C9 = +0.046875
The structure of Figure 1 does not require extra filters in order to achieve the required frequency 30 response, the transfer functions of the block only require one variable to be changed (K) in order to change Zt while ensuring that the circuit has the required frequency response and remains stable.
Claims
1. An interface circuit comprising a processing unit, an analogue port having a pair of terminals for connection to an analogue loop, a digital output port and a digital input port, said processing unit including an input path between the digital input port and the analogue port arranged to convert digital input signls to analogue output signals, an output path between the analogue port and the digital output port arranged to convert analogue input signals to digital output signals and a cross-over path for supplying digital signals derived from analogue input signals to the input path wherein the processing unit is arranged to synthesise a component of a terminating impedance across the analogue terminals: characterised by a transmission path having variable resistance electrically connected across the analogue ports and means for varying both the resistance of the transmission path and characteristics of the processing unit to change the value of the impedance across the terminals of the analogue port.
2. An interface circuit according to claim 1 in which the characteristics of the processing unit are determined by a single variable (K) and the resistance of the transmission path is also varied in relation to the value of said variable.
3. An interface circuit according to claim 2 in which the resistance of the transmission path varies linearly with the variable value.
4. An interface circuit according to any of claims 1 to 3 in which the digital filter has realisable negative delay.
5. An interface circuit according to any of claims 1 to 4 in which the digital filter includes a finite impulse response filter. — o —
6. An interface circuit according to claim 5 in which a digital scaling means having a numerical value equal to the resistance of said transmission path is in parallel with the finite impulse response filter.
7. A transmission system comprising an analogue loop, means for coding analogue signals from said loop to provide a digital output, means for decoding a digital input to supply analogue signals to said loop, a digital filter for supplying a portion of the digital output to the digital input to synthesise a terminating impedance for the analogue loop : characterised by a variable resistive transmission path terminating the analogue loop and means for varying the resistance of said transmission path and for varying characteristics of the digital filter to change the value of the synthesised impedance.
8. A method of interfacing a subscribers analogue loop to a digital input line and a digital output line wherein an analogue impedance is simulated by supplying a proportion of the digital output to the digital input via a digital filter : characterised by terminating the analogue loop with a variable resistance, varying said resistance and varying the characteristics of the digital filter to change the value of the simulated impedance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AT86906882T ATE56113T1 (en) | 1985-11-22 | 1986-11-19 | INTERFACE CIRCUIT. |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8528843 | 1985-11-22 | ||
| GB858528843A GB8528843D0 (en) | 1985-11-22 | 1985-11-22 | Codec |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0247118A1 true EP0247118A1 (en) | 1987-12-02 |
| EP0247118B1 EP0247118B1 (en) | 1990-08-29 |
Family
ID=10588644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP86906882A Expired EP0247118B1 (en) | 1985-11-22 | 1986-11-19 | Interface circuit |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4894864A (en) |
| EP (1) | EP0247118B1 (en) |
| JP (1) | JPS63501465A (en) |
| CA (1) | CA1267727A (en) |
| DE (1) | DE3673816D1 (en) |
| GB (1) | GB8528843D0 (en) |
| WO (1) | WO1987003440A1 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE457923B (en) * | 1987-06-15 | 1989-02-06 | Ellemtel Utvecklings Ab | DEVICE TO ACHIEVE A CONTROLLABLE LINE CUT IMPEDANCE |
| JP2999214B2 (en) * | 1990-03-02 | 2000-01-17 | 株式会社東芝 | Transmission input / output circuit |
| DE4008450A1 (en) * | 1990-03-16 | 1991-09-19 | Telefonbau & Normalzeit Gmbh | CIRCUIT ARRANGEMENT FOR SIGNAL AND INFORMATION CONVERSION BETWEEN ANALOG-OPERATED CONNECTION LINES AND DIGITALLY-OPERATED CONNECTING BODIES IN COMMUNICATION SWITCHING SYSTEMS |
| IT1259009B (en) * | 1992-07-24 | 1996-03-11 | Italtel Telematica | METHOD AND DEVICE FOR THE ADAPTATION OF USER TERMINATION IMPEDANCES AND USER ATTACK TO THE CHARACTERISTIC IMPEDANCE OF THE USER TELEPHONE LINE |
| MY110609A (en) * | 1993-06-30 | 1998-08-29 | Harris Corp | Carbon microphone interface for a modem |
| ATE187029T1 (en) * | 1993-09-02 | 1999-12-15 | Siemens Ag | CIRCUIT ARRANGEMENT FOR GENERATING A VARIABLE LINE TERMINATION IMPEDANCE |
| US6041114A (en) | 1997-03-27 | 2000-03-21 | Active Voice Corporation | Telecommute server |
| US6198817B1 (en) | 1998-01-23 | 2001-03-06 | International Business Machines Corporation | Communication interface having combined shaping of receive response and synthesized matching terminating impedances for different frequency bands and a design method therefor |
| US6181792B1 (en) | 1998-01-23 | 2001-01-30 | International Business Machines Corporation | Communication interface having synthesized matching impedances for different frequency bands and a design method therefor |
| US6553118B1 (en) * | 1999-05-11 | 2003-04-22 | Agere Systems Inc. | Method and apparatus for calculating DC offset in a digital gyrator |
| US6665403B1 (en) * | 1999-05-11 | 2003-12-16 | Agere Systems Inc. | Digital gyrator |
| US6615027B1 (en) * | 2000-01-21 | 2003-09-02 | Qualcomm Incorporated | Method and circuit for providing interface signals between integrated circuits |
| US6573729B1 (en) | 2000-08-28 | 2003-06-03 | 3Com Corporation | Systems and methods for impedance synthesis |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4270027A (en) * | 1979-11-28 | 1981-05-26 | International Telephone And Telegraph Corporation | Telephone subscriber line unit with sigma-delta digital to analog converter |
| JPS5725731A (en) * | 1980-07-22 | 1982-02-10 | Iwatsu Electric Co Ltd | Hybrid circuit |
| US4351060A (en) * | 1980-10-23 | 1982-09-21 | International Telephone And Telegraph Corporation | Automatic, digitally synthesized matching line terminating impedance |
| DE3586696T2 (en) * | 1984-05-30 | 1993-04-01 | Hitachi Ltd | PCM CODER / DECODER WITH TWO-WIRE / FOUR-WIRE CONVERSION. |
| US4629829A (en) * | 1984-12-14 | 1986-12-16 | Motorola, Inc. | Full duplex speakerphone for radio and landline telephones |
-
1985
- 1985-11-22 GB GB858528843A patent/GB8528843D0/en active Pending
-
1986
- 1986-11-19 DE DE8686906882T patent/DE3673816D1/en not_active Revoked
- 1986-11-19 WO PCT/GB1986/000707 patent/WO1987003440A1/en not_active Application Discontinuation
- 1986-11-19 EP EP86906882A patent/EP0247118B1/en not_active Expired
- 1986-11-19 JP JP61506108A patent/JPS63501465A/en active Pending
- 1986-11-19 US US07/095,573 patent/US4894864A/en not_active Expired - Fee Related
- 1986-11-21 CA CA000523506A patent/CA1267727A/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| See references of WO8703440A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0247118B1 (en) | 1990-08-29 |
| CA1267727A (en) | 1990-04-10 |
| US4894864A (en) | 1990-01-16 |
| WO1987003440A1 (en) | 1987-06-04 |
| JPS63501465A (en) | 1988-06-02 |
| DE3673816D1 (en) | 1990-10-04 |
| GB8528843D0 (en) | 1985-12-24 |
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