EP0232253A1 - Systemes d'inductance - Google Patents

Systemes d'inductance

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Publication number
EP0232253A1
EP0232253A1 EP85903939A EP85903939A EP0232253A1 EP 0232253 A1 EP0232253 A1 EP 0232253A1 EP 85903939 A EP85903939 A EP 85903939A EP 85903939 A EP85903939 A EP 85903939A EP 0232253 A1 EP0232253 A1 EP 0232253A1
Authority
EP
European Patent Office
Prior art keywords
signal
signals
output
frequency
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85903939A
Other languages
German (de)
English (en)
Other versions
EP0232253A4 (en
Inventor
Nicholas F. D'antonio
Ronald W. D'antonio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Antonio Ronald W D
Original Assignee
Antonio Ronald W D
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Antonio Ronald W D filed Critical Antonio Ronald W D
Publication of EP0232253A1 publication Critical patent/EP0232253A1/fr
Publication of EP0232253A4 publication Critical patent/EP0232253A4/en
Withdrawn legal-status Critical Current

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01DMEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
    • G01D5/14Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
    • G01D5/20Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
    • G01D5/204Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature by influencing the mutual induction between two or more coils
    • G01D5/2053Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature by influencing the mutual induction between two or more coils by a movable non-ferromagnetic conductive element

Definitions

  • the present invention concerns apparatus and methods employing inductance devices having a variable reluctance in their magnetic fields for converting a parameter, such as relative motion, force, or pressure, into an electrical signal for measurement.
  • the inven ⁇ tion further involves the generation of signals of varying frequency according to some parameter, and to the processing of such signals for some useful purpose.
  • Transducers employing variable reluctances and inductances for detecting motion are known. These are referred to by such terms as proximity sensors and magneto sensors, and examples of these devices include the linear variable differential transformer (“LVDT”) eddy current killed oscillator (“ECKO”) and eddy cur ⁇ rent oscillator level detector (“ECOLD”)-
  • LVDT linear variable differential transformer
  • ECKO eddy current killed oscillator
  • ECOLD eddy cur ⁇ rent oscillator level detector
  • a change in diaphragm position in response to a force applied to it changes the gaps between the cores and the diaphragm resulting in changes in the inductances of the coils.
  • the ratio of the changes in the inductances of the colls is mea ⁇ sured through an alternating current bridge.
  • the alternating current bridge signal In order to obtain a direct current indication of the diaphragm motion, the alternating current bridge signal must be demodulated.
  • U.S. Patent No. 4,310,807 discloses a reluctance proximity sensor having a reactive sensing unit in an L/C tuning circuit of an oscillator, which is connected ahead of an operational amplifier. A shortcoming of the latter 5 sensor is the requirement of a separate squaring cir ⁇ cuit for generating a square wave frequency response.
  • Variable frequency oscillators are known which can be used with variable capacitive transducers to generate output signals whose frequencies are a func- 10 tion of the parameter being sensed by the transducer. For example, see U.S. Patent No. 4,310,806 dated January 12, 1982.
  • Another object is to provide an inexpensive
  • a related object is to provide such a transducer which is stable under various temperature conditions, easy to use with other circuit components, and which is gener-
  • Still another object of the present invention is the provision of an oscillator for generating sig ⁇ nals whose frequencies vary according to characteris ⁇ tics of a transducer in the oscillator network, wherein the oscillator is effective and efficient and relative ⁇ ly free of the shortcomings of the prior art as dis ⁇ cussed previously.
  • a further object of the invention is the pro ⁇ vision of an effective and efficient processor for processing signals from the signal -generators which generate variable frequency signals, such as those described above, to produce intelligible or otherwise usable output signals.
  • a processor can be con ⁇ structed to be compact and rugged, and capable of avoiding shortcomings of the prior art as -discussed above.
  • Another object is to provide an efficient digital to analog converter.
  • an inductor having a variable reluctance that affects its magnetic field may form part of a self-excited oscillator gen ⁇ erating an analog or digital alternating current signal having an inductance-dependent frequency.
  • the result ⁇ ing inductance is varied by changing the reluctance in the magnetic field created by the inductor. Changes in inductance and, therefore, the magnitude of the move ⁇ ment of the transducer components because of the applied force or pressure are conveniently determined by measuring the change in the frequency of the oscil ⁇ lator signal.
  • a reluctance means for varying the reluctance of the magnetic field of the inductor may be a shield receiving the inductor or a solid body proximate to, and movable relative to, the inductor.
  • the reluctance means is made of a mate ⁇ rial that modifies the magnetic field by providing a reluctance different from that of air.
  • Either the reluctance means or the Inductor may be mounted on a movable base such as a diaphragm that can be displaced in response to a force applied to it.
  • a change in the nature of the magnetic path of the inductor leads to a change in inductance and indicates the relative motion of the reluctance means with respect to the inductor.
  • eddy currents can be responsible for changes in effective inductance by providing a variable obstacle ' to the field.
  • An oscillator according to the inven ⁇ tion produces a signal with an inductance-sensitive frequency, according to changes in a transducer in ⁇ cluded in the oscillator network, and when a transducer as described above is so employed, relative motion of the transducer elements results in changes in frequen ⁇ cy. Both the direction and magnitude of frequency changes may be conveniently measured in novel digital processor circuitry readily adapted to integrated cir- cuitry.
  • That novel circuitry measures the time re ⁇ quired by an oscillator having an inductance-sensitive frequency to generate a fixed number of cycles in com ⁇ parison to time required to generate that number of cycles when no stimulus is applied to the transducer.
  • a digital to analog converter according to an embodi ⁇ ment of the invention receives digital signals like the foregoing, and integrates them to produce output sig ⁇ nals having non-unitary slopes and lengths which vary according to the duration of the digital signals.
  • Figure 1 is a side view of an embodiment of a reluctance transducer according to the Invention.
  • Figure 2 is a graph of the electrical response of an embodiment of the invention built according to Figure 1.
  • Figure 3 is a graph of the electrical response of an embodiment of the invention built according to Figure 1.
  • Figure 4 is a graph of the electrical response ' of another embodiment of the invention built according to Figure 1.
  • Figure 5 is a perspective view of an embodi- ment of a reluctance transducer according to the inven ⁇ tion.
  • Figure 6 is a perspective view of still an ⁇ other embodiment of a reluctance transducer according to the invention.
  • Figure 7 is a side view of a fourth embodiment of a reluctance transducer according to the invention.
  • Figures 8-13 are schematic diagrams of embodi ⁇ ments of signal generators according to the invention.
  • Figure 14 is a schematic diagram of signal processing circuitry according to the invention for processing a signal generated In a variable inductance signal generator.
  • Figure 15 is a timing diagram illustrating the operation of the circuitry shown in Figure 14.
  • Figure 16 is a schematic diagram of other signal processing circuitry according to the invention for processing a signal generated in a variable induc ⁇ tance signal generator.
  • Figure 17 is a timing diagram illustrating the operation of the circuitry shown in Figure 16.
  • Figure 18 is a schematic diagram of circuitry for making an analog to digital converter In accordance with the invention.
  • Transducer 1 includes a core ⁇ , about which a coil ⁇ is wound.
  • core 3 and coil ⁇ are rigidly mounted with respect to a flexible diaphragm 7 on which a hollow cylinder 9 is securely mounted.
  • Core 3 is preferably made of a ferromagnetic material -to increase the inductance of coil ⁇ .
  • Hollow cylinder 9 can be a non-ferrous metallic or ferromagnetic material whose relative position will variably alter the magnetic field around the coil, allowing for either an eddy current or altered magnetization effect.
  • core 3 and coil ⁇ protrude partially into hollow cylinder ⁇ .
  • diaphragm ⁇ In response to forces applied to the diaphragm (in the horizontal direction according to the drawing of Figure 1) , diaphragm ⁇ flexes with the result that the coil is inserted further into or with ⁇ drawn from cylinder 9- When current flows through coil 5, a corresponding magnetic field is created around the coil. Part of that field is intercepted by cylinder 9 and is modified by the cylinder. As diaphragm 7 flexes, more or less of the magnetic field of coil 5 is intercepted, resulting in a change with respect to time of the current flowing through coil ⁇ . This time rate of change of current and its corresponding field and inductive characteristics therein, serves to modify the inherent inductance of coil ⁇ . The inductance change is measured by sensing the change in the current flow ⁇ ing through coil ⁇ . That is, cylinder 9 provides a variable reluctance means for changing the reluctance to the magnetic field in the region about coil ⁇ .
  • the shape of coil 5 In Figure 1 is merely schematic.
  • the coil need not be helical and could even be planar.
  • Various coil config ⁇ urations and the choice of core and shield materials affect the basic inductance achievable and the magni ⁇ amplitude of the changes in inductance, i.e. the dynamic range and sensitivity of the transducer resulting from the relative motion of the elements of the transducer.
  • the response of- the transducer is lin ⁇ ear.
  • FIG. 1 A number of examples of the embodiment of Figure 1 have been constructed and their.electrlcal characteristics measured.
  • Core 3 w s formed from a ferromagnetic material and coil ⁇ wound around it.
  • cylinder.9 has a close fit over coil ⁇ but is relatively free from physical contact in order to reduce the friction between them to a minimum.
  • a plastic sleeve was placed over the coil to protect it against damage and to reduce that friction.
  • gener ⁇ al a closer fit between the cylinder and coil yields a greater dynamic range but a greater risk of friction; a looser fit yields a smaller dynamic range and a lower risk of friction. It was desired to construct a small, low cost, lightweight transducer so cylinder was constructed of aluminum in the measured examples.
  • edge of cylinder 9 intercept only the magnetic lines created by coil 5 that are nearly parallel to the longitudinal axis of core 3 « In - • terms of the dimensions of the measured examples, the edge of cylinder 9 should extend over and cover a por ⁇ tion of the coll beyond the end of core 3 during opera ⁇ tion to assure operation in the linear range.
  • diaphragm 7 was initially a convo ⁇ luted rubber diaphragm having a central planar surface with concentric corrugations between it and the outer support structure.
  • this type of diaphragm was found subject to drift, i.e. gradual position changes or "creep" under the influence of a steady state pres ⁇ sure or force.
  • the cylinder had an inside diameter of 4.2 mm and an outside diameter of.6.25 mm, meaning its wall thickness was approximately 1 mm.
  • a large linear range of frequency change as a function of de ⁇ flection was measured; e.g. the linear frequency re- sponse over a deflection range of about 3 mm was over 300 kHz.
  • FIG. 5 Another embodiment 11 of a reluctance trans ⁇ ducer is shown in Figure 5.
  • a coil 13 is wound around a tubular structure * 15 which has an air inner core 17.
  • the reluctance shield includes a tubular portion 19 which is concentric to a rod 21. While these elements are shown separated in Figure 5 for clarity, in use core 15 is received by tubular shield 19 and rod 21 is received by air core 17. Both tube 19 and rod 21 ' are mounted on a flexible diaphragm 23 to which the forces to be measured are applied.
  • this embodiment yields a lower inductance because of air core 17, but a greater dynamic range because a large portion of the total magnetic field produced by coil 13 is influenced by the incremental movement of the shield and tube over and into the coil.
  • a very useful alternative to the simultaneous movement of tube 19 and rod 21 over and into the coil, is to securely mount tube 19 around the outer portion of coil 13.
  • tube 19 will protect the coil against outside disturbances such as magnetic or electro-magnetic fields or the otion " of other metallic parts in the vicinity of the measurement.
  • Shield 19 can be a ferromagnetic material for best results in this approach.
  • FIG. 6 Still another embodiment 31 of a reluctance transducer is shown in Figure 6.
  • a coil 33 is wound about a core 35.
  • a magnet 37 having a con- cave face 39 opposite coil 33 is mounted on a flexible diaphragm 41.
  • a large dynamic range is achieved because of the large magnetic field produced by magnet 37. It is not necessary that face 39 be concave, but that shape extends the linear re- sponse range of this embodiment because the concave face 39 is conformal to the magnetic lines of force leaving the top of core 35.
  • An embodiment 51 of a transducer shown in Figure 7 permits measurement of a force regardless of its direction.
  • the force is applied to a deflectable beam 53 on one end of which a magnet 55 is mounted.
  • magnet 55 is disposed opposite a coil 57 wound around a core 59. Any o f-axis motion between coil 57 and magnet 55 results in a disturbance of the coil's magnetic field which may be measured as a change in the time dependent current flowing through the coil, i.e., a change in inductance.
  • the beam could be made to move four units of distance, while the same one unit of force in the y-direction could be made to move the beam only one unit of distance.
  • Any number of force- distance combinations could be implemented for any number of beams alone or In combination (parallel, for example), could be made.
  • 5 Networks have been devised for generating variable frequency signals according to changes in inductance, and these can be used for measuring the changes in inductance in a reluctance transducer.
  • Figure 8 schematically depicts a simple circuit in
  • a coil 71* which may be the coil of a reluctance transducer, is con-
  • Inverter 73 may be an integrated circuit Schmitt trigger such as a CD 40106.
  • the input terminal of inverter 73 is connected to ground through a vari ⁇ able resistor 75 « When the signal at the input termi-
  • inverter 73 20 nal of inverter 73 is in its low state, the signal at the output terminal is in its high state, causing an increasing current to flow through inductor 71 and the magnetic field about the inductor to grow.
  • the rate of growth of the field is determined by the time constant
  • Resistance 75 allows adjustment o the base, i.e. quiescent, frequency of the oscillator by changing
  • the output terminal of an inverter 81 is connected to the Input terminal of an Inverter 83 and to one terminal of an inductor 85-
  • the other terminal of Inductor 85 is 0 connected through a resistance 87 to the input terminal of inverter 81 and through a variable resistance 89 to the output terminal of inverter 83-
  • Inductor 85 may be the coil of a reluctance transducer.
  • resistance 87 provides a measure of stability against temperature and power supply voltage varia ⁇ tions.
  • variable resistor 89 adjusts the frequency of the output signal by adjusting the inductive time constant of the net ⁇ work.
  • Common, low power consumption, CMOS integrated circuit Schmitt trigger inverters such as the CD 40106 may be used In the sensing means embodiments shown in Figures 8 and 9.
  • a circuit element 101 may be either a comparator to produce a pulse train signal as shown or an operational amplifier to produce an analog, sinusoidal signal which is also shown.
  • the positive sense input terminal 103 of circuit 101 Is used to establish a switching threshold.
  • a voltage source 105 connected through the wiping contact of a potentiometer 107 to input terminal 103, is used to establish that threshold.
  • an Inductor 109 which may be a coil in a reluctance transducer, is connected from the output terminal of circuit 101 to its negative sense input terminal 111.
  • variable resistance 113 connected between ground and terminal 111 permits adjustment of the time related Input voltage characteristics to circuit 101.
  • circuit 101 When circuit 101 is a comparator, It acts like the inverter described above, switching the signal at its output terminal between high and low output states in response to voltage changes applied at negative sense input terminal 111 that cross the threshold es ⁇ tablished at positive sense input terminal 103.
  • circuit 101 When circuit 101 is an operational ampli ⁇ bomb, it responds to incremental changes in the input signal. As a result, the output signal Is sinusoidal. In the former case, resistance 113 varies the base frequency and In the latter, it has its greatest effect in varying the initial condition amplitude of the sinu ⁇ soidal signal.
  • circuit 101 is a comparator or opera ⁇ tional amplifier.
  • a comparator the frequency of the pulse train generated varies when the inductance of inductor 109 changes.
  • an operational amplifier the greatest variation is seen .in the amplitude of the output signal that varies in respons.e to the changes in inductance. While these changes may be detected by different circuitry, each of these sensing means em ⁇ bodiments generates a signal having a characteristic that varies in response to variations in the inductive time constant of feedback elements 109 and 113 *
  • FIG. 11 illustrates circuitry analogous to that of Figure 8, except NAND gate 121 is substituted for inverter 73 as both a control means and frequency generating means.
  • NAND gate 121 receives a control signal as schematically illustrated in Figure 11.
  • the other input terminal and the output terminal of NAND are connected with the circuit ele ⁇ ments as described in Figure 8 to form a variable- frequency oscillator. Only when the control signal is in its high state can the depicted circuitry operate to produce an oscillation signal at its output terminal. Thus a power savings is achieved by repeatedly pulsing gate 121 to operate the oscillator only Intermittent ⁇ ly.
  • the output frequency of this network is far more sensitive to supply voltage variations than that of Figure 12 described below; therefore, it can be used as a "battery condition indicator" by making periodic checks on the oscillator frequency and comparing it against the initial condition value.
  • Gate 121 may be a type CD 4093 quad Schmitt Trigger CMOS NAND gate.
  • FIG 12 a circuit analogous to that of Figure 9 is shown.
  • Inverter 81 Is replaced by a NAND gate 131, and an electronic switch 141 is connected in series with inductor 85 which together act as the control means described for Figure 11.
  • the output level of gate 131 is always high in the OFF mode of operation; thus, the OFF state of the inverter is always low which serves to avoid any uncertainty in the logic levels to be expected during lntermittant opera ⁇ tion.
  • Switch 141 may be a type CD 4066 and Its opening and closing in response to the application of the con ⁇ trol signal assures the absence of oscillation during the OFF cycle.
  • an electronic switch 151 which may be a type CD 4066, is again connected in series with inductor 109 of Figure 10 as a control means.
  • a control signal opening and closing the switch is applied to switch 151.
  • An open switch 151 prevents oscillation; a closed switch 151 permits oscillation.
  • Figure 14 shows a schematic embodiment of circuitry for detectin .variations in the frequency, -16-
  • a frequency generator supplies the signal in which frequency variation is to be detected.
  • the circuitry of Figure 9 is repeated as an embodiment of a frequency generator with inverters 201 and 203 connected in series, an inductor 205 connected between the common connection of the Inverters and through a resistor 207 to the input terminal of inverter 201.
  • a variable resistance 209 is connected between the output terminal of inverter 203 and through inductor 205 to the input terminal of inverter 203.
  • the output terminal of in- verter 203 Is designated as point A and the signal present at that point is designated as signal A for convenience of reference.
  • the variable frequency " oscillator shown in Figure 14 as generating signal A can be replaced by any of the oscillator embodiments shown in Figures 8, 10, 11, 12 or 13 or any another variable frequency oscillator embodiment.
  • a timing oscillator is constructed similarly, including inverters 211 and 213 connected in series.
  • the fixed terminals of a potentiometer 215 are respec ⁇ tively connected between the common connection of in ⁇ verters 211 and 213 and (a) in series through a re ⁇ sistor 217 to the input of inverter 211 and (b) through a capacitor 219 to the output terminal of inverter 213-
  • the wiping contact of potentiometer 215 Is connected to the terminal of capacitor 219 that is not connected to the output terminal of inverter 213-
  • the signal observed at the output terminal of inverter 213 Is designated as signal B.
  • a pulse train generator Identical to the timing oscillator just described is provided, but its components can be of different values to produce dif ⁇ ferent pulse widths and repetition rates.
  • That gen- erator includes inverters 221 and 223, a potentiometer 225, a feedback resistor 227 and a capacitor 229.
  • the output signal at the output of inverter 223 is desig ⁇ nated as signal C to aid description of the operation of the circuit.
  • the counting means comprises two four bit counters, 231 and 233, connected in series to form an eight bit counter.
  • the counters could each be one half of a CD 4520 binary type cir-» cuit.
  • Each four bit counter has a count input terminal C, an enable input terminal E,' a reset terminal R and four output bit lines.
  • Signal A is transmitted to terminal C of counter 231-
  • the highest count bit line of counter 231 is connected to the E terminal of counter 233-
  • the R terminals of each counter go to a reset line, RSI.
  • the C terminal of counter 233 is grounded and its highest count bit line serves as an output terminal Q ⁇ .
  • the output signal B of the timing oscillator including inverters 211 and 213 is connected to enable terminal E of counter 231-
  • counter 231 begins counting the pulses in signal A.
  • a high to low transition occurs at the highest bit line and so is transmitted to the enable terminal of counter 233 which, serving as a negative edge trigger, will count one unit.
  • the process is repeated until a count of 128 pulses Is reached where- upon the signal at terminal Q N goes high.
  • the Q N terminal of counter 233 is connected to an 8 bit counter driver, including two 4 bit counters 235 and 237 connected to each other as counters 231 and 233 are.
  • the enable terminal of counter 235 is connected to the Q pleasant terminal of counter 233 and the C terminal of counter 235 receives the signal designated as C and generated by the pulse train generator in ⁇ cluding inverters 221 and 223.
  • Counters 235 and 237 could each be half of a CD 4518 BCD (Binary coded decimal) type circuit.
  • a reset.line RS2 is connected to the reset terminals of counters 235 and 237-
  • the output bit lines of each of counters 235 and 237 are connected, respectively, to display drivers 239 and 241 which convert the BCD Information into the form neces- sary to drive a two digit visual display 243-
  • Drivers 239 and 241 each have a store terminal S, both of which are connected to a store line ST, and seven output terminals connected to display 243- Drivers 239 and 241 may each be a CD 4056 type circuit.
  • Figure 14 also includes in phantom lines a D- flip flop 245 having its C terminal connected to termi ⁇ nal Q N of counter 233 (which in this option is not connected to counter 235).
  • a type CD 4013 flip flop is suitable for this application.
  • the Q NN output terminal of flip flop 245 is connected to the enable terminal of counter 235- Reset terminal R of flip .flop 245 is connected to reset line RSI.
  • the purpose of flip flop 245 is to hold or freeze a high signal generated at the Q w terminal of counter 233, since that signal could assume Its low state in the embodiment after 256 pulses of Signal A; this would disable the 235, 237 counters causing an incorrect reading to occur.
  • FIG. 15 The operation of the circuit of Figure 14 is more clearly understood by reference to the timing diagram of Figure 15 where the top three time scales show the A and B signals and that at terminal Q.- when no stimulus Is applied, i.e. when the frequency of the frequency generator is in its initial condition state. If a reluctance transducer Is present in the frequency ⁇ generator A, that state would be a quiescent one when no force or pressure is being applied to the transducer elements.
  • the middle three time scales show the A and C signals and signal at terminal Q N when a positive sense stimulus Is applied.
  • the lower three time scales show the timing of the reset and store signals, RSI, RS2 and ST, respectively.
  • the timing means switches signal B to its high condition activating- the cycle counter 231, 232 to count the transitions in the pulses generated by the frequency generating means 201, 203.
  • the timing means is designed to switch signal B to its low state, ending the interval, on the positive transition of the 128th pulse, i.e. precisely when the Q signal goes high, if the frequency generating signal, signal A, is of the constant, quiescent frequency.
  • Pulses ST and RS2 follow. If a positive sense stimulus Is applied causing the frequency of the signal A to Increase, the Q w output goes high before the B signal goes low to disable the cycle counter and end the Interval. This condition is illustrated in the middle three time scales of Figure 15. In this situation, when the 128th pulse is reached and Q N goes high, the display driver counter 235, 237 is activated and begins counting the pulses in signal C. This counting con ⁇ tinues until the end of the interval when the B signal goes low. The number of pulses of signal C counted is proportional to the increase in the frequency of signal A and, therefore, in the case of a linearly operating reluctance transducer, proportional to the force or pressure applied.
  • timing signal B generates reset pulse RSI which clears the reluctance counters and with Q M low disables the display counters 235 and 237-
  • the store pulse ST then latches the pulse count of signal C into the display drivers 239, 241 and the Information is displayed on digital display 243 as a measure of the magnitude of the stimulus, e.g. the force or pressure applied.
  • the next interval of measurement can begin immediately if desired.
  • the circuitry of Figure 14 visually displays the change in frequency above the base frequency. Each successive display interval shows a value proportionate to the difference in frequency above the base value, but there Is no ability to show changes in frequency having a negative sense, i.e.
  • a frequency generator just like that in Figure 14 generates a pulse train, signal A.
  • the generator receives a stimulus that changes the frequency of the pulses and that stimulus may be the changing inductance of a reluctance transducer respond ⁇ ing to an applied force.
  • Signal A is applied to an 8 bit counter, comprising two 4 bit counters connected in series just as in Figure 14.
  • the output signal of the 8 bit counter at terminal Q personally of counter 233 is con ⁇ nected to the input terminal of D-flip flop 245, the element that was noted as optional in Figure 14.
  • the output signal at the primary terminal, Q NN of flip flop 245 is connected to the first of two input terminals of an AND gate 247.
  • the output at the complementary terminal ⁇ ,,lang is connected to the first of two input terminals of an AND gate 2 9. Otherwise, flip flop 245 is connected in Figure 16 as it was in Figure 14.
  • a timing oscillator, just as in Figure 14; generates signal B, a very long pulse in comparison to the pulse widths of signal A.
  • Signal B is applied not only to the enable input terminal of counter 231 but also to the second of the two input terminals of AND gate 247 and to an inverter 251.
  • the signal at the output of AND gate 247, signal D is connected to the C terminal of a second D-flip flop 253- Flip flop 253 also receives reset signal RSI at its reset terminal.
  • the output signal from the primary terminal Q of flip flop 253 is connected to a setting circuit 255 for establishing the sign of visual display 243 according to the direction of the change of the frequency of signal A.
  • the output terminal of inverter 251 at which the complement of signal B, B, appears is connected to the second input terminal of AND gate 249.
  • the output signal of AND gate 249, signal E, is likewise connected to an input terminal of a t ird D-flip flop 257, having the same reset connection to RSI.
  • the output signal at the primary output terminal Q_ of flip flop 257 is connected to a second setting circuit 259 for establishing the sign of digital visual display 243 according to the direction of change of the frequency of signal A.
  • Signals D and E are connected to the two input terminals of an OR gate 261.
  • the output terminal of OR gate 261 is connected to the enable terminal E of the driver counter means, including counters 235 and 237 as in Figure 14.
  • the AND and OR gates, together with flip flop 245, comprise a decision means receiving the first enabling signal appearing at terminal Q M of counter 233 when, as before, 128 pulses have been counted.
  • a first timing signal, the low-high transition of signal B is generated to begin an interval and a second timing signal, the high-low transition of signal B is generated during the interval, to determine whether the frequency of signal A is increasing or decreasing.
  • the decision means also receives these timing signals and determines whether the oscillator frequency is increasing or decreasing. The result of that determination is the generation of at least one direction signal, such as signals D and E, and the signals supplied to the setting circuits 255 and 259.
  • FIG. 17 Operation of the circuitry of Figure 16 is further understood by reference to the timing diagrams of Figure 17.
  • the top five time scales in Figure 17 illustrate operation of the circuitry when the frequen ⁇ cy source is quiescent, i.e. when it is operating at its base frequency. This situation may include a re ⁇ luctance transducer with no force applied to it.
  • Sig- nal A is constant in frequency over the entire inter ⁇ val.
  • Signal B starts the interval with its low to high transition and later during the interval, preferably at its midpoint, generates as a second timing signal by undergoing a high low transition.
  • Figure 17 illustrate the operation of the circuit when a positive stimulus, a stimulus causing an increase in frequency, is applied to the -source of signal A.
  • the increased frequency of signal A means that 128 pulses will be counted during the high level of signal B, and the signals at terminals Q*. and Q Nf . will go high during the early part of an interval, i.e. before the high-low transition of signal B.
  • signal D goes high, until the high-low transition In signal B, and display counter 235, 237 is enabled through OR gate 26l.
  • a direction signal appears at the Q terminal of flip flop 253 so that setting circuit 255 establishes the sign on display 243 as positive.
  • the display counters 235, 237 then count the pulses in signal C until the high-low -transition in signal B, which switches signal D to its low state. At that point, the output of flip flop 245 has already latched with Q NN terminal signal high and QNN termi ⁇ nal signal low, so that signal E remains in its low state. The output signal of OR gate 26l goes low, disabling display counter 235, 237.
  • the display counter generates a frequency change signal that.is transmitted to display 243 by the ST pulse and which displays a value proportional to the number of pulses of signal C that were counted, a number that is propor ⁇ tional to the increase in frequency of signal A over the base frequency.
  • the driver counter begins counting the pulses of signal C when signal - ! B switches from high to low.
  • the signals at ter ⁇ minals Q N and Q MN still go high, meaning the signal at Q NN goes low, switching signal E to its low state.
  • Signal D never goes high in this situation.
  • Display counter 235, 237 is then stopped and the frequency change signal indicating the number of pulses counted is transmitted by pulse ST and appears on display 243 indicating the amount of the decrease in frequency, or, force or pressure according to the scaling.
  • sig ⁇ nal E goes high, a direction signal is produced as a high level signal at the Q terminal of flip flop 257, . . activating setting circuit 259 to set the sign of dis ⁇ play 243- s negative.
  • reset signals RSI and RS2 are generated in a conventional way to reset the cycle counter and display counter.
  • Signal ST is also generated to save the value in the counter and display It on display 243.
  • Another interval may begin immediately thereafter or there may be a "dead" time between intervals.
  • the measurement interval in any of the circuits should be much shorter than the minimum duration of variations in the frequency being detected. This same performance criteria applies whether measurements are made constantly or the circuitry is intermittently operated as described above to reduce power consumption. It is also important to realize that the digital displays 243 of Figures 14 and 16 may be replaced with other types of displays and, as dis ⁇ cussed in Figure 18 below, their drive signals can be used for other functions, digital, or analog. The cir- ' cultry of Figures 14 and 16 is particularly useful because it may be conveniently constructed, except for visual displays, on a single totally digital integrated circuit chip.
  • the drive signals (D and E) that are developed from the interrogation of the applied force or pressure can be used for other useful functions.
  • a plus and minus digital to analog converter can be made by integrating the length of either or both of the D and E intervals to produce an analog signal level indicative of the parameter being measured.
  • This type of circuitry will be useful ln many applications such as the control of trajecto ⁇ ries, speed, force, pressure or pressure regulation, level (mechanical or fluid), etc.
  • Figure 18 shows one possible embodiment of this technique.
  • the circuit shown in Figure 18 includes an OR gate 270 having an output connected to switches 272 and 274.
  • Switch 272 is connected to a resistor 276, and a grounded resistor 27-8 is connected to the line interconnecting switch 272 and resistor 276.
  • a signal is applied to resistor 276.
  • the output of resistor 276 is connected to each of a switch 280, a capacitor 282 and to the negative input of an amplifier 284.
  • Switch 274 is connected to , a resistor 286, and a grounded resistor 288 is connected to the line inter ⁇ connecting switch 274 and 286.
  • a signal v / ⁇ r) p- ⁇ is applied .to resistor 286.
  • the output of resistor 286 is connected to the positive input of amplifie-r 284, to a capacitor 289 and to a switch 290.
  • the latter switch is connected across capacitor 289, and the capacitor is connected to ground.
  • a RESET signal can be applied to each of switches 280 and 290.
  • the output signal of amplifier 284 is designated V , and the output line of amplifier 284 is connected to switch 280, to capacitor 282, and optionally to a switch 292 whose output is designated V O5.
  • amplifier 284 of the network will respond to the E interval ⁇ through OR gate 270 and by closing switch 272 when E is high.
  • resistor 286 references the non-inverting input to ground when switch 274 is open. In this way, a series of short ramps, all of equal positive or negative non- unitary slopes (i.e. having values other whole numbers) and each having a length (and therefore a final ampli ⁇ tude) which is directly related to the length of time the signal appears.
  • the slope, or correction could also be adaptive by allowing the adapting input signal to automatically change the inte ⁇ gration time constant in response to certain pre ⁇ selected and properly weighted system parameters. This is suggested by the V AD p signals to the now variable input resistors 276 and 286. Finally, capacitors 282 and 289 are the reac ⁇ tive portion of the integration time constant, and since they represent the storage elements in the con ⁇ trol network, switches 280 and 290 along with the reset pulse shown are used to either Initialize the system or to clear it as requirements dictate.
  • sample and hold function 292 could be added to the output.
  • each and every measurement interval for the generation of the D or E signals would result in a brand new out ⁇ put signal V whose absolute value is a direct repre ⁇ sentation of the measured parameter rather than a cor ⁇ rection of the old Vo as previously described.
  • the new value would then be stored in capacitor 294 by virtue of the momentary closure of switch 292 when the sample pulse occurs.
  • a reluctance transducer comprising an inner induc- •tive coil for generating a magnetic field in response to the flow of a direct electrical current, reluctance means proximate and surrounding said coil for modifying the reluctance presented to said magnetic field in response to changes in the relative positions of said coil and said reluctance means, and flexible coupling means affixed to one of said coil and said reluctance means for moving said coil relative to said reluctance !._eans In response to applied force.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Hall/Mr Elements (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

Une mesure effective et efficace d'un paramètre physique dynamique telle q'une pression, une force ou un mouvement relatif est obtenue grâce à un système peu couteux qui comprend un dispostif de reluctance relativement mobile (9) entourant la bobine (5) en fonction des changements du paramètre dynamique (F), un générateur de signaux comprenant une résistance variable (75, 89) et un onduleur (73, 81, 83), un comparateur (101) ou un amplificateur opérationnel (101); le système comprend également un processeur (figure 14) pour le traitement des signaux provenant du générateur de signaux selon un comptage des cycles dans le signal de sortie du générateur de signaux et une valeur de train d'impulsions prédéterminée, ainsi q'un convertisseur numérique/analogique (figure 18) pour intégrer les signaux numériques et obtenir des signaux analogiques ayant une pente non-unitaire dont la longueur est représentative de la durée des signaux numériques.
EP19850903939 1985-07-29 1985-07-29 Inductance systems Withdrawn EP0232253A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1985/001427 WO1987000951A1 (fr) 1985-07-29 1985-07-29 Systemes d'inductance

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EP0232253A1 true EP0232253A1 (fr) 1987-08-19
EP0232253A4 EP0232253A4 (en) 1990-09-26

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US5589639A (en) * 1986-02-28 1996-12-31 D'antonio; Nicholas F. Sensor and transducer apparatus
GB8704900D0 (en) * 1987-03-03 1987-04-08 Lucas Ind Plc Transducer
ATE141404T1 (de) * 1988-01-22 1996-08-15 Data Instr Inc Linearer weggeber, besonders verwendbar bei hydraulischen und pneumatischen zylindern
US5497147A (en) * 1993-06-21 1996-03-05 Microstrain, Company Differential variable reluctance transducer
DE19508213B4 (de) * 1995-03-08 2005-10-27 Grundig Multimedia B.V. Fügeüberprüfung
US6622567B1 (en) 1999-03-01 2003-09-23 Microstrain, Inc. Micropower peak strain detection system for remote interrogation
US6433629B2 (en) 2000-01-24 2002-08-13 Microstrain, Inc. Micropower differential sensor measurement

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Also Published As

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EP0232253A4 (en) 1990-09-26
WO1987000951A1 (fr) 1987-02-12

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