EP0226721A1 - Switchable bipolar current source - Google Patents

Switchable bipolar current source Download PDF

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Publication number
EP0226721A1
EP0226721A1 EP86112708A EP86112708A EP0226721A1 EP 0226721 A1 EP0226721 A1 EP 0226721A1 EP 86112708 A EP86112708 A EP 86112708A EP 86112708 A EP86112708 A EP 86112708A EP 0226721 A1 EP0226721 A1 EP 0226721A1
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EP
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Prior art keywords
transistors
current source
output
transistor
input
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Granted
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EP86112708A
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German (de)
French (fr)
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EP0226721B1 (en
Inventor
Jochen Dipl.-Ing. Reisinger
Franz Dipl.-Ing. Dielacher
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Siemens AG
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Siemens AG
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Priority to AT86112708T priority Critical patent/ATE82808T1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the invention relates to a bipolar current source according to the preamble of patent claim 1.
  • the invention is based on the object of specifying a reference current source which can be switched in polarity and whose reference current is adjustable.
  • Embodiments of the inventive concept are characterized in the subclaims.
  • the circuit according to the invention is supplied by a voltage lying between two terminals VDD and VSS of a supply voltage source.
  • the circuit contains a first current mirror with metal oxide semiconductor transistors of the n-channel type and a second current mirror with metal oxide Hall conductor transistors of the p-channel type, which are connected in series and whose output transistors are controlled alternately via transistor switches.
  • a current Io is fed into the first current mirror via a terminal SE.
  • This first current mirror contains the input transistor MN1, which is connected as a diode, the mirror transistor MN2 and the output transistor MN3. While the gates of the transistors MN1 and MN2 are connected directly to one another and to the input terminal SE, the output circuit of a transistor MP3 lies between the gate of the transistor MN3.
  • the connections of the transistors MN1, MN2 and MN3 serving as source are connected to the terminal VSS of the supply voltage source.
  • the output circuit of a transistor MN4 is located in front of the gate of the transistor MN3 and the terminal VSS of the supply voltage source.
  • the output circuits of transistors MP1 and MP2 of the second current mirror are in series with the output circuits of transistors MN2 and MN3.
  • the gate of transistor MP1 is directly connected to the junction of the output circuits Transistors MN2 and MP1 and connected to the gate of transistor MP2 via the output circuit of a transistor MN5.
  • the connections of the transistors of the second current mirror which serve as the source are connected to the terminal VDD of the supply voltage source.
  • the gate of transistor MP2 is also connected to terminal VDD across the output circuit of transistor MP4.
  • the terminal SA for the current output of the circuit is located at the connection point of the output circuits of the two output transistors MN3 and MP2.
  • the transistors MN4 and MN5 are in the exemplary embodiment of the n-channel type and the transistors MP3 and MP4 of the p-channel type; the gates of the latter four transistors are connected to one another at a terminal VZ.
  • the current Io flowing into the circuit via the terminal SE is first reflected by the transistor MN1 connected as a diode into the mirror transistor MN2 and thus also flows through the input transistor of the second current mirror MP1.
  • the transistors MN4 and MN5 are now blocked and the transistors MP3 and MP4 are switched to the conductive state or vice versa. It is essential to the invention that the output transistors of the two current mirrors can be switched off, in particular alternately, for which purpose other switch arrangements or other transistor types can also be used.
  • the transistor MP3 conducts and the transistor MP4 blocks.
  • the input current Io is then mirrored into the transistor MN3 in accordance with the transmission ratio of the first current mirror, ie essentially in accordance with the ratio of channel width to channel length of the transistor MN3 with respect to the transistor MN1.
  • the through the transistors MN2 and Current flowing in MP1 has no influence on the output current of the circuit, since transistor MN5 blocks and transistor MP4 conducts at negative potential at terminal VZ, so that output transistor MP2 of the second current mirror is blocked.
  • the situation is exactly the opposite, i.e. the transistor MP3 blocks and the transistor MN4 conducts, so that the output transistor MN3 safely blocks.
  • the input current Io is first mirrored into the transistor MN2 according to the conversion ratio of the transistors MN2 to MN1 of the first current mirror.
  • This current which then also flows through the transistor MP1, is calculated in accordance with the transmission ratio of the second current mirror, i.e. mirrored into transistor MP2 according to the ratio of transistors MP2 to MP1.
  • the reference current flowing into output terminal SA is either negative or positive.
  • FIG. 2 shows another embodiment of the input circuit of the switchable bipolar current source according to FIG. 1.
  • the output circuit of the transistor MN1 is connected to the terminal serving as drain via a resistor R with a terminal GND for connecting a reference potential.
  • the connection of this transistor serving as the source lies at the pole VSS of the supply voltage source.
  • the gate of transistor MN1 and thus the gate of transistor MN2 and a connection of the output circuit of transistor MP3 is at the output of an operational amplifier OP, the inverting input of which is connected to a terminal VREF Connection of a reference potential and its non-inverting input is connected to the connection point of the output circuit of the transistor MN1 and the resistor R.
  • the rest of the circuit is then designed according to the invention in accordance with FIG. 1.
  • the input current Io to be mirrored and flowing through the transistor MN1 is decoupled from the output of the operational amplifier OP via the amplifier via the transistor MN1 to the input of the operational amplifier and is thus kept constant.
  • the transistors of the current mirrors can be designed, for example, according to the cascode principle or according to the Wilson or Improved Wilson principle.
  • FIG. 3 shows a circuit operating according to the cascode principle with an input circuit according to FIG. 2.
  • the transistors MN1, MN2 and MP1 according to FIG. 1 are connected in series by two transistors N11 and N12, N21 and N22 as well as P11 and P12 replaced.
  • Gate and drain connections of transistors N12, P11 and P12 are each connected to one another.
  • the transistors N11 and N12 are driven with an input circuit according to FIG. 2.
  • the output transistors MN3 and MP2 according to FIG. 1 are replaced by the parallel connection of three, each of two transistors connected in series.
  • the drain connections connected to a common node form the circuit output and are connected to the terminals 5A sets.
  • the jointly controlled gates of N11 and N12 are connected to the gates of N31, N33 and N35 via the output circuit of MP3.
  • the gate of P12 is connected to the gates of P22, P24 and P26 via the output circuit of MN5.
  • the transistors N12, N22, N32, N34, N36 on the one hand and P11, P21, P23 and P25 on the other hand each have common gate control.
  • FIG. 3 can be operated with only one switch combination MN4, MN5, MP3, MP4 according to FIG. 1, which acts on only one gate circuit in each case.
  • the series connection of the resistors RN and RG lying between the drain connections of N21 and P12 brings about a symmetrization of the circuit, ie the same operating points or the same drain-source voltages of the current mirror transistors when the load is connected from the terminal SA to the reference terminal GND. Then the connection point between RN and RG is virtually at the reference potential.
  • the reference output current can be increased in accordance with the changed transmission ratio of the current mirror with the same dimensioning of the transistors. If one chooses the ohmic load to be switched by the terminal SA against the reference terminal GND according to the translation of the current level smaller than the resistance R, then the voltage drops across the load and R are equal.
  • FIG. 4 shows an exemplary embodiment according to the invention of a circuit working according to the Improved Wilson principle with an input circuit according to FIG. 2.
  • a circuit according to this principle enables the same drain-source voltages of the transistors by one versus one Wilson current source additional transistor connected as a diode.
  • the circuit according to FIG. 4 results from the circuit according to FIG. 3 with the changes listed below, the reference symbols of the current source transistors having been changed.
  • the drain-gate connections of N12 and P11 (FIG. 3) are omitted for N2 and P1 (FIG. 4), but drain-gate connections are made for N22, N32, N34, N36, P21, P23 and P25 (FIG. 3) Connections are provided so that the elements N4, N6, N8, N10, P5, P7 and P9 (FIG. 4) result.
  • the not yet switched gate circuit of the output transistors is provided with switching transistors MN41, MN51, MP31 and MP41 which can be controlled by terminal VZ. which in this order correspond to the transistors MN4, MN5, MP3 and MP4 for the other gate circuit.
  • the series connection of the output circuits of two transistors P3 and P4 and a resistor RG are connected from the terminal VDD to the reference terminal GND.
  • the drain and gate of P3 are connected to each other and to the gate of P1 and the gate of P4 is connected to the gate of P2.
  • This arrangement serves to symmetrize the circuit in order to ensure the same operating points for all transistors.
  • the resistors RN and RP and R and an ohmic load to be switched by the terminal SA against the reference potential also belong, in accordance with the explanations given in FIG. 3, to ensure the same operating points for the transistors.
  • circuits according to the invention shown in FIGS. 1 to 4 as exemplary embodiments contain metal oxide semiconductor transistors, the letters N or P of the reference symbols relating to the channel type.
  • a circuit construction with metal oxide semiconductor transistors of another type is encompassed by the teaching of the invention.
  • this circuit can also be implemented with the aid of bipolar transistors.
  • there is the possibility of increasing the output reference current with simple means in that further metal oxide transistors are connected in parallel with the output transistors, taking into account the channel type, or the essentially current-determining ratio of channel width Channel length is increased.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)

Abstract

Die schaltbare bipolare Stromquelle enthält die Kombination zweier hintereinander geschalteter konventioneller Stromspiegel (MN1, MN2, MN3; MP1, MP2), die vom entgegengesetzten Typ sind und deren Ausgangstransistoren (MN3, MP2) über Transistorschalter (MN4, MP3, MP4, MN5) wechselweise angesteuert werden, so daß am Ausgang (SA) abhängig vom Schaltzustand (VZ) ein positiver oder negativer Referenzstrom zur Verfügung steht.The switchable bipolar current source contains the combination of two series-connected conventional current mirrors (MN1, MN2, MN3; MP1, MP2), which are of the opposite type and whose output transistors (MN3, MP2) are controlled alternately via transistor switches (MN4, MP3, MP4, MN5) so that a positive or negative reference current is available at the output (SA) depending on the switching state (VZ).

Description

Die Erfindung betrifft eine bipolare Stromquelle nach dem Oberbegriff des Patentanspruchs 1.The invention relates to a bipolar current source according to the preamble of patent claim 1.

Stromquellen, die einen positiven oder negativen Ausgangs­strom liefern können, sind bekannt und beispielsweise in dem Buch "Halbleiter-Schaltungstechnik" von U. Tietze, Ch. Schenk, Springer-Verlag, Berlin, Heidelberg, New York, 1980, Seite 54 folgende beschrieben. Eine dort angegebene Stromquelle liefert einen Ausgangsstrom, der proportional zu einer an­gelegten Eingangsspannung ist. Für einen Anwendungsfall, der entweder einen positiven oder negativen Referenzstrom er­fordert, ist eine Lösung mit einer Stromquelle für den posi­tiven und einer Stromquelle für den negativen Referenzstrom mit nachfolgender Multiplexschaltung üblich.Current sources which can supply a positive or negative output current are known and are described, for example, in the book "Semiconductor Circuit Technology" by U. Tietze, Ch. Schenk, Springer-Verlag, Berlin, Heidelberg, New York, 1980, page 54, below. A current source specified there provides an output current that is proportional to an applied input voltage. For an application that requires either a positive or negative reference current, a solution with a current source for the positive and a current source for the negative reference current with subsequent multiplexing is common.

Der Erfindung liegt die Aufgabe zugrunde, eine in der Polari­tät umschaltbare Referenzstromquelle anzugeben, deren Referenz­strom einstellbar ist.The invention is based on the object of specifying a reference current source which can be switched in polarity and whose reference current is adjustable.

Diese Aufgabe wird bei einer bipolaren Stromquelle der ein­gangs genannten Art erfindungsgemäß durch die Merkmale des kennzeichnenden Teils des Patentanspruchs 1 gelöst.This object is achieved according to the invention in a bipolar current source of the type mentioned at the outset by the features of the characterizing part of patent claim 1.

Ausgestaltungen des Erfindungsgedankens sind in Unteran­sprüchen gekennzeichnet.Embodiments of the inventive concept are characterized in the subclaims.

Die Erfindung wird im folgenden anhand von in den Figuren der Zeichnung dargestellten Ausführungsbeispielen näher erläutert. Gleiche Elemente sind mit gleichen Bezugszeichen versehen.The invention is explained in more detail below with reference to exemplary embodiments shown in the figures of the drawing. The same elements are provided with the same reference symbols.

Es zeigt:

  • Fig. 1 ein Schaltbild einer erfindungsgemäßen schaltbaren bipolaren Stromquelle,
  • Fig. 2 ein Ausführungsbeispiel einer Eingangsschaltung für eine erfindungsgemäße schaltbare bipolare Strom­quelle,
  • Fig. 3 ein Schaltbild einer nach dem Kaskode-Prinzip arbeitenden erfindungsgemäßen Stromquelle.
  • Fig. 4 ein Schaltbild einer nach dem Improved-Wilson-Prin­zip arbeitenden erfindungsgemäßen Stromquelle.
It shows:
  • 1 is a circuit diagram of a switchable bipolar current source according to the invention,
  • 2 shows an embodiment of an input circuit for a switchable bipolar current source according to the invention,
  • Fig. 3 is a circuit diagram of a current source according to the invention working on the cascode principle.
  • Fig. 4 is a circuit diagram of a power source according to the invention working according to the Improved Wilson principle.

Gemäß Fig. 1 wird die erfindungsgemäße Schaltung von einer zwischen zwei Klemmen VDD und VSS einer Speisespannungs­quelle liegenden Spannung versorgt. Die Schaltung enthält einen ersten Stromspiegel mit Metalloxid-Halbleitertransi­storen vom n-Kanal-Typ und einen zweiten Stromspiegel mit Metalloxid-Hallbleitertransistoren vom p-Kanal-Typ, die hintereinander geschaltet sind und deren Ausgangstransistoren über Transistorschalter wechselweise angesteuert werden. In den ersten Stromspiegel wird über eine Klemme SE ein Strom Io eingespeist. Dieser erste Stromspiegel enthält den Eingangstransistor MN1, der als Diode geschaltet ist, den Spiegeltransistor MN2 und den Ausgangstransistor MN3. Während die Gates der Transistoren MN1 und MN2 direkt miteinander und mit der Eingangsklemme SE ver-bunden sind, liegt zwischen dem Gate des Transistors MN3 der Ausgangskreis eines Transistors MP3. Die als Source dienenden Anschlüsse der Transistoren MN1, MN2 und MN3 sind mit der Klemme VSS der Speisespannungsquelle verbunden. Zusätzlich liegt vor dem Gate des Transistors MN3 und der Klemme VSS der Speise­spannungsquelle der Ausgangskreis eines Transistors MN4.1, the circuit according to the invention is supplied by a voltage lying between two terminals VDD and VSS of a supply voltage source. The circuit contains a first current mirror with metal oxide semiconductor transistors of the n-channel type and a second current mirror with metal oxide Hall conductor transistors of the p-channel type, which are connected in series and whose output transistors are controlled alternately via transistor switches. A current Io is fed into the first current mirror via a terminal SE. This first current mirror contains the input transistor MN1, which is connected as a diode, the mirror transistor MN2 and the output transistor MN3. While the gates of the transistors MN1 and MN2 are connected directly to one another and to the input terminal SE, the output circuit of a transistor MP3 lies between the gate of the transistor MN3. The connections of the transistors MN1, MN2 and MN3 serving as source are connected to the terminal VSS of the supply voltage source. In addition, the output circuit of a transistor MN4 is located in front of the gate of the transistor MN3 and the terminal VSS of the supply voltage source.

In Serie zu den Ausgangskreisen der Transistoren MN2 und MN3 liegen die Ausgangskreise der Transistoren MP1 und MP2 des zweiten Stromspiegels. Das Gate des Transistors MP1 ist direkt mit dem Verbindungspunkt der Ausgangskreise der Transistoren MN2 und MP1 und über den Ausgangskreis eines Transistors MN5 mit dem Gate des Transistors MP2 verbunden. Die als Source dienenden Anschlüsse der Transistoren des zweiten Stromspiegels sind mit der Klemme VDD der Speise­spannungsquelle verbunden. Das Gate des Transistors MP2 liegt über dem Ausgangskreis eines Transistors MP4 ebenfalls an der Klemme VDD. Am Verbindungspunkt der Ausgangskreise der beiden Ausgangstransistoren MN3 und MP2 liegt die Klemme SA für den Stromausgang der Schaltung. Die Transistoren MN4 und MN5 sind im Ausfhrungsbeispiel vom n-Kanal-Typ und die Transistoren MP3 und MP4 vom p-Kanal-Typ; die Gates dieser letztgenannten vier Transistoren sind miteinander an einer Klemme VZ angeschlossen.The output circuits of transistors MP1 and MP2 of the second current mirror are in series with the output circuits of transistors MN2 and MN3. The gate of transistor MP1 is directly connected to the junction of the output circuits Transistors MN2 and MP1 and connected to the gate of transistor MP2 via the output circuit of a transistor MN5. The connections of the transistors of the second current mirror which serve as the source are connected to the terminal VDD of the supply voltage source. The gate of transistor MP2 is also connected to terminal VDD across the output circuit of transistor MP4. The terminal SA for the current output of the circuit is located at the connection point of the output circuits of the two output transistors MN3 and MP2. The transistors MN4 and MN5 are in the exemplary embodiment of the n-channel type and the transistors MP3 and MP4 of the p-channel type; the gates of the latter four transistors are connected to one another at a terminal VZ.

Der über die Klemme SE in die Schaltung fließende Strom Io wird vom als Diode geschalteten Transistor MN1 zunächst in den Spiegeltransistor MN2 gespiegelt und fließt damit auch durch den Eingangstransistor des zweiten Stromspiegels MP1. Abhängig vom Vorzeichen eines an der Klemme VZ liegenden Potentials werden nun entweder die Transistoren MN4 und MN5 gesperrt und die Transistoren MP3 und MP4 in den leitenden Zustand geschaltet oder paarweise umgekehrt. Erfindungs­wesentlich ist, daß die Ausgangstransistoren der beiden Stromspiegel abschaltbar sind, insbesondere wechselweise, wozu auch andere Schalteranordnungen oder andere Transi­stortypen dienen können.The current Io flowing into the circuit via the terminal SE is first reflected by the transistor MN1 connected as a diode into the mirror transistor MN2 and thus also flows through the input transistor of the second current mirror MP1. Depending on the sign of a potential at the terminal VZ, either the transistors MN4 and MN5 are now blocked and the transistors MP3 and MP4 are switched to the conductive state or vice versa. It is essential to the invention that the output transistors of the two current mirrors can be switched off, in particular alternately, for which purpose other switch arrangements or other transistor types can also be used.

Bei einem negativen Potential an der Klemme VZ leitet der Transistor MP3 und der Transistor MP4 sperrt. Der Eingangs­strom Io wird dann entsprechend dem Übersetzungsverhältnis des ersten Stromspiegels, d.h. im wesentlichen entsprechend dem Verhältnis von Kanalweite zu Kanallänge des Transistors MN3 bezogen auf den Transistor MN1 in den Transistor MN3 gespiegelt. Der gleichzeitig durch die Transistoren MN2 und MP1 fließende Strom hat auf den Ausgangsstrom der Schaltung keinen Einfluß, da bei negativem Potential an der Klemme VZ der Transistor MN5 sperrt und der Transistor MP4 leitet, so daß der Ausgangstransistor MP2 des zweiten Stromspiegels ge­sperrt wird.If the potential at the terminal VZ is negative, the transistor MP3 conducts and the transistor MP4 blocks. The input current Io is then mirrored into the transistor MN3 in accordance with the transmission ratio of the first current mirror, ie essentially in accordance with the ratio of channel width to channel length of the transistor MN3 with respect to the transistor MN1. The through the transistors MN2 and Current flowing in MP1 has no influence on the output current of the circuit, since transistor MN5 blocks and transistor MP4 conducts at negative potential at terminal VZ, so that output transistor MP2 of the second current mirror is blocked.

Bei einem positiven Potential an der Klemme VZ sind die Verhältnisse genau umgekehrt, d.h. der Transistor MP3 sperrt und der Transistor MN4 leitet, so daß der Ausgangstransis­tor MN3 sicher sperrt. Da andererseits in diesem Fall der Transistor MN5 leitet und der Transistor MP4 gesperrt ist, wird der Eingangsstrom Io zunächst gemäß dem Übersetzungs­verhältnis der Transistoren MN2 zu MN1 des ersten Strom­spiegels in den Transistor MN2 gespiegelt. Dieser dann eben­falls durch den Transistor MP1 fließende Strom wird gemäß dem Übersetzungsverhältnis des zweiten Stromspiegels, d.h. gemäß dem Übersetzungsverhältnis der Transistoren MP2 zu MP1 in den Transistor MP2 gespiegelt. Abhängig vom Potential der Klemme VZ ist damit der in die Ausgangsklemme SA fließende Referenz­strom entweder negativ oder positiv.With a positive potential at terminal VZ, the situation is exactly the opposite, i.e. the transistor MP3 blocks and the transistor MN4 conducts, so that the output transistor MN3 safely blocks. On the other hand, since in this case the transistor MN5 conducts and the transistor MP4 is blocked, the input current Io is first mirrored into the transistor MN2 according to the conversion ratio of the transistors MN2 to MN1 of the first current mirror. This current, which then also flows through the transistor MP1, is calculated in accordance with the transmission ratio of the second current mirror, i.e. mirrored into transistor MP2 according to the ratio of transistors MP2 to MP1. Depending on the potential of terminal VZ, the reference current flowing into output terminal SA is either negative or positive.

In Fig. 2 ist eine andere Ausgestaltung der Eingangs­schaltung der erfindungsgemäßen schaltbaren bipolaren Strom­quelle nach Fig. 1 angegeben. Der Ausgangskreis des Transis­tors MN1 ist mit dem als Drain dienenden Anschluß über einen Widerstand R mit einer Klemme GND zum Anschluß eines Be­zugspotentials verbunden. Der als Source dienende Anschluß dieses Transistors liegt am Pol VSS der Versorgungsspannungs­quelle. Das Gate des Transistors MN1 und damit das Gate des Transistors MN2 und ein Anschluß des Ausgangskreises des Transistors MP3 liegt am Ausgang eines Operationsverstärkers OP, dessen invertierender Eingang mit einer Klemme VREF zum Anschluß eines Referenzpotentials und dessen nichtinver­tierender Eingang mit dem Verbindungspunkt des Ausgangs­kreises des Transistors MN1 und des Widerstandes R verbunden ist. Die übrige Schaltung ist dann erfindungsgemäß ent­sprechend Fig. 1 ausgeführt. Gemäß dem an der Klemme VREF liegenden Referenzpotential wird der zu spiegelnde, durch den Transistor MN1 fließende Eingangsstrom Io vom Ausgang des Operationsverstärkers OP über den sverstärkers über den Transistor MN1 auf den Eingang des Operationsverstärkers gegengekoppelt und somit konstant gehalten.FIG. 2 shows another embodiment of the input circuit of the switchable bipolar current source according to FIG. 1. The output circuit of the transistor MN1 is connected to the terminal serving as drain via a resistor R with a terminal GND for connecting a reference potential. The connection of this transistor serving as the source lies at the pole VSS of the supply voltage source. The gate of transistor MN1 and thus the gate of transistor MN2 and a connection of the output circuit of transistor MP3 is at the output of an operational amplifier OP, the inverting input of which is connected to a terminal VREF Connection of a reference potential and its non-inverting input is connected to the connection point of the output circuit of the transistor MN1 and the resistor R. The rest of the circuit is then designed according to the invention in accordance with FIG. 1. In accordance with the reference potential at the terminal VREF, the input current Io to be mirrored and flowing through the transistor MN1 is decoupled from the output of the operational amplifier OP via the amplifier via the transistor MN1 to the input of the operational amplifier and is thus kept constant.

Eine andere Ausgestaltung einer erfindungsgemäßen Schaltung ist vorgesehen, wenn der Innenwiderstand der Stromquellen erhöht werden soll. Dazu können die Transistoren der Strom­spiegel beispielsweise nach dem Kaskode-Prinzip oder nach dem Wilson- oder Improved-Wilson-Prinzip ausgebildet sein.Another embodiment of a circuit according to the invention is provided if the internal resistance of the current sources is to be increased. For this purpose, the transistors of the current mirrors can be designed, for example, according to the cascode principle or according to the Wilson or Improved Wilson principle.

Fig. 3 zeigt eine nach dem Kaskode-Prinzip arbeitende Schaltung mit einer Eingangsschaltung gemäß Fig. 2. In ihr sind die Transistoren MN1,MN2 und MP1 gemäß Fig. 1 durch die Reihenschaltung jeweils zweier Transistoren N11 und N12, N21 und N22 sowie P11 und P12 ersetzt.FIG. 3 shows a circuit operating according to the cascode principle with an input circuit according to FIG. 2. In it, the transistors MN1, MN2 and MP1 according to FIG. 1 are connected in series by two transistors N11 and N12, N21 and N22 as well as P11 and P12 replaced.

Gate- und Drainanschlüsse der Transistoren N12, P11 und P12 sind jeweils miteinander verbunden. Die Ansteuerung der Transistoren N11 und N12 erfolgt mit einer Eingangsschaltung gemäß Fig. 2.Gate and drain connections of transistors N12, P11 and P12 are each connected to one another. The transistors N11 and N12 are driven with an input circuit according to FIG. 2.

Die Ausgangstransistoren MN3 und MP2 gemäß Fig. 1 sind durch die Parallelschaltung von drei, jeweils aus zwei in Reihe geschalteten Transistoren ersetzt. Die auf einen gemeinsamen Knotenpunkt geschalteten Drainanschlüsse bil­den den Schaltungsausgang und sind an die Klemmen 5A ge­ legt. Die gemeinsam angesteuerten Gates von N11 und N12 sind über den Ausgangskreis von MP3 an die Gates von N31, N33 und N35 angeschlossen. Ebenso ist das Gate von P12 über den Ausgangskreis von MN5 mit den Gates von P22, P24 und P26 verbunden. Jeweils gemeinsame Gateansteuerung be­sitzen die Transistoren N12, N22, N32, N34, N36 einer­seits und P11, P21, P23 und P25 andererseits. Erfindungsgemäß läßt sich die Kaskode-Schaltung gemäßt Fig. 3 mit nur einer Schalterkombination MN4, MN5, MP3, MP4 gemäß Fig. 1, die auf jeweils nur einen Gatekreis wirkt, betreiben. Die zwischen den Drainanschlüssen von N21 und P12 liegende Reihenschaltung der Widerstände RN und RG bewirkt eine Symmetrierung der Schaltung, d.h. gleiche Arbeitspunkte bzw. gleiche Drain-Source-Spannungen der Stromspiegeltransistoren, wenn die Last von der Klemme SA gegen die Bezugsklemme GND geschaltet wird. Dann liegt der Verbindungspunkt von RN mit RG virtuell auf dem Bezugspotential.The output transistors MN3 and MP2 according to FIG. 1 are replaced by the parallel connection of three, each of two transistors connected in series. The drain connections connected to a common node form the circuit output and are connected to the terminals 5A sets. The jointly controlled gates of N11 and N12 are connected to the gates of N31, N33 and N35 via the output circuit of MP3. Likewise, the gate of P12 is connected to the gates of P22, P24 and P26 via the output circuit of MN5. The transistors N12, N22, N32, N34, N36 on the one hand and P11, P21, P23 and P25 on the other hand each have common gate control. According to the invention, the cascode circuit according to FIG. 3 can be operated with only one switch combination MN4, MN5, MP3, MP4 according to FIG. 1, which acts on only one gate circuit in each case. The series connection of the resistors RN and RG lying between the drain connections of N21 and P12 brings about a symmetrization of the circuit, ie the same operating points or the same drain-source voltages of the current mirror transistors when the load is connected from the terminal SA to the reference terminal GND. Then the connection point between RN and RG is virtually at the reference potential.

Durch Parallelschalten mehrerer Ausgangskreise läßt sich bei gleicher Dimmensionierung der Transistoren der Refe­renz-Ausgangsstrom entsprechend dem geänderten Übersetzungs­verhältnis des Stromspiegels vergrößern. Wählt man die von der Klemme SA gegen die Bezugsklemme GND zu schaltende ohmsche Last entsprechend der Übersetzung des Stromspie­gels kleiner als den Widerstand R, dann sind die Spannungs­abfälle über der Last und R gleich groß.By connecting several output circuits in parallel, the reference output current can be increased in accordance with the changed transmission ratio of the current mirror with the same dimensioning of the transistors. If one chooses the ohmic load to be switched by the terminal SA against the reference terminal GND according to the translation of the current level smaller than the resistance R, then the voltage drops across the load and R are equal.

Fig. 4 zeigt ein erfindungsgemäßes Ausführungsbeispiel einer nach dem Improved-Wilson-Prinzip arbeitenden Schal­tung mit einer Eingangsschaltung gemäß Fig. 2. Eine Schal­tung nach diesem Prinzip ermöglicht gleiche Drain-Source-­Spannungen der Transistoren durch einen gegenüber einer Wilson-Stromquelle zusätzlichen, als Diode geschalteten Transistor.FIG. 4 shows an exemplary embodiment according to the invention of a circuit working according to the Improved Wilson principle with an input circuit according to FIG. 2. A circuit according to this principle enables the same drain-source voltages of the transistors by one versus one Wilson current source additional transistor connected as a diode.

Die Schaltung gemäß Fig. 4 ergibt sich mit nachstehend aufgeführten Veränderungen aus der Schaltung gemäß Fig. 3, wobei die Bezugszeichen der Stromquellentransistoren ge­ändert wurden. Die Drain-Gate-Verbindungen von N12 und P11 (Fig. 3) entfallen für N2 und P1 (Fig. 4) dafür werden bei N22, N32, N34, N36, P21, P23 und P25 (Fig. 3) Drain-­Gate-Verbindungen vorgesehen, so daß sich die Elemente N4, N6, N8, N10, P5, P7 und P9 (Fig. 4) ergeben. Zusätz­lich wird jeweils der noch nicht geschaltete Gatekreis der Ausgangstransistoren mit von der Klemme VZ steuerba­ren Schalttransistoren MN41, MN51, MP31 und MP41 versehen. die in dieser Reihenfolge jeweils den Transistoren MN4, MN5, MP3 und MP4 für den jeweils anderen Gatekreis ent­sprechen.The circuit according to FIG. 4 results from the circuit according to FIG. 3 with the changes listed below, the reference symbols of the current source transistors having been changed. The drain-gate connections of N12 and P11 (FIG. 3) are omitted for N2 and P1 (FIG. 4), but drain-gate connections are made for N22, N32, N34, N36, P21, P23 and P25 (FIG. 3) Connections are provided so that the elements N4, N6, N8, N10, P5, P7 and P9 (FIG. 4) result. In addition, the not yet switched gate circuit of the output transistors is provided with switching transistors MN41, MN51, MP31 and MP41 which can be controlled by terminal VZ. which in this order correspond to the transistors MN4, MN5, MP3 and MP4 for the other gate circuit.

Zusätzlich ist von der Klemme VDD gegen die Bezugsklemme GND die Reihenschaltung der Ausgangskreise zweier Tran­sistoren P3 und P4 sowie ein Widerstand RG geschaltet. Drain und Gate von P3 sind miteinander und mit dem Gate von P1 und das Gate von P4 ist mit dem Gate von P2 ver­bunden. Diese Anordnung dient zur Symmetrierung der Schaltung, um gleiche Arbeitspunkte für alle Transistoren zu gewährleisten. Ebenfalls gehören die Widerstände RN und RP sowie R und eine von der Klemme SA gegen das Be­zugspotential zu schaltenden ohmsche Last entsprechend den Ausführungen zu Fig. 3 zur Sicherung gleicher Ar­beitspunkte für die Transistoren.In addition, the series connection of the output circuits of two transistors P3 and P4 and a resistor RG are connected from the terminal VDD to the reference terminal GND. The drain and gate of P3 are connected to each other and to the gate of P1 and the gate of P4 is connected to the gate of P2. This arrangement serves to symmetrize the circuit in order to ensure the same operating points for all transistors. The resistors RN and RP and R and an ohmic load to be switched by the terminal SA against the reference potential also belong, in accordance with the explanations given in FIG. 3, to ensure the same operating points for the transistors.

Die gemäß den Figuren 1 bis 4 als Ausführungsbeipsiele ange­führten erfindungsgemäßen Schaltungen enthalten Metalloxid-­Halbleitertransistoren, wobei die Buchstaben N oder P der Bezugszeichen den Kanal-Typ angehen. Ein Schaltungsaufbau mit Metalloxid-Halbleitertransistoren anderen Typ wird von der Lehre der Erfindung umfaßt. Ebensogut läßt sich diese Schaltung jedoch mit Hilfe von bipolaren Transistoren realisieren. Speziell in der Ausführung mit Metalloxid-­Halbleiter-Transistoren ergibt sich die Möglichkeit, den Ausgangs- Referenzstrom mit einfachen Mitteln zu vergrößern, indem weitere Metalloxid-Transistoren den Ausgangstransi­storen unter Beachtung des Kanaltyps parallel geschaltet werden oder das im wesentlichen den Strom bestimmende Verhältnis von Kanalweite zu Kanallänge vergrößert wird.The circuits according to the invention shown in FIGS. 1 to 4 as exemplary embodiments contain metal oxide semiconductor transistors, the letters N or P of the reference symbols relating to the channel type. A circuit construction with metal oxide semiconductor transistors of another type is encompassed by the teaching of the invention. However, this circuit can also be implemented with the aid of bipolar transistors. Especially in the version with metal oxide semiconductor transistors, there is the possibility of increasing the output reference current with simple means, in that further metal oxide transistors are connected in parallel with the output transistors, taking into account the channel type, or the essentially current-determining ratio of channel width Channel length is increased.

Claims (13)

1. Bipolare Stromquelle mit einer Speisespannungsquel­le (VDD, VSS), einem ersten Stromspiegel (MN1, MN2, MN3; N11, N12, N21, N22, N31 bis N36; N1 bis N10) mit Tran­sistoren eines Typs und einem zweiten Stromspiegel (MP1, MP2; P11, P12, P21 bis P26; P1 bis P10) mit Transisto­ren vomanderen Typ, die eine Eingangs- und Ausgangstran­sistoranordnung (MN1, MP1; N11, N12, P11, P12; N1, N2, P1, P2; MN3, MP2; N31 bis N36, P21 bis P26; N5 bis N10, P5 bis P10) enthalten, dadurch gekenn­zeichnet, daß die Stromspiegel (MN1 bis MN3, MP1, MP2; N11, N12, N21, N22, N31 bis N36, P11, P12, P21 bis P26; N1 bis N10, P1 bis P10) hintereinander ge­schaltet sind und ihre Ausgangstransistorenordnung (MN3, MP2; N31 bis N36, P21 bis P26; N5 bis N10, P5 bis P10) abschaltbar ist.1. Bipolar current source with a supply voltage source (VDD, VSS), a first current mirror (MN1, MN2, MN3; N11, N12, N21, N22, N31 to N36; N1 to N10) with transistors of one type and a second current mirror (MP1, MP2; P11, P12, P21 to P26; P1 to P10) with transistors of another type which have an input and output transistor arrangement (MN1, MP1; N11, N12, P11, P12; N1, N2, P1, P2; MN3, MP2; Contain N31 to N36, P21 to P26; N5 to N10, P5 to P10), characterized in that the current mirrors (MN1 to MN3, MP1, MP2; N11, N12, N21, N22, N31 to N36, P11, P12, P21 to P26; N1 to N10, P1 to P10) are connected in series and their output transistor arrangement (MN3, MP2; N31 to N36, P21 to P26; N5 to N10, P5 to P10) can be switched off. 2. Bipolare Stromquelle nach Anspruch 1, dadurch gekennzeichnet, daß der erste Stromspiegel (MN1 bis MN3; N11, N12, N21, N22, N31 bis N36; N1 bis N10) eine Spiegeltransistoranordnung (MN2; N21, N22; N3, N4) enthält, die mit ihrem Ausgangskreis in Serie zum Aus­gangskreis der Eingangstransistoranordnung (MP1; P11, P12; P1, P2) des zweiten Stromspiegels (MP1, MP2; P11, P12, P21 bis P26; P1 bis P10) liegt.2. Bipolar current source according to claim 1, characterized in that the first current mirror (MN1 to MN3; N11, N12, N21, N22, N31 to N36; N1 to N10) contains a mirror transistor arrangement (MN2; N21, N22; N3, N4) , which lies with its output circuit in series with the output circuit of the input transistor arrangement (MP1; P11, P12; P1, P2) of the second current mirror (MP1, MP2; P11, P12, P21 to P26; P1 to P10). 3. Bipolare Stromquelle nach Anspruch 1 oder 2, da­durch gekennzeichnet, daß Ein­gangstransistoren (MN1, MP1; N12, P11, P12; N4, P2, P3) der Eingangstransistoranordnung (MN1, MP1; N11, N12, P11, P12; N1, N2, P1 bis P4) als Dioden geschaltet sind.3. Bipolar current source according to claim 1 or 2, characterized in that input transistors (MN1, MP1; N12, P11, P12; N4, P2, P3) of the input transistor arrangement (MN1, MP1; N11, N12, P11, P12; N1, N2 , P1 to P4) are connected as diodes. 4. Bipolare Stromquelle nach Anspruch 1 oder 2, da­durch gekennzeichnet, daß ein Eingangstransistor (MN1; N11; N1) der Eingangstransistor­anordnung des ersten Stromspiegels (MN1 bis MN3; N11, N12, N21, N22, N31 bis N36; N1 bis N10) mit seinem Aus­gangskreis über einen Widerstand (R) mit einem Bezugs­potential (GND) und mit seinem Steuereingang mit dem Ausgangs eines Operationsverstärkers (OP) verbunden ist, an dessen invertierenden Eingangs (-) ein Referenz­potential (VREF) und an dessen nichtinvertierenden Ein­gang (+) das Potential des Verbindungspunktes des Wi­derstandes (R) mit dem Ausgangskreis des Eingangstran­sistors (MN1, N11; N1) liegt, und daß mindestens ein Eingangstransistor (MP1; P12; P2) der Eingangstransistor­anordnung des zweiten Stromspiegels (MP1, MP2; P11, P12, P21 bis P26; P1 bis P10) als Diode geschaltet ist.4. Bipolar current source according to claim 1 or 2, characterized in that an input transistor (MN1; N11; N1) of the input transistor arrangement of the first current mirror (MN1 to MN3; N11, N12, N21, N22, N31 to N36; N1 to N10) with its output circuit is connected via a resistor (R) to a reference potential (GND) and its control input is connected to the output of an operational amplifier (OP), a reference potential (VREF) at its inverting input (-) and the reference potential (VREF) at its non-inverting input (+) Potential of the connection point of the resistor (R) with the output circuit of the input transistor (MN1, N11; N1), and that at least one input transistor (MP1; P12; P2) of the input transistor arrangement of the second current mirror (MP1, MP2; P11, P12, P21 bis P26; P1 to P10) is connected as a diode. 5. Bipolare Stromquelle nach Anspruch 1 bis 4, da­durch gekennzeichnet, daß die Transistoren der Stromspiegel als Kaskode-Transistor­stufen (N11, N12, N21, N22, N31 bis N36, P11, P12, P21 bis P26) ausgebildet sind.5. Bipolar current source according to claim 1 to 4, characterized in that the transistors of the current mirror are designed as cascode transistor stages (N11, N12, N21, N22, N31 to N36, P11, P12, P21 to P26). 6. Bipolare Stromquelle nach Anspruch 1 bis 4, da­durch gekennzeichnet, daß die Transistoren der Stromspiegel als Wilson-Stromquelle ausgebildet sind.6. Bipolar current source according to claim 1 to 4, characterized in that the transistors of the current mirror are designed as a Wilson current source. 7. Bipolare Stromquelle nach Anspruch 1 bis 4, da­durch gekennzeichnet, daß die Transistoren der Stromspiegel als Improved-Wilson-­Stromquelle (N1 bis N12, P1 bis P12) ausgebildet sind.7. Bipolar current source according to claim 1 to 4, characterized in that the transistors of the current mirror as an Improved Wilson current source (N1 to N12, P1 to P12) are formed. 8. Bipolare Stromquelle nach Anspruch 1 bis 7, da­durch gekennzeichnet, daß den Steueranschlüsse der Ausgangstransistoranordnung (MN3, MP2; N5 bis N10, P5 bis P10) jeweils der Ausgangskreis eines Transistors (MP3, MN5; MP3, MP31, MN5, MN51) vor­geschaltet und den Steueranschlüssen und den speise­spannungsseitigen Ausgangsanschlüssen der Ausgangs­transistoranordnung (MN3, MP2; N5 bis N10, P5 bis P10) jeweils der Ausgangskreis eines Transistors (MN4, MP4; MN4, MN41, MP4, MP41) parallel geschaltet ist.8. Bipolar current source according to claim 1 to 7, characterized in that the control connections of the output transistor arrangement (MN3, MP2; N5 to N10, P5 to P10) each have the output circuit of a transistor (MP3, MN5; MP3, MP31, MN5, MN51) connected upstream and the control connections and the supply voltage-side output connections of the output transistor arrangement (MN3, MP2; N5 to N10, P5 to P10) each have the output circuit of a transistor (MN4, MP4; MN4, MN41, MP4, MP41) connected in parallel. 9. Bipolare Stromquelle nach Anspruch 1 bis 8, da­durch gekennzeichnet, daß die vorgeschalteten Transistoren (MP3, MN5; MP3, MP31, MN5, MN51) vom entgegengesetzten Typ und die parallelge­schalteten (MN4, MP4; MN4, MN41, MP4, MP41) vom glei­chen Typ wie die zugehörigen Ausgangstransistoren (MN3, MP2; N5 bis N10, P5 bis P10) sind und ihre Steueran­schlüsse mit einer gemeinsamen Steuerklemme (VZ) verbun­den sind.9. Bipolar current source according to claim 1 to 8, characterized in that the upstream transistors (MP3, MN5; MP3, MP31, MN5, MN51) of the opposite type and the parallel connected (MN4, MP4; MN4, MN41, MP4, MP41) from are of the same type as the associated output transistors (MN3, MP2; N5 to N10, P5 to P10) and their control connections are connected to a common control terminal (VZ). 10. Bipolare Stromquelle nach Anspruch 1 bis 9, da­durch gekennzeichnet, daß in je­dem Stromapiegel jeweils nur ein Zweig der Steueran­schlüsse der Ausgangstransistoranordnung (N31 bis N36, P21 bis P26; N5 bis N10, P5 bis P10; Fig. 3) gemäß den Ansprüchen 8 und 9 ausgestaltet ist.10. Bipolar current source according to claim 1 to 9, characterized in that in each current mirror only one branch of the control terminals of the output transistor arrangement (N31 to N36, P21 to P26; N5 to N10, P5 to P10; Fig. 3) according to claims 8 and 9 is designed. 11. Bipolare Stromquelle nach Anspruch 1 bis 10, da­durch gekennzeichnet, daß die Spie­geltransistoranordnung (MN2; N21, N22; N3, N4) des ersten Stromspiegels (MN1 bis MN3; N11, N12, N31 bis N36; N1 bis N10) mit der Eingangstransistoranordnung (MP1; P11, P12, P1, P2) des zweiten Stromspiegels (MP1, MP2; P11, P12, P21 bis P26; P1 bis P10) über wenigstens einen, ins­besondere zwei gleiche Widerstände verbunden ist.11. Bipolar current source according to claim 1 to 10, characterized in that the mirror transistor arrangement (MN2; N21, N22; N3, N4) of the first current mirror (MN1 to MN3; N11, N12, N31 to N36; N1 to N10) with the input transistor arrangement (MP1; P11, P12, P1, P2) of the second current mirror (MP1, MP2; P11, P12, P21 to P26; P1 to P10) is connected via at least one, in particular two, identical resistors. 12. Bipolare Stromquelle nach Anspruch 1 bis 11, da­durch gekennzeichnet, daß die Transistoren der Stromspiegel im gleichen Arbeitspunkt betrieben werden.12. Bipolar current source according to claim 1 to 11, characterized in that the transistors of the current mirror are operated at the same operating point. 13. Bipolare Stromquelle nach Anspruch 1 bis 12, ge­kennzeichnet durch Ausbildung mit komple­mentären Metalloxid-Halbleitertransistoren.13. Bipolar current source of claim 1 to 12, characterized by forming complementary metal oxide semiconductor transistors.
EP86112708A 1985-09-30 1986-09-15 Switchable bipolar current source Expired - Lifetime EP0226721B1 (en)

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DE3687161D1 (en) 1993-01-07
ATE82808T1 (en) 1992-12-15
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