EP0226721A1 - Switchable bipolar current source - Google Patents
Switchable bipolar current source Download PDFInfo
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- EP0226721A1 EP0226721A1 EP86112708A EP86112708A EP0226721A1 EP 0226721 A1 EP0226721 A1 EP 0226721A1 EP 86112708 A EP86112708 A EP 86112708A EP 86112708 A EP86112708 A EP 86112708A EP 0226721 A1 EP0226721 A1 EP 0226721A1
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- 229910044991 metal oxide Inorganic materials 0.000 claims description 7
- 150000004706 metal oxides Chemical class 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000011144 upstream manufacturing Methods 0.000 claims 2
- 230000000295 complement effect Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
Definitions
- the invention relates to a bipolar current source according to the preamble of patent claim 1.
- the invention is based on the object of specifying a reference current source which can be switched in polarity and whose reference current is adjustable.
- Embodiments of the inventive concept are characterized in the subclaims.
- the circuit according to the invention is supplied by a voltage lying between two terminals VDD and VSS of a supply voltage source.
- the circuit contains a first current mirror with metal oxide semiconductor transistors of the n-channel type and a second current mirror with metal oxide Hall conductor transistors of the p-channel type, which are connected in series and whose output transistors are controlled alternately via transistor switches.
- a current Io is fed into the first current mirror via a terminal SE.
- This first current mirror contains the input transistor MN1, which is connected as a diode, the mirror transistor MN2 and the output transistor MN3. While the gates of the transistors MN1 and MN2 are connected directly to one another and to the input terminal SE, the output circuit of a transistor MP3 lies between the gate of the transistor MN3.
- the connections of the transistors MN1, MN2 and MN3 serving as source are connected to the terminal VSS of the supply voltage source.
- the output circuit of a transistor MN4 is located in front of the gate of the transistor MN3 and the terminal VSS of the supply voltage source.
- the output circuits of transistors MP1 and MP2 of the second current mirror are in series with the output circuits of transistors MN2 and MN3.
- the gate of transistor MP1 is directly connected to the junction of the output circuits Transistors MN2 and MP1 and connected to the gate of transistor MP2 via the output circuit of a transistor MN5.
- the connections of the transistors of the second current mirror which serve as the source are connected to the terminal VDD of the supply voltage source.
- the gate of transistor MP2 is also connected to terminal VDD across the output circuit of transistor MP4.
- the terminal SA for the current output of the circuit is located at the connection point of the output circuits of the two output transistors MN3 and MP2.
- the transistors MN4 and MN5 are in the exemplary embodiment of the n-channel type and the transistors MP3 and MP4 of the p-channel type; the gates of the latter four transistors are connected to one another at a terminal VZ.
- the current Io flowing into the circuit via the terminal SE is first reflected by the transistor MN1 connected as a diode into the mirror transistor MN2 and thus also flows through the input transistor of the second current mirror MP1.
- the transistors MN4 and MN5 are now blocked and the transistors MP3 and MP4 are switched to the conductive state or vice versa. It is essential to the invention that the output transistors of the two current mirrors can be switched off, in particular alternately, for which purpose other switch arrangements or other transistor types can also be used.
- the transistor MP3 conducts and the transistor MP4 blocks.
- the input current Io is then mirrored into the transistor MN3 in accordance with the transmission ratio of the first current mirror, ie essentially in accordance with the ratio of channel width to channel length of the transistor MN3 with respect to the transistor MN1.
- the through the transistors MN2 and Current flowing in MP1 has no influence on the output current of the circuit, since transistor MN5 blocks and transistor MP4 conducts at negative potential at terminal VZ, so that output transistor MP2 of the second current mirror is blocked.
- the situation is exactly the opposite, i.e. the transistor MP3 blocks and the transistor MN4 conducts, so that the output transistor MN3 safely blocks.
- the input current Io is first mirrored into the transistor MN2 according to the conversion ratio of the transistors MN2 to MN1 of the first current mirror.
- This current which then also flows through the transistor MP1, is calculated in accordance with the transmission ratio of the second current mirror, i.e. mirrored into transistor MP2 according to the ratio of transistors MP2 to MP1.
- the reference current flowing into output terminal SA is either negative or positive.
- FIG. 2 shows another embodiment of the input circuit of the switchable bipolar current source according to FIG. 1.
- the output circuit of the transistor MN1 is connected to the terminal serving as drain via a resistor R with a terminal GND for connecting a reference potential.
- the connection of this transistor serving as the source lies at the pole VSS of the supply voltage source.
- the gate of transistor MN1 and thus the gate of transistor MN2 and a connection of the output circuit of transistor MP3 is at the output of an operational amplifier OP, the inverting input of which is connected to a terminal VREF Connection of a reference potential and its non-inverting input is connected to the connection point of the output circuit of the transistor MN1 and the resistor R.
- the rest of the circuit is then designed according to the invention in accordance with FIG. 1.
- the input current Io to be mirrored and flowing through the transistor MN1 is decoupled from the output of the operational amplifier OP via the amplifier via the transistor MN1 to the input of the operational amplifier and is thus kept constant.
- the transistors of the current mirrors can be designed, for example, according to the cascode principle or according to the Wilson or Improved Wilson principle.
- FIG. 3 shows a circuit operating according to the cascode principle with an input circuit according to FIG. 2.
- the transistors MN1, MN2 and MP1 according to FIG. 1 are connected in series by two transistors N11 and N12, N21 and N22 as well as P11 and P12 replaced.
- Gate and drain connections of transistors N12, P11 and P12 are each connected to one another.
- the transistors N11 and N12 are driven with an input circuit according to FIG. 2.
- the output transistors MN3 and MP2 according to FIG. 1 are replaced by the parallel connection of three, each of two transistors connected in series.
- the drain connections connected to a common node form the circuit output and are connected to the terminals 5A sets.
- the jointly controlled gates of N11 and N12 are connected to the gates of N31, N33 and N35 via the output circuit of MP3.
- the gate of P12 is connected to the gates of P22, P24 and P26 via the output circuit of MN5.
- the transistors N12, N22, N32, N34, N36 on the one hand and P11, P21, P23 and P25 on the other hand each have common gate control.
- FIG. 3 can be operated with only one switch combination MN4, MN5, MP3, MP4 according to FIG. 1, which acts on only one gate circuit in each case.
- the series connection of the resistors RN and RG lying between the drain connections of N21 and P12 brings about a symmetrization of the circuit, ie the same operating points or the same drain-source voltages of the current mirror transistors when the load is connected from the terminal SA to the reference terminal GND. Then the connection point between RN and RG is virtually at the reference potential.
- the reference output current can be increased in accordance with the changed transmission ratio of the current mirror with the same dimensioning of the transistors. If one chooses the ohmic load to be switched by the terminal SA against the reference terminal GND according to the translation of the current level smaller than the resistance R, then the voltage drops across the load and R are equal.
- FIG. 4 shows an exemplary embodiment according to the invention of a circuit working according to the Improved Wilson principle with an input circuit according to FIG. 2.
- a circuit according to this principle enables the same drain-source voltages of the transistors by one versus one Wilson current source additional transistor connected as a diode.
- the circuit according to FIG. 4 results from the circuit according to FIG. 3 with the changes listed below, the reference symbols of the current source transistors having been changed.
- the drain-gate connections of N12 and P11 (FIG. 3) are omitted for N2 and P1 (FIG. 4), but drain-gate connections are made for N22, N32, N34, N36, P21, P23 and P25 (FIG. 3) Connections are provided so that the elements N4, N6, N8, N10, P5, P7 and P9 (FIG. 4) result.
- the not yet switched gate circuit of the output transistors is provided with switching transistors MN41, MN51, MP31 and MP41 which can be controlled by terminal VZ. which in this order correspond to the transistors MN4, MN5, MP3 and MP4 for the other gate circuit.
- the series connection of the output circuits of two transistors P3 and P4 and a resistor RG are connected from the terminal VDD to the reference terminal GND.
- the drain and gate of P3 are connected to each other and to the gate of P1 and the gate of P4 is connected to the gate of P2.
- This arrangement serves to symmetrize the circuit in order to ensure the same operating points for all transistors.
- the resistors RN and RP and R and an ohmic load to be switched by the terminal SA against the reference potential also belong, in accordance with the explanations given in FIG. 3, to ensure the same operating points for the transistors.
- circuits according to the invention shown in FIGS. 1 to 4 as exemplary embodiments contain metal oxide semiconductor transistors, the letters N or P of the reference symbols relating to the channel type.
- a circuit construction with metal oxide semiconductor transistors of another type is encompassed by the teaching of the invention.
- this circuit can also be implemented with the aid of bipolar transistors.
- there is the possibility of increasing the output reference current with simple means in that further metal oxide transistors are connected in parallel with the output transistors, taking into account the channel type, or the essentially current-determining ratio of channel width Channel length is increased.
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Abstract
Die schaltbare bipolare Stromquelle enthält die Kombination zweier hintereinander geschalteter konventioneller Stromspiegel (MN1, MN2, MN3; MP1, MP2), die vom entgegengesetzten Typ sind und deren Ausgangstransistoren (MN3, MP2) über Transistorschalter (MN4, MP3, MP4, MN5) wechselweise angesteuert werden, so daß am Ausgang (SA) abhängig vom Schaltzustand (VZ) ein positiver oder negativer Referenzstrom zur Verfügung steht.The switchable bipolar current source contains the combination of two series-connected conventional current mirrors (MN1, MN2, MN3; MP1, MP2), which are of the opposite type and whose output transistors (MN3, MP2) are controlled alternately via transistor switches (MN4, MP3, MP4, MN5) so that a positive or negative reference current is available at the output (SA) depending on the switching state (VZ).
Description
Die Erfindung betrifft eine bipolare Stromquelle nach dem Oberbegriff des Patentanspruchs 1.The invention relates to a bipolar current source according to the preamble of patent claim 1.
Stromquellen, die einen positiven oder negativen Ausgangsstrom liefern können, sind bekannt und beispielsweise in dem Buch "Halbleiter-Schaltungstechnik" von U. Tietze, Ch. Schenk, Springer-Verlag, Berlin, Heidelberg, New York, 1980, Seite 54 folgende beschrieben. Eine dort angegebene Stromquelle liefert einen Ausgangsstrom, der proportional zu einer angelegten Eingangsspannung ist. Für einen Anwendungsfall, der entweder einen positiven oder negativen Referenzstrom erfordert, ist eine Lösung mit einer Stromquelle für den positiven und einer Stromquelle für den negativen Referenzstrom mit nachfolgender Multiplexschaltung üblich.Current sources which can supply a positive or negative output current are known and are described, for example, in the book "Semiconductor Circuit Technology" by U. Tietze, Ch. Schenk, Springer-Verlag, Berlin, Heidelberg, New York, 1980, page 54, below. A current source specified there provides an output current that is proportional to an applied input voltage. For an application that requires either a positive or negative reference current, a solution with a current source for the positive and a current source for the negative reference current with subsequent multiplexing is common.
Der Erfindung liegt die Aufgabe zugrunde, eine in der Polarität umschaltbare Referenzstromquelle anzugeben, deren Referenzstrom einstellbar ist.The invention is based on the object of specifying a reference current source which can be switched in polarity and whose reference current is adjustable.
Diese Aufgabe wird bei einer bipolaren Stromquelle der eingangs genannten Art erfindungsgemäß durch die Merkmale des kennzeichnenden Teils des Patentanspruchs 1 gelöst.This object is achieved according to the invention in a bipolar current source of the type mentioned at the outset by the features of the characterizing part of patent claim 1.
Ausgestaltungen des Erfindungsgedankens sind in Unteransprüchen gekennzeichnet.Embodiments of the inventive concept are characterized in the subclaims.
Die Erfindung wird im folgenden anhand von in den Figuren der Zeichnung dargestellten Ausführungsbeispielen näher erläutert. Gleiche Elemente sind mit gleichen Bezugszeichen versehen.The invention is explained in more detail below with reference to exemplary embodiments shown in the figures of the drawing. The same elements are provided with the same reference symbols.
Es zeigt:
- Fig. 1 ein Schaltbild einer erfindungsgemäßen schaltbaren bipolaren Stromquelle,
- Fig. 2 ein Ausführungsbeispiel einer Eingangsschaltung für eine erfindungsgemäße schaltbare bipolare Stromquelle,
- Fig. 3 ein Schaltbild einer nach dem Kaskode-Prinzip arbeitenden erfindungsgemäßen Stromquelle.
- Fig. 4 ein Schaltbild einer nach dem Improved-Wilson-Prinzip arbeitenden erfindungsgemäßen Stromquelle.
- 1 is a circuit diagram of a switchable bipolar current source according to the invention,
- 2 shows an embodiment of an input circuit for a switchable bipolar current source according to the invention,
- Fig. 3 is a circuit diagram of a current source according to the invention working on the cascode principle.
- Fig. 4 is a circuit diagram of a power source according to the invention working according to the Improved Wilson principle.
Gemäß Fig. 1 wird die erfindungsgemäße Schaltung von einer zwischen zwei Klemmen VDD und VSS einer Speisespannungsquelle liegenden Spannung versorgt. Die Schaltung enthält einen ersten Stromspiegel mit Metalloxid-Halbleitertransistoren vom n-Kanal-Typ und einen zweiten Stromspiegel mit Metalloxid-Hallbleitertransistoren vom p-Kanal-Typ, die hintereinander geschaltet sind und deren Ausgangstransistoren über Transistorschalter wechselweise angesteuert werden. In den ersten Stromspiegel wird über eine Klemme SE ein Strom Io eingespeist. Dieser erste Stromspiegel enthält den Eingangstransistor MN1, der als Diode geschaltet ist, den Spiegeltransistor MN2 und den Ausgangstransistor MN3. Während die Gates der Transistoren MN1 und MN2 direkt miteinander und mit der Eingangsklemme SE ver-bunden sind, liegt zwischen dem Gate des Transistors MN3 der Ausgangskreis eines Transistors MP3. Die als Source dienenden Anschlüsse der Transistoren MN1, MN2 und MN3 sind mit der Klemme VSS der Speisespannungsquelle verbunden. Zusätzlich liegt vor dem Gate des Transistors MN3 und der Klemme VSS der Speisespannungsquelle der Ausgangskreis eines Transistors MN4.1, the circuit according to the invention is supplied by a voltage lying between two terminals VDD and VSS of a supply voltage source. The circuit contains a first current mirror with metal oxide semiconductor transistors of the n-channel type and a second current mirror with metal oxide Hall conductor transistors of the p-channel type, which are connected in series and whose output transistors are controlled alternately via transistor switches. A current Io is fed into the first current mirror via a terminal SE. This first current mirror contains the input transistor MN1, which is connected as a diode, the mirror transistor MN2 and the output transistor MN3. While the gates of the transistors MN1 and MN2 are connected directly to one another and to the input terminal SE, the output circuit of a transistor MP3 lies between the gate of the transistor MN3. The connections of the transistors MN1, MN2 and MN3 serving as source are connected to the terminal VSS of the supply voltage source. In addition, the output circuit of a transistor MN4 is located in front of the gate of the transistor MN3 and the terminal VSS of the supply voltage source.
In Serie zu den Ausgangskreisen der Transistoren MN2 und MN3 liegen die Ausgangskreise der Transistoren MP1 und MP2 des zweiten Stromspiegels. Das Gate des Transistors MP1 ist direkt mit dem Verbindungspunkt der Ausgangskreise der Transistoren MN2 und MP1 und über den Ausgangskreis eines Transistors MN5 mit dem Gate des Transistors MP2 verbunden. Die als Source dienenden Anschlüsse der Transistoren des zweiten Stromspiegels sind mit der Klemme VDD der Speisespannungsquelle verbunden. Das Gate des Transistors MP2 liegt über dem Ausgangskreis eines Transistors MP4 ebenfalls an der Klemme VDD. Am Verbindungspunkt der Ausgangskreise der beiden Ausgangstransistoren MN3 und MP2 liegt die Klemme SA für den Stromausgang der Schaltung. Die Transistoren MN4 und MN5 sind im Ausfhrungsbeispiel vom n-Kanal-Typ und die Transistoren MP3 und MP4 vom p-Kanal-Typ; die Gates dieser letztgenannten vier Transistoren sind miteinander an einer Klemme VZ angeschlossen.The output circuits of transistors MP1 and MP2 of the second current mirror are in series with the output circuits of transistors MN2 and MN3. The gate of transistor MP1 is directly connected to the junction of the output circuits Transistors MN2 and MP1 and connected to the gate of transistor MP2 via the output circuit of a transistor MN5. The connections of the transistors of the second current mirror which serve as the source are connected to the terminal VDD of the supply voltage source. The gate of transistor MP2 is also connected to terminal VDD across the output circuit of transistor MP4. The terminal SA for the current output of the circuit is located at the connection point of the output circuits of the two output transistors MN3 and MP2. The transistors MN4 and MN5 are in the exemplary embodiment of the n-channel type and the transistors MP3 and MP4 of the p-channel type; the gates of the latter four transistors are connected to one another at a terminal VZ.
Der über die Klemme SE in die Schaltung fließende Strom Io wird vom als Diode geschalteten Transistor MN1 zunächst in den Spiegeltransistor MN2 gespiegelt und fließt damit auch durch den Eingangstransistor des zweiten Stromspiegels MP1. Abhängig vom Vorzeichen eines an der Klemme VZ liegenden Potentials werden nun entweder die Transistoren MN4 und MN5 gesperrt und die Transistoren MP3 und MP4 in den leitenden Zustand geschaltet oder paarweise umgekehrt. Erfindungswesentlich ist, daß die Ausgangstransistoren der beiden Stromspiegel abschaltbar sind, insbesondere wechselweise, wozu auch andere Schalteranordnungen oder andere Transistortypen dienen können.The current Io flowing into the circuit via the terminal SE is first reflected by the transistor MN1 connected as a diode into the mirror transistor MN2 and thus also flows through the input transistor of the second current mirror MP1. Depending on the sign of a potential at the terminal VZ, either the transistors MN4 and MN5 are now blocked and the transistors MP3 and MP4 are switched to the conductive state or vice versa. It is essential to the invention that the output transistors of the two current mirrors can be switched off, in particular alternately, for which purpose other switch arrangements or other transistor types can also be used.
Bei einem negativen Potential an der Klemme VZ leitet der Transistor MP3 und der Transistor MP4 sperrt. Der Eingangsstrom Io wird dann entsprechend dem Übersetzungsverhältnis des ersten Stromspiegels, d.h. im wesentlichen entsprechend dem Verhältnis von Kanalweite zu Kanallänge des Transistors MN3 bezogen auf den Transistor MN1 in den Transistor MN3 gespiegelt. Der gleichzeitig durch die Transistoren MN2 und MP1 fließende Strom hat auf den Ausgangsstrom der Schaltung keinen Einfluß, da bei negativem Potential an der Klemme VZ der Transistor MN5 sperrt und der Transistor MP4 leitet, so daß der Ausgangstransistor MP2 des zweiten Stromspiegels gesperrt wird.If the potential at the terminal VZ is negative, the transistor MP3 conducts and the transistor MP4 blocks. The input current Io is then mirrored into the transistor MN3 in accordance with the transmission ratio of the first current mirror, ie essentially in accordance with the ratio of channel width to channel length of the transistor MN3 with respect to the transistor MN1. The through the transistors MN2 and Current flowing in MP1 has no influence on the output current of the circuit, since transistor MN5 blocks and transistor MP4 conducts at negative potential at terminal VZ, so that output transistor MP2 of the second current mirror is blocked.
Bei einem positiven Potential an der Klemme VZ sind die Verhältnisse genau umgekehrt, d.h. der Transistor MP3 sperrt und der Transistor MN4 leitet, so daß der Ausgangstransistor MN3 sicher sperrt. Da andererseits in diesem Fall der Transistor MN5 leitet und der Transistor MP4 gesperrt ist, wird der Eingangsstrom Io zunächst gemäß dem Übersetzungsverhältnis der Transistoren MN2 zu MN1 des ersten Stromspiegels in den Transistor MN2 gespiegelt. Dieser dann ebenfalls durch den Transistor MP1 fließende Strom wird gemäß dem Übersetzungsverhältnis des zweiten Stromspiegels, d.h. gemäß dem Übersetzungsverhältnis der Transistoren MP2 zu MP1 in den Transistor MP2 gespiegelt. Abhängig vom Potential der Klemme VZ ist damit der in die Ausgangsklemme SA fließende Referenzstrom entweder negativ oder positiv.With a positive potential at terminal VZ, the situation is exactly the opposite, i.e. the transistor MP3 blocks and the transistor MN4 conducts, so that the output transistor MN3 safely blocks. On the other hand, since in this case the transistor MN5 conducts and the transistor MP4 is blocked, the input current Io is first mirrored into the transistor MN2 according to the conversion ratio of the transistors MN2 to MN1 of the first current mirror. This current, which then also flows through the transistor MP1, is calculated in accordance with the transmission ratio of the second current mirror, i.e. mirrored into transistor MP2 according to the ratio of transistors MP2 to MP1. Depending on the potential of terminal VZ, the reference current flowing into output terminal SA is either negative or positive.
In Fig. 2 ist eine andere Ausgestaltung der Eingangsschaltung der erfindungsgemäßen schaltbaren bipolaren Stromquelle nach Fig. 1 angegeben. Der Ausgangskreis des Transistors MN1 ist mit dem als Drain dienenden Anschluß über einen Widerstand R mit einer Klemme GND zum Anschluß eines Bezugspotentials verbunden. Der als Source dienende Anschluß dieses Transistors liegt am Pol VSS der Versorgungsspannungsquelle. Das Gate des Transistors MN1 und damit das Gate des Transistors MN2 und ein Anschluß des Ausgangskreises des Transistors MP3 liegt am Ausgang eines Operationsverstärkers OP, dessen invertierender Eingang mit einer Klemme VREF zum Anschluß eines Referenzpotentials und dessen nichtinvertierender Eingang mit dem Verbindungspunkt des Ausgangskreises des Transistors MN1 und des Widerstandes R verbunden ist. Die übrige Schaltung ist dann erfindungsgemäß entsprechend Fig. 1 ausgeführt. Gemäß dem an der Klemme VREF liegenden Referenzpotential wird der zu spiegelnde, durch den Transistor MN1 fließende Eingangsstrom Io vom Ausgang des Operationsverstärkers OP über den sverstärkers über den Transistor MN1 auf den Eingang des Operationsverstärkers gegengekoppelt und somit konstant gehalten.FIG. 2 shows another embodiment of the input circuit of the switchable bipolar current source according to FIG. 1. The output circuit of the transistor MN1 is connected to the terminal serving as drain via a resistor R with a terminal GND for connecting a reference potential. The connection of this transistor serving as the source lies at the pole VSS of the supply voltage source. The gate of transistor MN1 and thus the gate of transistor MN2 and a connection of the output circuit of transistor MP3 is at the output of an operational amplifier OP, the inverting input of which is connected to a terminal VREF Connection of a reference potential and its non-inverting input is connected to the connection point of the output circuit of the transistor MN1 and the resistor R. The rest of the circuit is then designed according to the invention in accordance with FIG. 1. In accordance with the reference potential at the terminal VREF, the input current Io to be mirrored and flowing through the transistor MN1 is decoupled from the output of the operational amplifier OP via the amplifier via the transistor MN1 to the input of the operational amplifier and is thus kept constant.
Eine andere Ausgestaltung einer erfindungsgemäßen Schaltung ist vorgesehen, wenn der Innenwiderstand der Stromquellen erhöht werden soll. Dazu können die Transistoren der Stromspiegel beispielsweise nach dem Kaskode-Prinzip oder nach dem Wilson- oder Improved-Wilson-Prinzip ausgebildet sein.Another embodiment of a circuit according to the invention is provided if the internal resistance of the current sources is to be increased. For this purpose, the transistors of the current mirrors can be designed, for example, according to the cascode principle or according to the Wilson or Improved Wilson principle.
Fig. 3 zeigt eine nach dem Kaskode-Prinzip arbeitende Schaltung mit einer Eingangsschaltung gemäß Fig. 2. In ihr sind die Transistoren MN1,MN2 und MP1 gemäß Fig. 1 durch die Reihenschaltung jeweils zweier Transistoren N11 und N12, N21 und N22 sowie P11 und P12 ersetzt.FIG. 3 shows a circuit operating according to the cascode principle with an input circuit according to FIG. 2. In it, the transistors MN1, MN2 and MP1 according to FIG. 1 are connected in series by two transistors N11 and N12, N21 and N22 as well as P11 and P12 replaced.
Gate- und Drainanschlüsse der Transistoren N12, P11 und P12 sind jeweils miteinander verbunden. Die Ansteuerung der Transistoren N11 und N12 erfolgt mit einer Eingangsschaltung gemäß Fig. 2.Gate and drain connections of transistors N12, P11 and P12 are each connected to one another. The transistors N11 and N12 are driven with an input circuit according to FIG. 2.
Die Ausgangstransistoren MN3 und MP2 gemäß Fig. 1 sind durch die Parallelschaltung von drei, jeweils aus zwei in Reihe geschalteten Transistoren ersetzt. Die auf einen gemeinsamen Knotenpunkt geschalteten Drainanschlüsse bilden den Schaltungsausgang und sind an die Klemmen 5A ge legt. Die gemeinsam angesteuerten Gates von N11 und N12 sind über den Ausgangskreis von MP3 an die Gates von N31, N33 und N35 angeschlossen. Ebenso ist das Gate von P12 über den Ausgangskreis von MN5 mit den Gates von P22, P24 und P26 verbunden. Jeweils gemeinsame Gateansteuerung besitzen die Transistoren N12, N22, N32, N34, N36 einerseits und P11, P21, P23 und P25 andererseits. Erfindungsgemäß läßt sich die Kaskode-Schaltung gemäßt Fig. 3 mit nur einer Schalterkombination MN4, MN5, MP3, MP4 gemäß Fig. 1, die auf jeweils nur einen Gatekreis wirkt, betreiben. Die zwischen den Drainanschlüssen von N21 und P12 liegende Reihenschaltung der Widerstände RN und RG bewirkt eine Symmetrierung der Schaltung, d.h. gleiche Arbeitspunkte bzw. gleiche Drain-Source-Spannungen der Stromspiegeltransistoren, wenn die Last von der Klemme SA gegen die Bezugsklemme GND geschaltet wird. Dann liegt der Verbindungspunkt von RN mit RG virtuell auf dem Bezugspotential.The output transistors MN3 and MP2 according to FIG. 1 are replaced by the parallel connection of three, each of two transistors connected in series. The drain connections connected to a common node form the circuit output and are connected to the terminals 5A sets. The jointly controlled gates of N11 and N12 are connected to the gates of N31, N33 and N35 via the output circuit of MP3. Likewise, the gate of P12 is connected to the gates of P22, P24 and P26 via the output circuit of MN5. The transistors N12, N22, N32, N34, N36 on the one hand and P11, P21, P23 and P25 on the other hand each have common gate control. According to the invention, the cascode circuit according to FIG. 3 can be operated with only one switch combination MN4, MN5, MP3, MP4 according to FIG. 1, which acts on only one gate circuit in each case. The series connection of the resistors RN and RG lying between the drain connections of N21 and P12 brings about a symmetrization of the circuit, ie the same operating points or the same drain-source voltages of the current mirror transistors when the load is connected from the terminal SA to the reference terminal GND. Then the connection point between RN and RG is virtually at the reference potential.
Durch Parallelschalten mehrerer Ausgangskreise läßt sich bei gleicher Dimmensionierung der Transistoren der Referenz-Ausgangsstrom entsprechend dem geänderten Übersetzungsverhältnis des Stromspiegels vergrößern. Wählt man die von der Klemme SA gegen die Bezugsklemme GND zu schaltende ohmsche Last entsprechend der Übersetzung des Stromspiegels kleiner als den Widerstand R, dann sind die Spannungsabfälle über der Last und R gleich groß.By connecting several output circuits in parallel, the reference output current can be increased in accordance with the changed transmission ratio of the current mirror with the same dimensioning of the transistors. If one chooses the ohmic load to be switched by the terminal SA against the reference terminal GND according to the translation of the current level smaller than the resistance R, then the voltage drops across the load and R are equal.
Fig. 4 zeigt ein erfindungsgemäßes Ausführungsbeispiel einer nach dem Improved-Wilson-Prinzip arbeitenden Schaltung mit einer Eingangsschaltung gemäß Fig. 2. Eine Schaltung nach diesem Prinzip ermöglicht gleiche Drain-Source-Spannungen der Transistoren durch einen gegenüber einer Wilson-Stromquelle zusätzlichen, als Diode geschalteten Transistor.FIG. 4 shows an exemplary embodiment according to the invention of a circuit working according to the Improved Wilson principle with an input circuit according to FIG. 2. A circuit according to this principle enables the same drain-source voltages of the transistors by one versus one Wilson current source additional transistor connected as a diode.
Die Schaltung gemäß Fig. 4 ergibt sich mit nachstehend aufgeführten Veränderungen aus der Schaltung gemäß Fig. 3, wobei die Bezugszeichen der Stromquellentransistoren geändert wurden. Die Drain-Gate-Verbindungen von N12 und P11 (Fig. 3) entfallen für N2 und P1 (Fig. 4) dafür werden bei N22, N32, N34, N36, P21, P23 und P25 (Fig. 3) Drain-Gate-Verbindungen vorgesehen, so daß sich die Elemente N4, N6, N8, N10, P5, P7 und P9 (Fig. 4) ergeben. Zusätzlich wird jeweils der noch nicht geschaltete Gatekreis der Ausgangstransistoren mit von der Klemme VZ steuerbaren Schalttransistoren MN41, MN51, MP31 und MP41 versehen. die in dieser Reihenfolge jeweils den Transistoren MN4, MN5, MP3 und MP4 für den jeweils anderen Gatekreis entsprechen.The circuit according to FIG. 4 results from the circuit according to FIG. 3 with the changes listed below, the reference symbols of the current source transistors having been changed. The drain-gate connections of N12 and P11 (FIG. 3) are omitted for N2 and P1 (FIG. 4), but drain-gate connections are made for N22, N32, N34, N36, P21, P23 and P25 (FIG. 3) Connections are provided so that the elements N4, N6, N8, N10, P5, P7 and P9 (FIG. 4) result. In addition, the not yet switched gate circuit of the output transistors is provided with switching transistors MN41, MN51, MP31 and MP41 which can be controlled by terminal VZ. which in this order correspond to the transistors MN4, MN5, MP3 and MP4 for the other gate circuit.
Zusätzlich ist von der Klemme VDD gegen die Bezugsklemme GND die Reihenschaltung der Ausgangskreise zweier Transistoren P3 und P4 sowie ein Widerstand RG geschaltet. Drain und Gate von P3 sind miteinander und mit dem Gate von P1 und das Gate von P4 ist mit dem Gate von P2 verbunden. Diese Anordnung dient zur Symmetrierung der Schaltung, um gleiche Arbeitspunkte für alle Transistoren zu gewährleisten. Ebenfalls gehören die Widerstände RN und RP sowie R und eine von der Klemme SA gegen das Bezugspotential zu schaltenden ohmsche Last entsprechend den Ausführungen zu Fig. 3 zur Sicherung gleicher Arbeitspunkte für die Transistoren.In addition, the series connection of the output circuits of two transistors P3 and P4 and a resistor RG are connected from the terminal VDD to the reference terminal GND. The drain and gate of P3 are connected to each other and to the gate of P1 and the gate of P4 is connected to the gate of P2. This arrangement serves to symmetrize the circuit in order to ensure the same operating points for all transistors. The resistors RN and RP and R and an ohmic load to be switched by the terminal SA against the reference potential also belong, in accordance with the explanations given in FIG. 3, to ensure the same operating points for the transistors.
Die gemäß den Figuren 1 bis 4 als Ausführungsbeipsiele angeführten erfindungsgemäßen Schaltungen enthalten Metalloxid-Halbleitertransistoren, wobei die Buchstaben N oder P der Bezugszeichen den Kanal-Typ angehen. Ein Schaltungsaufbau mit Metalloxid-Halbleitertransistoren anderen Typ wird von der Lehre der Erfindung umfaßt. Ebensogut läßt sich diese Schaltung jedoch mit Hilfe von bipolaren Transistoren realisieren. Speziell in der Ausführung mit Metalloxid-Halbleiter-Transistoren ergibt sich die Möglichkeit, den Ausgangs- Referenzstrom mit einfachen Mitteln zu vergrößern, indem weitere Metalloxid-Transistoren den Ausgangstransistoren unter Beachtung des Kanaltyps parallel geschaltet werden oder das im wesentlichen den Strom bestimmende Verhältnis von Kanalweite zu Kanallänge vergrößert wird.The circuits according to the invention shown in FIGS. 1 to 4 as exemplary embodiments contain metal oxide semiconductor transistors, the letters N or P of the reference symbols relating to the channel type. A circuit construction with metal oxide semiconductor transistors of another type is encompassed by the teaching of the invention. However, this circuit can also be implemented with the aid of bipolar transistors. Especially in the version with metal oxide semiconductor transistors, there is the possibility of increasing the output reference current with simple means, in that further metal oxide transistors are connected in parallel with the output transistors, taking into account the channel type, or the essentially current-determining ratio of channel width Channel length is increased.
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT86112708T ATE82808T1 (en) | 1985-09-30 | 1986-09-15 | SWITCHABLE BIPOLAR POWER SOURCE. |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3534830 | 1985-09-30 | ||
DE3534830 | 1985-09-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0226721A1 true EP0226721A1 (en) | 1987-07-01 |
EP0226721B1 EP0226721B1 (en) | 1992-11-25 |
Family
ID=6282347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP86112708A Expired - Lifetime EP0226721B1 (en) | 1985-09-30 | 1986-09-15 | Switchable bipolar current source |
Country Status (5)
Country | Link |
---|---|
US (1) | US4740743A (en) |
EP (1) | EP0226721B1 (en) |
JP (1) | JP2646443B2 (en) |
AT (1) | ATE82808T1 (en) |
DE (1) | DE3687161D1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0373471A1 (en) * | 1988-12-16 | 1990-06-20 | STMicroelectronics S.r.l. | Current source circuit with complementary current mirrors |
EP0570820A2 (en) * | 1992-05-20 | 1993-11-24 | Siemens Aktiengesellschaft | Switchable current source circuit and the use of such a circuit in a phase detector |
EP0613072A1 (en) * | 1993-02-12 | 1994-08-31 | Koninklijke Philips Electronics N.V. | Integrated circuit comprising a cascode current mirror |
EP0627820A2 (en) * | 1993-06-02 | 1994-12-07 | Motorola, Inc. | A charge pump with a programmable pump current and system |
EP0642072A1 (en) * | 1993-09-03 | 1995-03-08 | Siemens Aktiengesellschaft | Current mirror |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2765841B2 (en) * | 1987-11-27 | 1998-06-18 | 株式会社日立製作所 | Semiconductor device |
US4825099A (en) * | 1987-12-04 | 1989-04-25 | Ford Microelectronics | Feedback-controlled current output driver having reduced current surge |
US5266887A (en) * | 1988-05-24 | 1993-11-30 | Dallas Semiconductor Corp. | Bidirectional voltage to current converter |
US5519309A (en) * | 1988-05-24 | 1996-05-21 | Dallas Semiconductor Corporation | Voltage to current converter with extended dynamic range |
GB2225910A (en) * | 1988-12-08 | 1990-06-13 | Philips Electronic Associated | Processing sampled analogue electrical signals |
FR2641388B1 (en) * | 1988-12-30 | 1991-03-15 | Radiotechnique Compelec | INTEGRATED CIRCUIT COMPRISING A SWITCHABLE CURRENT GENERATOR |
WO1991018338A1 (en) * | 1990-05-17 | 1991-11-28 | International Business Machines Corporation | Switchable current source |
USRE42250E1 (en) | 1994-12-29 | 2011-03-29 | Stmicroelectronics, Inc. | Delay circuit and method |
US5936451A (en) * | 1994-12-29 | 1999-08-10 | Stmicroeletronics, Inc. | Delay circuit and method |
KR100218306B1 (en) * | 1996-06-27 | 1999-09-01 | 구본준 | Voltage-current converter |
CN100514250C (en) * | 2000-07-05 | 2009-07-15 | 盛群半导体股份有限公司 | Current output circuit with high current ratio |
DE10065379A1 (en) * | 2000-12-27 | 2002-07-18 | Infineon Technologies Ag | Current mirror circuit |
JP4662698B2 (en) * | 2003-06-25 | 2011-03-30 | ルネサスエレクトロニクス株式会社 | Current source circuit and current setting method |
JP2005100345A (en) * | 2003-08-28 | 2005-04-14 | Rohm Co Ltd | Current control circuit, semiconductor device and imaging device |
DE102008014425B4 (en) * | 2008-03-13 | 2012-03-29 | Atmel Automotive Gmbh | Driver circuit with a snubber network using a current mirror |
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JPS6095620A (en) * | 1983-10-04 | 1985-05-29 | アメリカン テレフオン アンド テレグラフ カンパニー | Electronic circuit for current switch |
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JPS56143026A (en) * | 1980-04-10 | 1981-11-07 | Fujitsu Ltd | Symmetrical type constant current circuit |
JPH0656935B2 (en) * | 1982-04-24 | 1994-07-27 | 日本電装株式会社 | Constant current control circuit |
JPS5990412A (en) * | 1982-11-15 | 1984-05-24 | Nec Corp | Bidirectional constant current driving circuit |
US4583037A (en) * | 1984-08-23 | 1986-04-15 | At&T Bell Laboratories | High swing CMOS cascode current mirror |
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- 1986-09-15 DE DE8686112708T patent/DE3687161D1/en not_active Expired - Lifetime
- 1986-09-15 AT AT86112708T patent/ATE82808T1/en not_active IP Right Cessation
- 1986-09-15 EP EP86112708A patent/EP0226721B1/en not_active Expired - Lifetime
- 1986-09-29 US US06/913,412 patent/US4740743A/en not_active Expired - Lifetime
- 1986-09-29 JP JP61231080A patent/JP2646443B2/en not_active Expired - Lifetime
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US3611171A (en) * | 1969-12-11 | 1971-10-05 | Ibm | Integrated circuit video amplifier |
US3976896A (en) * | 1974-10-29 | 1976-08-24 | The Solartron Electronic Group Limited | Reference voltage sources |
JPS6095620A (en) * | 1983-10-04 | 1985-05-29 | アメリカン テレフオン アンド テレグラフ カンパニー | Electronic circuit for current switch |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0373471A1 (en) * | 1988-12-16 | 1990-06-20 | STMicroelectronics S.r.l. | Current source circuit with complementary current mirrors |
EP0570820A2 (en) * | 1992-05-20 | 1993-11-24 | Siemens Aktiengesellschaft | Switchable current source circuit and the use of such a circuit in a phase detector |
EP0570820A3 (en) * | 1992-05-20 | 1993-12-15 | Siemens Ag | Switchable current source circuit and the use of such a circuit in a phase detector |
EP0613072A1 (en) * | 1993-02-12 | 1994-08-31 | Koninklijke Philips Electronics N.V. | Integrated circuit comprising a cascode current mirror |
EP0627820A2 (en) * | 1993-06-02 | 1994-12-07 | Motorola, Inc. | A charge pump with a programmable pump current and system |
EP0627820A3 (en) * | 1993-06-02 | 1994-12-14 | Motorola, Inc. | A charge pump with a programmable pump current and system |
EP0642072A1 (en) * | 1993-09-03 | 1995-03-08 | Siemens Aktiengesellschaft | Current mirror |
Also Published As
Publication number | Publication date |
---|---|
JP2646443B2 (en) | 1997-08-27 |
JPS6279514A (en) | 1987-04-11 |
US4740743A (en) | 1988-04-26 |
DE3687161D1 (en) | 1993-01-07 |
ATE82808T1 (en) | 1992-12-15 |
EP0226721B1 (en) | 1992-11-25 |
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