EP0201267A2

EP0201267A2 - Row processor for bit-map display

Info

Publication number: EP0201267A2
Application number: EP86303243A
Authority: EP
Inventors: Joseph H. Hubert; Donald J. Eckardt
Original assignee: Tektronix Inc
Current assignee: Tektronix Inc
Priority date: 1985-05-02
Filing date: 1986-04-29
Publication date: 1986-11-12
Also published as: JPS61254984A; EP0201267A3

Abstract

A row processor unit for a bit-map, raster scan display performs per-scan-line frame buffer management functions. A portion of the frame buffer memory which is not used for display contains load/decode parameters. These parameters are accessed by the row processor unit during the horizontal blanking interval and used for display and data movement operations during the refreshing of the following scan line. A pattern memory provides pixel masks for scrolling as well as providing cursor patterns.

Description

Background of the Invention

Field of the Invention.

The present invention relates to frame buffers for raster scan displays, and more particularly to a row processor for a bit-map display which performs per-scan-line display and copy functions.

Description of the Prior Art.

In raster scan displays a frame buffer is used to store a digital representation of an ,image to be displayed. The frame buffer is divided into one or more planes, each plane having a plurality of words, each word representing a plurality of picture elements, or pixels. For a display of 640 pixels across by 480 rows with 16-bit (pixel) frame buffer words, each display is composed of 40 words per row, 19,200 words in all. A display cycle consists of a plurality of horizontal display cycles for each scan line with a plurality of horizontal blanking cycles after each horizontal scan line during the horizontal retrace period of the display. Each cycle consists of a refresh portion during which a word is read from the frame buffer, and an update portion during which data can be written into the frame buffer or data in the frame buffer can be modified.
To move a portion, or block, of the image from one position to another within the display, an operation referred to as bit block transfer (BITBLT) is performed. However, attempts to scroll an image via BITBLT result in tearing, flickering or inchworming distortion of the image. What is desired is a smooth scrolling of an image without such distortion.

SummarY of the Invention

Accordingly, the present invention provides a row processor unit for a bit-map, raster scan display which performs per-scan-line frame buffer management functions. A portion of the frame buffer memory which is not used for display contains load/decode parameters. These parameters are accessed by the row processor unit during the horizontal blanking interval and used for display and data movement operations during the refreshing of the following scan line. A pattern memory provides pixel masks for scrolling as well as providing cursor patterns.
Objects, advantages and novel features of the present invention will be apparent from the following detailed description when read in conjunction with the appended claims and attached drawings.

Brief Description of the Drawings

Fig. 1 is a block diagrammatic view of a frame buffer with a row processor unit according to the present invention.
Fig. 2a-2g is an illustrative view of the row processor unit field within a frame buffer memory.
Fig. 3 is a schematic view of a decoder for the row processor unit.
Fig. 4 is a schematic view of a pattern memory for the row processor unit.
Fig. 5 is a schematic view of a row destination counter for the row processor unit.
Fig. 6 is a block diagrammatic view to illustrate the operation of the row processor unit.
Fig. 7 is a state diagrammatic view of the operation of the row processor unit.

Description of the Preferred Embodiment

Referring now to Fig. 1 a frame buffer 10 is shown having a frame buffer memory 12 with one or more planes (A, B, C, D). For purposes of illustration the frame buffer memory 12 has a 640x480 pixel display bit-map and a row processor unit field 16 which is 112x512 pixels on the A-plane. The remainder of the 1024x512 pixel frame buffer memory 12 may be used for other purposes.
Fig. 2 is illustrative of one frame buffer geometry where each frame buffer word is 16-bits, or 2-bytes, long. A CRT (cathode ray tube) controller 18 provides row and column addresses for the frame buffer memory 12 during refresh display cycles. A frame buffer addressing circuit 20 is situated between the CRT controller 18 and the frame buffer memory 12 for row address selection. A color map 22 receives the pixel display data from the display bit-map 14 as accessed by the CRT controller 18 and outputs a video signal to a display device which includes color information.
A row processor unit 24 received the data contained in the row processor field 16 and decodes such data to perform several functions. A pattern memory 26 contains cursor patterns and scroll masks. The row processor unit 24 selects either a cursor pattern or a scroll mask from the pattern memory 26 by row as the CRT controller 18 clocks through the columns. The column addresses from the CRT controller 18 also are input to the row processor unit 24. The row processor unit 24 accesses the frame buffer addressing circuit 20 as does a display processor, or central processing unit (CPU). The row processor unit 24 also accesses the color map 22 to effect palette color changes or cursor color. A frame buffer state machine 28 acts as a traffic controller and provides the timing signals for the frame buffer 10. The cursor from the pattern memory 26 selected by the row processor unit 24 is input to the color map 22 for output as video data to the display unit.
The row processor unit 24 and pattern memory 26 are shown in greater detail in Figs. 3-5. For illustration reference to the frame buffer words of Figs. 2a-f which make up the row processor field 16 as shown in Fig. 2g is made to describe the circuitry. The A-plane data (APD) from the frame buffer memory 12 is input to a data latch 30 and clocked out for each column clockpulse (CCLK), i.e., once for each frame buffer word. The output from the data latch 30 forms a row processor data (RPD) bus.
A decoder 32 receives as inputs bits 0,1 and 15 of each RPD word, the column count (CC) and most significant bit of the row count (CR9) from the CRT controller 18, a row block transfer enable (ROWBLTEN) signal from the display processor and a row processor strobe (RPSTB) signal from the state machine 28. Bit 15 of each row processor word (words 40-46 for each scan line) is a load bit. Until the column count reaches 40, i.e., is out of the display bit-map area 14, the decoder 32 is inhibited. Also when CR9 is set, equivalent to row 512 and above, which is outside the extent of the frame buffer memory 12, the decoder 32 also is inhibited. When the column and row counts (CC and CR9) indicate that the frame buffer words are within the row processor field 14, bit 15 for each word is checked to see if it is set. If bit 15 is set, the decoder 32 outputs a command for a row function to be performed on the next scan line.
Referring to Figs. 2a-f in sequence an interrupt signal (INTO and/or INT1) is output from the decoder 32 if bit 15 and bit 0 and/or bit 1 is set in word 40. INTO/1 are used to synchronize the row processing unit 24 with the CPU. If bit 15 is set in word 41 a cursor load (CURSORLD) signal is output. For words 42 and 43 a palette load (PALD) signal is output if bit 15 is set, each word referencing one of the bit-planes. If bit 15 is set in word 44, a row block transfer request (ROWBLTRQ) signal is output when bit 0 is also set and a ROWBLTEN signal is input from the display processor. A row block transfer mask load (RBMASKLD) signal is output when bit 15 is set in word 45.
Finally, word 46 provides a row processor counter enable (RPCNTEN) signal when bit 15 is set as well as a row counter load (RCNTLD) signal.
When the load bit is set in one of the row processor words, the parameters in that word are either executed immediately or loaded into registers. The function executed may be for a single scan line, such as the interrupt pulses, INTO, INT1, or may be performed on successive lines using the same parameters until new values are loaded or-the function disabled, such as cursor and scrolling operations. As shown in Fig. 4 when a cursor word (41) is decoded by the decoder 32, the CURSORLD signal clocks the parameter value in bits 0-4 into a cursor register 34. The value in the cursor register 34 is a row address (PROW) for the pattern RAM 26. For each successive scan line during the refresh scan time the pattern at that row is transferred, when the output of the cursor register is enabled by a video enable (VIDEN) signal, to a cursor shift register 36 upon receipt of a shift register load (SRLD) signal from the frame buffer controller (FBC) 28 and the cursor enable (CURSEN) from the cursor register. The dot clock pulses (DCLK) then clock out the cursor to the video display circuit via the color map circuit 22 for display.
For scroll/fill operations the RBMASKLD signal from the decoder 32 clocks the mask pattern value and the plane mask value into a mask register 38. The plane mask value provides an enable signal (APEN, BPEN, CPEN, DPEN) from the mask register 38 to the respective planes, and the mask pattern provides a row address to the pattern RAM 26 when the mask register output is enabled by a row block transfer write (ROWBLTWR) signal from the frame buffer controller 28. A row destination counter 40 is enabled by the RPCNTEN signal and the address destination for the data on the following scan line is loaded into the register by the RCNTLD signal. During the update cycle the ROWBLTWR signal also outputs a frame buffer row address (FR) into which the data of that scan line is rewritten for the pixels in each column specified by the mask pattern. The RPSTB signal, which occurs during every word access, increments the row destination counter 40 during the scroll/fill operation when enabled by RPCNTEN.
Figs. 6 and 7 illustrate the operation of the frame buffer 10. During the horizontal display time each frame buffer word is readout during the refresh time, including the cursor from the pattern RAM 26. Between reading of frame buffer words the frame buffer 10 may be accessed by the CPU. For scroll/fill operations during the refresh cycle the video data readout from the frame buffer memory 12 is latched and held until the update cycle. During the update cycle the video data is rewritten into the frame buffer memory 10 at the location specified by the row destination counter 40 for the pixels indicated by the mask pattern. During the horizontal retrace, or blanking, period the CRT controller 18 continues to increment through the frame buffer memory 10. The words from the RPU field 16 are readout and decoded, and the parameters contained therein are loaded into appropriate registers for execution during the next scan line. Again as in normal display the CPU has access to the frame buffer memory 10 during the update portion of the blanking cycle. At the completion of horizontal retrace the column count is reset to zero and the CRT controller increments the row address to display the next scan line.
Thus, the present invention provides a row processor for a bit-map, raster scan display which uses an unused portion of a frame buffer memory for each scan line to store instructions and parameters which are executed on subsequent scan lines to eliminate image distortion during scroll/fill operations.

Claims

1. A row processor unit for a bit-map, raster scan display comprising:

means for storing parameters on a per-scan-line basis, said storing means being located within an undisplayed portion of a frame buffer memory;

means for decoding and loading said parameters into registers; and

means for executing the functions represented by said parameters on a per-scan-line basis.

2. A row processor unit for a bit-map, raster scan display comprising:

an undisplayed portion of a frame buffer memory within which a plurality of parameter words, each having a specified function and associated parameter values, is stored for execution on a per-scan-line basis;

means for decoding said specific functions and for loading said parameter values into a specified register;

means for storing a plurality of patterns, said patterns being accessed by said parameter values for certain ones of said specified functions; and

means for executing said specified functions according to said parameter values and said patterns on a per-scan-line basis.