EP0198258A3 - Memory means with multiple word read and single word write - Google Patents
Memory means with multiple word read and single word write Download PDFInfo
- Publication number
- EP0198258A3 EP0198258A3 EP86103695A EP86103695A EP0198258A3 EP 0198258 A3 EP0198258 A3 EP 0198258A3 EP 86103695 A EP86103695 A EP 86103695A EP 86103695 A EP86103695 A EP 86103695A EP 0198258 A3 EP0198258 A3 EP 0198258A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- information
- memory
- write
- read
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Bus Control (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Image Input (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US713365 | 1985-03-19 | ||
US06/713,365 US4716545A (en) | 1985-03-19 | 1985-03-19 | Memory means with multiple word read and single word write |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0198258A2 EP0198258A2 (en) | 1986-10-22 |
EP0198258A3 true EP0198258A3 (en) | 1989-09-06 |
EP0198258B1 EP0198258B1 (en) | 1997-08-06 |
Family
ID=24865845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP86103695A Expired - Lifetime EP0198258B1 (en) | 1985-03-19 | 1986-03-19 | Memory means with multiple word read and write |
Country Status (6)
Country | Link |
---|---|
US (1) | US4716545A (en) |
EP (1) | EP0198258B1 (en) |
JP (1) | JP2643928B2 (en) |
AU (1) | AU574905B2 (en) |
CA (1) | CA1256217A (en) |
DE (1) | DE3650642T2 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4912630A (en) * | 1988-07-29 | 1990-03-27 | Ncr Corporation | Cache address comparator with sram having burst addressing control |
JPH02190930A (en) * | 1988-12-29 | 1990-07-26 | Internatl Business Mach Corp <Ibm> | Software instruction executing apparatus |
US5307469A (en) * | 1989-05-05 | 1994-04-26 | Wang Laboratories, Inc. | Multiple mode memory module |
US5261073A (en) * | 1989-05-05 | 1993-11-09 | Wang Laboratories, Inc. | Method and apparatus for providing memory system status signals |
US6564308B2 (en) | 1989-05-05 | 2003-05-13 | Samsung Electronics Co. Ltd. | Multiple mode memory module |
US5146582A (en) * | 1989-06-19 | 1992-09-08 | International Business Machines Corp. | Data processing system with means to convert burst operations into memory pipelined operations |
DE69031658T2 (en) * | 1989-09-11 | 1998-05-20 | Wang Laboratories | DEVICE AND METHOD FOR MAINTENANCE OF CACHE / CENTRAL STORAGE CONSISTENCY |
EP0440456B1 (en) * | 1990-01-31 | 1997-01-08 | Hewlett-Packard Company | Microprocessor burst mode with external system memory |
US5778423A (en) * | 1990-06-29 | 1998-07-07 | Digital Equipment Corporation | Prefetch instruction for improving performance in reduced instruction set processor |
US5278967A (en) * | 1990-08-31 | 1994-01-11 | International Business Machines Corporation | System for providing gapless data transfer from page-mode dynamic random access memories |
US5339399A (en) * | 1991-04-12 | 1994-08-16 | Intel Corporation | Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus |
US5313475A (en) * | 1991-10-31 | 1994-05-17 | International Business Machines Corporation | ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme |
US5752260A (en) * | 1996-04-29 | 1998-05-12 | International Business Machines Corporation | High-speed, multiple-port, interleaved cache with arbitration of multiple access addresses |
US6446198B1 (en) * | 1999-09-30 | 2002-09-03 | Apple Computer, Inc. | Vectorized table lookup |
KR20210031266A (en) * | 2019-09-11 | 2021-03-19 | 삼성전자주식회사 | Interface circuit, memory device, storage device and operation method of the memory device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2030333A (en) * | 1978-08-30 | 1980-04-02 | Int Standard Electric Corp | Part-word Addressing |
US4370712A (en) * | 1980-10-31 | 1983-01-25 | Honeywell Information Systems Inc. | Memory controller with address independent burst mode capability |
EP0109298A2 (en) * | 1982-11-15 | 1984-05-23 | Data General Corporation | Computer memory |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4099231A (en) * | 1975-10-01 | 1978-07-04 | Digital Equipment Corporation | Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle |
US4055851A (en) * | 1976-02-13 | 1977-10-25 | Digital Equipment Corporation | Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle |
US4126897A (en) * | 1977-07-05 | 1978-11-21 | International Business Machines Corporation | Request forwarding system |
US4424561A (en) * | 1980-12-31 | 1984-01-03 | Honeywell Information Systems Inc. | Odd/even bank structure for a cache memory |
US4378591A (en) * | 1980-12-31 | 1983-03-29 | Honeywell Information Systems Inc. | Memory management unit for developing multiple physical addresses in parallel for use in a cache memory |
JPS57167185A (en) * | 1981-04-06 | 1982-10-14 | Nec Corp | Memory circuit |
US4438493A (en) * | 1981-07-06 | 1984-03-20 | Honeywell Information Systems Inc. | Multiwork memory data storage and addressing technique and apparatus |
JPS58105363A (en) * | 1981-12-17 | 1983-06-23 | Fujitsu Ltd | Storage device |
-
1985
- 1985-03-19 US US06/713,365 patent/US4716545A/en not_active Expired - Lifetime
-
1986
- 1986-03-11 AU AU54491/86A patent/AU574905B2/en not_active Ceased
- 1986-03-18 CA CA000504430A patent/CA1256217A/en not_active Expired
- 1986-03-19 JP JP61061958A patent/JP2643928B2/en not_active Expired - Lifetime
- 1986-03-19 DE DE3650642T patent/DE3650642T2/en not_active Expired - Fee Related
- 1986-03-19 EP EP86103695A patent/EP0198258B1/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2030333A (en) * | 1978-08-30 | 1980-04-02 | Int Standard Electric Corp | Part-word Addressing |
US4370712A (en) * | 1980-10-31 | 1983-01-25 | Honeywell Information Systems Inc. | Memory controller with address independent burst mode capability |
EP0109298A2 (en) * | 1982-11-15 | 1984-05-23 | Data General Corporation | Computer memory |
Also Published As
Publication number | Publication date |
---|---|
EP0198258A2 (en) | 1986-10-22 |
JP2643928B2 (en) | 1997-08-25 |
DE3650642T2 (en) | 1998-02-26 |
JPS61217843A (en) | 1986-09-27 |
AU5449186A (en) | 1986-09-25 |
DE3650642D1 (en) | 1997-09-11 |
AU574905B2 (en) | 1988-07-14 |
CA1256217A (en) | 1989-06-20 |
EP0198258B1 (en) | 1997-08-06 |
US4716545A (en) | 1987-12-29 |
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