Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
  • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
  • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
  • H01L29/92—Capacitors having potential barriers
  • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

• Charge storage is a frequently used technique in semiconductor devices and integrated circuits. Examples of devices whose operation depends critically on charge storage are dynamic random access memories, bucket brigade shift registers, and charge coupled imaging devices. Many other kinds of semiconductor devices and integrated circuits also use charge storage. Depletion region charge storage may be accomplished using a physical P-N junction formed by abutting doped P and N regions. However, depletion regions may also be induced, as for example, by means of an MOS capacitor or the like. If a sufficiently large voltage is applied across an MOS capacitor or equivalent, a depletion region akin to that found in a P-N junction is created between the semiconductor surface and the bulk. Such induced depletion regions can equally well be used for charge storage devices.
• reference to storage of charge on junctions is intended to include charge stored in depletion regions whether formed by a permanently doped P-N junction or field induced or by formed by any other means.
• a significant problem that arises in connection with the use of charge storage is that the stored charge is subject to being discharged by minority carriers or electron-hole carrier pairs which reach the depletion region. These free carriers may arise from a number of sources, such as, generation within the junction region, injection from another nearby junction, or diffusion from outside the junction region, i.e., from within the bulk of the underlying semiconductor substrate.
• the result of the discharge is that the information represented by the stored charge decays. If discharge is severe, the information stored in the form of charge may be lost entirely. As a consequence, the charge representing the stored information must usually be periodically refreshed. The greater the number of free carriers created within or reaching the charge storage depletion region per unit time, the more frequently this stored information must be refreshed, that is, the lost charge replaced.
• Thermal carrier generation within the depletion region can dissipate the stored charge.
• Thermal carrier generation and carrier lifetime are related. In order to minimize thermal carrier generation in the depletion region, the carrier lifetime must be made as long as possible. Thus, great effort is expended to obtain long lifetime material in which to form the depletion regions used for charge storage. However, the longer the lifetime, the greater the probability that carriers from elsewhere in the device, e.g., carriers generated in the underlying substrate or injected from nearby junctions, will diffuse into the depletion region and discharge the stored information. Thus, conflicting requirements are encountered when trying to reduce all sources of carriers which might contribute to dissipating the stored charge and thereby requiring more frequent refresh. Ionizing radiation and particles absorbed within a semiconductor material produce free carriers by ionization.
• the depletion region of a charge storage device is relatively thin so that few ionizing events occur directly therein. Further, the depletion region is often located near a device surface, so that only comparatively low energy radiation or particles are likely to be absorbed there. These low energy particles can be easily filtered out by surface protection layers and so are readily avoided. However, the more energetic particles or radiation will pass through the surface layers and be absorbed in the bulk of the substrate. The carrier pairs freed by ionizing events occurring in the substrate can readily diffuse to the depletion region if the semiconductor "substrate has a high lifetime. It has been found that these bulk generated carriers are a significant cause of low storage times in many types of charge storage devices.
• One method for reducing the discharging effect of in-diffusing carriers is to reduce the bulk lifetime so that more of the bulk generated carriers recombine before reaching the depletion region of the storage device.
• Two methods of carrier lifetime control which are commonly used in silicon devices, for example, are electron bombardment and gold doping. Electron bombardment is believed to reduce lifetime by introducing defects in the crystal lattice. A disadvantage of using bombardment induced lattice defects for lifetime control is that such defects anneal out during subsequent high temperature processing steps.
• Gold doping is another means of controlling lifetime. However, gold doping is incapable of the necessary spatial resolution. For example, gold diffuses so rapidly in silicon at ordinary process temperatures that it travels throughout the entire wafer thickness in a very brief time. Further, the amount of lifetime reduction that can be obtained by these methods is often insufficient to prompt recombination of all in-diffusing carriers.
• argon has been investigated as a means of obtaining localized reduction in lifetime.
• the lifetime reductions from ion implanted argon appear to be primarily related to physical damage to the crystal lattice.
• the effect is significantly annealed by post implant heating. This is a substantial disadvantage since practical device fabricated methods generally require that the treated wafer be heated to high temperatures during subsequent fabrication steps.
• a means for forming radiation shielded charge storage devices comprising, a semiconductor substrate having first and second major surfaces, a high lifetime region adjacent the first major surface and adapted for containing one or more charge storage devices, a low lifetime region in the semiconductor substrate underlying the high lifetime region, wherein the low lifetime region contains reactive ions which form carrier recombination centers. It is essential that the lifetime killing impurities be implanted to dose levels which exceed the solid solubility limit of the impurities in the substrate material. It is desirable that the low lifetime region comprise a planar region of predetermined thickness which is small compared to the separation of the first and second major surfaces, and which is located substantially parallel to the first major surface.
• FIG. 2 shows a simplified schematic cross-sectional view of a portion of a semiconductor substrate containing charge storage device regions, according to the present invention
• FIG. 3 shows a simplified schematic cross-sectional view of a portion of a semiconductor substrate containing charge storage device regions and a bipolar device region, according to a further embodiment of the present invention
• FIG. 4 shows a simplified schematic cross-sectional view of a portion of a semiconductor substrate containing charge storage device regions according to a further embodiment of the present invention
• FIGS. 5A-I show simplified schematic cross- sectional views of a portion of a semiconductor substrate having charge storage device regions, during various stages of manufacture and using alternative manufacturing sequences, according to the present invention
• FIGS. 7A-B show plots of the normalized effective lifetime as a function of depth from the surface of the substrate for different implant doses of oxygen; and FIG. 8 shows plots of leakage current (I) versus depletion depth (w), and rate of charge of leakage current with depletion depth (dl/dw) versus depletion depth (w), for an N P diode in an epitaxially coated oxygen implanted silicon substrate.
• FIG. 1 shows portion 10 of semiconductor substrate 11 which has therein charge storage device regions 12 and 14.
• Charge storage device region 12 is doped to a conductivity type opposite that of substrate 11 so that a P-N junction exists between device region 12 and substrate 11.
• MOS structure 14 consists of metallic electrode 14a covering dielectric 14b which rests on substrate 11. When appropriately biased, MOS structure 14 depletes the portion of surface llu of substrate 11 underneath electrode 14a to form depletion region 14d having width 14e.
• Depletion region I4d results from charge applied to electrode 14a or charge trapped within dielectric region 14b. Depletion region 14d is induced by this applied or trapped charge. When the applied or trapped charge is removed, depletion region 14d disappears.
• Doped region 13 having a conductivity type opposite substrate 11 is also provided to illustrate the interaction of nearby junctions with charge storage devices 12 and 14.
• Argon diffuses less rapidly than gold in silicon, but is also not a practical lifetime killer for forming an effective free carrier recombination region since the decrease in lifetime obtained with argon, while initially a factor of about 10 , is reduced after heating of the implanted wafers to about 10 . This is insufficient to provide adequate shielding. Further, neither gold or argon react chemically with most semiconductor materials so the lifetime killing complexes formed by these materials are inherently unstable.
• nearby junction 13 A further mechanism which adversely affects the behavior of charge storage devices is illustrated by nearby junction 13.
• nearby junction 13 When nearby junction 13 is forward biased, minority carriers will be injected into substrate 11, as indicated by arrows 13a. Since, the material surrounding the charge storage devices must be high lifetime material, an appreciable fraction of injected carriers 13a may reach depletion regions 12a and 14d of charge storage devices 12 and 14 and cause discharge, just as do the carriers produced in the bulk by ionizing particles or radiation 15a-b. Similar effects may be produced by conductors running across the surface of substrate 11 and by other device regions through a phenomena called charge-pumping. When the voltage on these conductors or devices is varied, as for example during memory write or read operations, minority carriers may be injected into the near surface regions containing the charge storage devices.
• Dynamic random access memories are particularly susceptible to such phenomena which frequently manifest themselves as row or column disturb effects. Hence, shielding charge storage devices from such phenomena and effects is particularly important.
• FIG. 2 shows portion 30 of semiconductor substrate 31 in which have been constructed charge storage device regions 12 and 14. Ray 15 indicates either ionizing particles 15a or radiation 15b.
• Junction 13 has the same function as described in connection with Fig. 1.
• Charge storage devices 12 and 14, and junction 13 are constructed in zone 31a of substrate 31 adjacent surface 31u.
• Substrate 31 is chosen to be a high lifetime material so that zone 31a also has this property. This insures that the recombination-generation currents present in devices 12 and 14 will be extremely low and that devices 12 and 14 will inherently have good charge storage properties.
• very low lifetime zone or region 31c is placed immediately beneath device zone 31a. It is desirable that thickness 32a of device zone 31a be as small as possible consistent with the requirement that depletion regions 12a and 14d associated with devices 12 and 14 do not expand to contact low lifetime region 31c.
• very low lifetime zone 31c By placing very low lifetime zone 31c close to doped region 13, very low lifetime zone 31c also serves as a sink to absorb a large fraction of carriers 13a injected from doped region 13 into substrate 31. This reduces the sensitivity of charge storage devices 12 and 14 to minority carriers injected from nearby junction 13 or from adjacent charge pump regions which behave in a similar way with respect to injecting minority carriers into the surface regions of the device structure.
• such a super-saturated oxygen zone can be produced at a controlled depth within the substrate without destroying the single crystal nature of the substrate surface, or causing such a high density of surface defects as to preclude the construction of high quality charge storage devices in the overlying material.
• the super-saturated oxygen zone is stable during subsequent heat treatments so that post- implant high temperature processing steps do not cause significant annealing, that is, the very low free carrier lifetime in the super-saturated oxygen zone does not decrease or go away on post-implant heating.
• the stability of the super-saturated oxygen zone is believed to be due to the ability of the oxygen to react chemically with the semiconductor material to form a stable SiO ⁇ phase.
• Oxygen has been found to be a suitable material for forming free carrier shield region 71c in silicon.
• the depth of shield region 71c below surface 71u can be varied by varying the implant energy (see FIG. 6).
• the implant energy see FIG. 6
• the center of the implanted oxygen distribution is located about one micron below surface 71u.
• the center of the implant distribution is approximately two microns below surface 71u, and at 3,500 keV the center is about four microns below surface 71u.
• the width of the implanted distribution at a particular concentration level depends upon the energy and total dose. Profiles of concentration versus depth from the surface for various implantation energies and doses are shown in FIG. 6. The profiles of FIG.
• FIG. 51 The finished structure is illustrated in FIG. 51 wherein substrate 71 has thereon epitaxial layer 73 of thickness 73a in which are fabricated charge storage device regions 12 and 14.
• Low lifetime carrier shield region 71c of width 72b is located in substrate 71 below undisturbed region 71a of width thickness 72a.
• Means for obtaining the structure of FIG. 51 are illustrated in FIGS. 5F-H.
• bare substrate 71 FIG. 5A
• Epitaxial layer 73 is then applied to surface 71u of substrate 71, as illustrated in FIG. 5F.
• the epitaxially coated substrate is then implanted with ions 74 to produce buried low lifetime shield layer 71c, as illustrated in FIG. 5H.
• Duoplasmatron Source supplied with O2 gas. Beam currents were about 2 micro-amps of 0 , substantially all of which struck the wafer. Implantation on the General Ionex implanter was obtained through Universal Energy Systems of Dayton, Ohio. Typical implant doses and energies are shown in Table I. The implants were 1 generally made into bare silicon wafers. However, samples SW5-A and B were covered with a 0.02 micron oxide layer prior to implantation. This oxide layer is too thin to have any appreciable affect on the ion 5 penetration depth. No attempt was made to control the wafer temperature during implantation. After implantation the wafers were heated as shown in Table I in order to react the oxygen with the silicon substrate material to activate the recombination centers and form
• N + P diodes were formed by conventional diffusion at about 950 °C using a phosphorous dopant.
• the wafers were reoxidized at 900 °C and 1050 °C to form a gate oxide for the MOS capacitors.
• a metal layer was
• Table I the wafers of Table I were subjected to further post-implant heating during the formation of the test diodes and MOS capacitors. These further heating cycles were: 90-165 min. at 1000 °C for initial oxidation; 25 min. at 950 °C during phosphorous diffusion; 75-115 min. at 900 °C during reoxidation; and 135 min. at 1050 °C for gate oxidation.
• the wafers coated with epitaxial layers were subjected to an additional heating cycle of
• the peak of the oxygen implant distribution is estimated as lying four to five microns beneath the surface of the structures.
• the effective lifetime at the surface was determined separately to be approximately 150 microseconds.
• the solid curve in FIG. 8 is a plot of leakage current (I) versus depletion depth (w).
• the depletion region width is varied by varying the bias voltage.
• a log-linear scale is used in FIG. 8. Near zero volts bias, the depletion region is so thin that it does not extend into the implanted oxygen zone underlying the diode.
• the leakage current is very low under these conditions, e.g., about 10 ⁇ i ⁇ amps.
• the fact that the leakage current is so low is further evidence that the surface layers above the implanted region have not been damaged by the implant process, or at least that any damage which may have been created did not propagate into the epi-layer in which the test devices were formed.
• the bias on the diode is increased, the depletion region expands and the leakage current increases. So long as the depletion region does not touch the low lifetime (high thermal generation rate) implanted zone, the leakage current increases relatively slowly.
• the depth of the implanted zone can be varied by adjusting the implant energy and/or the epi-layer thickness.
• the minimum depth is set by the requirement that the device depletion layer not penetrate into the shield region.
• the maximum depth can be varied over a range of many microns by using higher energy implants and/or thicker epi-layers.
• maximum shielding effect is obtained when the shield zone is kept as close as possible to the depletion layer without touching.
• charge storage device structures which employ a shallow low lifetime shield region in a substrate, which is then -coated by an overlying epi-layer, are expected to give better performance, and are preferred.
• the lifetime killing action of the implanted impurities is stable if the substrate is heated during or after implantation to react the implanted impurities with the substrate material and form chemically bonded complexes which provide a rich abundance of deep recombination centers. This process is generally referred to herein as activation.
• Implanted oxygen in silicon is believed to form SiO ⁇ complexes. These complexes have been observed using transmission electron microscopy and appear to be very finely divided, e.g., about 100 Angstroms (10 ⁇ ° m) in size. The complexes are surrounded by larger dislocations.
• the concentration of the implanted impurities must be above the solid solubility limit of the ion in the semiconductor material.
• the activation heating may be performed in any type of heating means.
• activation heating was carried out in an ordinary tube furnace of the type commonly used for diffusion or oxidation of semiconductors such as silicon, generally in a nitrogen atmosphere. The times and temperatures are indicated in Table I.
• a model IA-2000 Rapid Isothermal Annealing (RIA) apparatus manufactured by Varian-Extrion of Glouster, Massachusetts is suitable.
• the implanted wafer or substrate is placed in a vacuum chamber in the RIA apparatus where it is thermally isolated and separated by a shutter from a hot heater block held at a high temperature, for example, 900-1300 °C.
• a shutter is rapidly moved aside so that the wafer is suddenly exposed to the high temperature radiation from the heater. Since the thermal mass of the wafer is small its temperature rises very rapidly.
• An optical pyrometer located behind the wafer is used to measure its temperature.
• the RIA apparatus permits a wafer to be heated from room temperature to 900-1300 °C and cooled back to the vicinity of room temperature in a matter of a few seconds or tens of seconds. For example, heating to over 1100 °C in 5-30 seconds and dropping back below about 800 °C in another 5-30 seconds can be achieved.
• This treatment is particularly desirable for activation of implanted lifetime killing impurity ions, since it provides activation without allowing time for substantial thermal diffusion which can cause the implanted impurity distribution to spread out.
• an impurity must provide deep recombination centers, i.e. recombination levels located in the vicinity of the middle of the forbidden energy gap of the semiconductor material being used. The action of deep centers or levels in promoting carrier recombination is described by A. S.
• Oxygen for example is a weak N-type impurity but is still suitable. Nitrogen is also expected to be a useful element as a lifetime killer even though located in column 5a, since it is not believed to be a strong dopant atom in silicon but is expected to provide deep recombination levels.
• impurities which diffuse very rapidly and at relatively low temperatures are not useful, since during subsequent heating steps they can spread into the surface portions occupied by the depletion regions of the charge storage devices. This will increase the leakage currents in the charge storage devices and degrade their charge storage properties.
• Gold is an example of a material which provides deep recombination centers, but has too high a diffusivity.
• lifetime killer impurities which have values of diffusivity D corresponding to (D) ' > 50 microns per square root hour, in the temperature range of interest for device fabrication, that is, 900-1300 °C, are not expected to be useful.
• impurities or particles which provide deep recombination centers mostly by virtue of the lattice damage they create during implantation or by formation of unreacted precipitates (e.g., gas bubbles), are less desirable because of the tendency of the lifetime killing effect to anneal away during subsequent heating.
• Noble gases are examples of this type of impurity.
• Argon in particular is known to provide thermally annealable recombination centers. Such materials generally do not form stable chemically bound complexes with the substrate material.
• impurity ions suitable for use in forming a free carrier shield region according to the present invention must be chosen from among the elements which provide deep recombination centers or levels, which react chemically with the substrate material so as to form bound complexes which do not substantially re- absorb or anneal out during subsequent heating, and which do not have a diffusivity so high as to preclude maintaining the implanted ions in a predetermined zone within the semiconductor substrate under the temperatures required in subsequent device manufacturing and use. Further it is desirable to chose elements from among those which do not provide a high density of shallow donor or acceptor levels. For silicon, materials having a diffusivity satisfying the relation (D) 1 x/ / i 2 i > 50 microns per square root hour in the range
• carbon in silicon affects the propensity of oxygen to precipitate from solution and form deep recombination levels. The exact mechanism by which this occurs is not clearly understood. Nevertheless, carbon provides a useful means of controlling the nucleation and reaction of lifetime killing impurities such as oxygen.
• carbon is implanted in the semiconductor substrate to stimulate the localized nucleation and reaction of dissolved or implanted oxygen or other reactive lifetime killing impurity. When carbon is present, the oxygen preferentially reacts on or near the carbon, rather than nucleating and reacting at random. Hence, the carbon allows greater control of the distribution of the lifetime killing complexes within the substrate.
• the invention provides an improved means and method for shielding charge storage devices in semiconductor substrates from the deleterious effects of incident radiation or particles, or from carriers which may be injected from nearby junctions or by charge pumping. It is further apparent that the invented means and method provides a very low lifetime free carrier shield zone or region immediately beneath a high lifetime surface layer suitable for construction of charge storage devices. Additionally, the concentration of lifetime killing impurities which can be provided in the carrier shield zone is very large, being at least an order of magnitude greater than the normal solid solubility. As a consequence, the lifetime reduction ratios obtained by the present invention in the carrier shield region are also very large, e.g. as much as 10 or more.

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