EP0122984B1

EP0122984B1 - Time measuring circuit

Info

Publication number: EP0122984B1
Application number: EP83302263A
Authority: EP
Inventors: Tadao Hiramatsu; Sunao Katayama
Original assignee: Hagiwara Electric Co Ltd
Current assignee: Hagiwara Electric Co Ltd
Priority date: 1983-04-21
Filing date: 1983-04-21
Publication date: 1988-08-17
Also published as: DE3377748D1; EP0122984A1

Description

The present invention relates to a time measuring circuit for meters of the pulse reflection type such as an ultrasonic axial force meter, an ultrasonic thickness meter or the like.
For accurate measurement of a distance by using light, or an axial force of a bolt or a thickness of an object by using ultrasonic waves, it is desirable to measure the distance, axial force or thickness with a resolution or resolving power of approximately 1 nS. To effect such accurate measurement, an expensive high speed counter has been utilized heretofore, resulting in provision of special and complicated circuits for the counter.
It is desirable to provide an improved time measuring circuit which is capable of effecting accurate measurement of distance, axial force or thickness with a resolution or resolving power of substantially 1 ns without the need to provide a high speed counter.
IBM Technical Disclosure Bulletin Volume 5 No. 5 October 1961, page 27 describes in outline a time measuring circuit for use in meters of the pulse reflection type for measuring a parameter of an object, the circuit including: a pulse oscillator means for producing a clock pulse at a predetermined frequency; means for producing a transmission pulse signal for transmission to the object to be measured; receiving means for receiving an echo pulse signal reflected from said object; a gate signal generator responsive to the transmission and echo pulse signals for producing a gate signal the duration of which is dependent on the time interval to be measured between transmission of the transmission pulse signal and receipt of the echo pulse signal; means responsive to the gate signal and to the clock pulse for providing a periodic waveform; means for detecting the value of the periodic waveform on termination of the gate signal; and means for providing an output related to the duration of the gate signal from a combination of a counted value of pulses and a quantity derived from said detected value the time measuring circuit.
While this proposal, as far as can be ascertained from the outline discussion, may obviate the need to provide a high speed counter, by providing a degree of "fine tuning" by detecting the value of the periodic waveform on termination of the gate signal, the present invention mitigates the problem still further by enabling enhanced accuracy of this "fine tuning" to be achieved. The present invention is characterised in that:-

said means responsive to the gate signal for providing a periodic waveform comprises first means responsive to the clock pulse from said oscillator means and to the gate signal from said generator to produce, in the presence of the gate signal, first and second clock pulse trains having the same phase and being relatively inverted and second means coupled to receive the first and second clock pulse trains and responsive to the gate signal to produce from both of the first and second clock pulse trains said one, or more than one, periodic waveform having the same period as the first and second clock pulse trains, the detected value of the, or of one of the periodic waveforms depending on the duration of the gate signal;
the time measuring circuit includes third means for counting the pulses of the first clock pulse train from said first means and for producing an output signal indicative of said counted value of pulses; and
said means for providing an output is coupled to receive, in addition to said counted value and said detected value, one of the first and second clock pulse trains, said output being derived additionally from the state of one of the first and second clock pulse trains.

Preferably the first means comprises a complementary-output element responsive to the clock pulse from said oscillator means for producing said first and second clock pulse trains;

gate means responsive to the gate signal from said gate signal generator to output the first and second clock pulse trains in the presence of the gate signal; and
a flip-flop for applying the first clock pulse train to said third means and for applying the first and second clock pulse trains to said second means.

It is also preferable that the third means is in the form of a counter connected to the flip-flop to count the pulses of the first clock pulse train, the second means is in the form of a pair of integration circuits connected to the flip-flop to selectively integrate the first and second clock pulses in response to the gate pulse signal, and that there is an analog-to-digital converter connected to the integration circuits to convert the detected finally integrated value into a digital value.
For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:-

Fig. 1 is a schematic block diagram of a time measuring circuit in accordance with the present invention;
Figs. 2 and 3 illustrate waveforms appearing at various points in the circuit diagram of Fig. 1;
Fig. 4 is a schematic block diagram of a modification of the time measuring circuit of Fig. 1; and
Fig. 5 illustrates waveforms appearing at various points in the circuit diagram of Fig. 4.

Referring now to the drawings, Fig. 1 illustrates a time measuring circuit adapted to an ultrasonic axial force meter of the pulse reflection type. The time measuring circuit includes a crystal oscillator 1 for producing clock pulses A in the form of rectangular waves at a frequency of 100 KHz-10 MHz, and a JK flip-flop 2 connected at its clock terminal CK to the output terminal of oscillator 1 and at its other input terminals J and K to a DC voltage source Vcc. The time measuring circuit further includes an RS flip-flop 3 which is applied at its set terminal S with a transmission pulse signal TTP from the ultrasonic axial force meter and at its reset terminal R with a reflection echo pulse RTP from the axial force meter. RS flip-flop 3 is connected at its output terminal Q to a clear input terminal CLR of flip-flop 2, each first input terminal of NAND gates 4 and 5, and the input terminal of a timer 8. The output terminal Q of RS flip-flop 3 is further connected to each set terminal S of first and second integration circuits 11 and 12 respectively through inverters 9 and 10. NAND gates 4 and 5 are connected at their second input terminals to output terminals Q and Q of JK flip-flop 2 and at their output terminals to reset and set terminals R and S of a second flip-flop 6 respectively.
A first output terminal Q of RS flip-flop 6 is connected to the input terminal of a counter 7, a microcomputer 14 and a reset terminal R of the second integration circuit 12, while a second output terminal Q of RS flip-flop 6 is connected to a reset terminal R of the first integration circuit 11. Each output terminal of integration circuits 11 and 12 is connected to an analog-to-digital (or A-D) converter 13 which is in turn connected to microcomputer 14. The microcomputer 14 is commercially available, the interface of which is connected at its input terminals to respective output terminals of counter 7, timer 8 and A-D converter 13.
The ultrasonic axial force meter includes a frequency divider 21 in the form of a counter for dividing the frequency of the clock pulses A from oscillator 1, and a pulse width adjuster 22 in the form of a one-shot circuit or a differentiation circuit for forming rectangular impulse waves from the divided clock pulses. The rectangular impulse waves are transmitted to a trigger circuit 23 and also transmitted as the transmission pulse signal TTP to RS flip-flop 3. The ultrasonic axial force meter further includes a probe 30 connected to trigger circuit 23 for producing an ultrasonic pulse wave, which is transmitted to an object to be measured, a receiving amplifier 31 for receiving an echo pulse train output from probe 30, and a comparator 32 for comparing an output of the amplifier 31 with a predetermined value to produce the reflection echo pulse RTP. Furthermore, the ultrasonic axial force meter includes a reset circuit 24 connected to a reset terminal R of counter 7 and responsive to the divided clock pulses from frequency divider 21 for producing a reset signal in accordance with the clock pulses from oscillator 1, a ten-key board 41 for applying an input signal indicative of a constant of the object such as a bolt to the computer 14, a select- key board 42 for selecting input data for the computer 14, an indicator 43 for indicating a value measured by the computer 14, and a thermometer 44 for measuring a temperature of the object and the ambient temperature.
In operation, as is illustrated in Fig. 2, RS flip- flop 3 is set in response to the transmission pulse signal TTP to produce a gate signal D at a high level and is reset in response to the reflection echo pulse RTP to make the gate signal low level. The duration of gate signal D is proportional, for instance, to an axial length of the bolt to be measured. When received the gate signal D causes JK flip-flip 2 to divide clock pulses A from oscillator 1 to produce at its terminals Q and Q output signals B, C in the form of rectangular waves which are relatively inverted at half the frequency of the clock pulses. When the level of gate signal D becomes low, the output signal B from terminal Q is maintained at a high level, while the output signal C from terminal Q is maintained at a low level. NAND gates 4 and 5 are responsive to the gate signal D to permit the output signals B and C to be applied to the second RS flip-flop 6 from JK flip-flop 2. When the level of gate signal D becomes low, the timer 8 produces a high level signal therefrom after lapse of a time t, and the computer 14 is responsive to the high level signal from timer 8 to receive output signals from counter 7 and A-D converter 13, as is described in detail later.
As is illustrated in Figure 3, the output signals B and C from JK flip-flop 2 are relatively inverted to form the output signals E and F from NAND gates 4 and 5 during appearance of the gate signal D. When the level of gate signal D becomes low, the output signals E and F are maintained at a high level respectively. When the second RS flip-flop 6 is applied at its terminals R and S with relatively inverted output signals E and F during appearance of the gate signal D, it produces relatively inverted output signals G and H at its terminals Q and Q. Upon disappearance of the gate signal D, the second RS flip-flop 6 acts to store each level of the output signals E and F.
If the level of gate signal D becomes low when the output signals B and C from JK flip-flop 2 are at low and high levels respectively, the output signal G from RS flip-flop 6 is applied as an input signal with a high level to the counter 7, as is illustrated in (a) of Figure 3. If the level of gate signal D becomes low when the output signals B and C from JK flip-flop 2 are at high and low levels respectively, the output signal G from RS flip-flop 6 is applied as an input signal with a low level to the counter 7, as is illustrated in (b) of Figure 3. As a result, the counter 7 acts to count the number of the output pulses G from RS flip-flop 6 thereby to measure a timely. Furthermore, the computer 14 discriminates the operation of integration circuit 11 or 12 in relation to the level of the output signal G from RS flip-flop 6 to produce an output signal therefrom for activation of A-D converter 13.
When applied with the output signal H at a low level from RS flip-flop 6, the first integration circuit 11 operates to produce an output signal I in the form of saw tooth waves. In this instance, A-D converter 13 is responsive to the output signal from computer 14 to convert the final voltage level of output signal I into a digital value indicative of a time T₂. In the case that the full scale of each saw tooth wave of signal I represent a time defined by one-fourth the frequency of the clock pulses, the time T₂ is measured by a digital value converted from the final saw tooth wave of signal I. This means that resolution or resolving power in measurement of the time T₂ can easily be enhanced up to e.g. 1 nS, in dependence on the capacity of the A-D converter 13 related to the frequency of the clock pulses. When applied with the output signal G with the low level from RS flip-flop 6, as is illustrated in (b) of Figure 3, the second integration circuit 12 operates to produce an output signal J in the form of saw tooth waves. In this instance A-D converter 13 is responsive to the output signal from computer 14 to convert the final voltage level of output signal J into a digital value indicative of a time T₃. This means that resolution or resolving power in measurement of the time T₃ can be easily enhanced up to, e.g., 1 nS, in dependence on the capacity of the A-D converter 13 related to the frequency of the clock pulses.
In such operation as described above, integration circuits 11 and 12startto integrate the low levels of input signals H and G applied to their reset terminals R respectively during appearance of the gate signal D and discharge when the levels of the input signals H and G become high. When the level of gate signal D become low, the integration circuits 11 and 12 act to hold therein the finally integrated voltages respectively, and subsequently A-D converter 13 is activated in response to the output signal from computer 14 in relation to the level of the output signal G to convert the integrated voltage into the digital value and produces an output signal indicative of the digital value upon completion of the voltage conversion. When applied with the output signal from A-D converter 13, the computer 14 receives an output signal from counter 7 to measure a sum of the time T, and the time T₂ or T₂and T₃, and the counter 7 is reset by a reset signal from reset circuit 24.
In the case that the microcomputer 14 is applied with the input signal G with high level upon disappearance of the gate signal D, it measures the time T on the basis of the following equation:
In the case that the microcomputer 14 is applied with the input signal G with low level upon disappearance of the gate signal D, it measures the time T on a basis of the following equation-:
where the value of T₂ is determined in its full scale.
In Figure 4 there is illustrated a modification of the time measuring circuit described above, in which JK flip-flop 2 in Figure 1 is replaced with a complementary-output element 200, and the integration circuits 11 and 12 are replaced with a voltage generator 90, a selector 100 and a single integration circuit 110. The complementary-output element 200 is arranged to produce relatively inverted clock pulses A and A at the same phase in response to input clock pulses from oscillator 1. The voltage generator 90 is arranged to produce positive and negative voltage signals +V_s, -V_s which have the same voltage levels and different polarities, the selector 100 is, for example, in the form of an analogue switch which is connected to voltage generator 90 to produce a positive voltage signal +Vg in response to the low level signal H from RS flip-flop 6 and to produce a negative voltage signal -V_s in response to the low level signal G from RS flip-flop 6, and the integration circuit 110 is arranged to charge in response to the positive voltage signal +V_s and discharge in response to the negative voltage signal -V_s thereby to produce an output signalla in the form of triangular waves as is illustrated in Fig. 5. The other arrangements are substantially the same as those in the time measuring circuit of Fig. 1.
Having thus described the preferred embodiments of the invention it should be understood that numerous structural modifications and adaptations may be resorted to without departing from the spirit of the invention. For instance, it is noted that A-D converter 13 of the above embodiment may be replaced with a voltage-frequency converter with a counter.

Claims

1. A time measuring circuit for use in meters of the pulse reflection type for measuring a parameter of an object, the circuit including: a pulse oscillator means (1) for producing a clock pulse (A) at a predetermined frequency: means (21, 22, 23) for producing a transmission pulse signal (TTP) for transmission to the object to be measured; receiving means (31) for receiving an echo pulse signal (RTP) reflected. from said object; a gate signal generator (3) responsive to the transmission and echo pulse signals for producing a gate signal (D) the duration of which is dependent on the time interval to be measured between transmission of the transmission pulse signal and receipt of the echo pulse signal; means (2, 4, 5, 6, 11, 12) responsive to the gate signal (D) and to the clock pulse (A) for providing a periodic waveform; means (13) for detecting the value of the periodic waveform on termination of the gate signal; and means (14) for providing an output related to the duration of the gate signal from a combination of a counted value of pulses and a quantity derived from said detected value, the time measuring circuit being characterised in that:-

said means (2, 4, 5, 6, 11, 12) responsive to the gate signal for providing a periodic waveform comprises first means (2,4,5,6) responsive to the clock pulse (A) from said oscillator means and to the gate signal (D) from said generator to output, in the presence of the gate signal, first and second clock pulse trains (G, H) having the same phase and being relatively inverted, and second means (11,12, or 90, 100, 110) coupled to receive the first and second clock pulse trains and responsive to the gate signal to produce from the first and second clock pulse trains said one, or more than one, periodic waveforms (I, J, la) having the same period as the first and second clock pulse trains, the detected value of the, or of one of the, periodic waveforms depending on the duration of the gate signal;

the time measuring circuit includes third means (7) for counting the pulses of the first clock pulse train (G) from said first means and for producing an output signal indicative of said counted value of pulses;

said means (14) for providing an output is coupled to receive, in addition to said counted value and said detected value, one of the first and second clock pulse trains, said output being derived additionally from the state of one of the first and second clock pulse trains.

2. Atime measuring circuit as claimed in claim 1, wherein said first means comprises:

a complementary-output element (2 or 200) responsive to the clock pulse (A) from said oscillator means for producing said first and second clock pulse trains;

gate means (4, 5) responsive to the gate signal (D) from said gate signal generator to output the first and second clock pulse trains in the presence of the gate signal; and

a flip-flop (6) for applying the first clock pulse train (G) to said third means and for applying the first and second clock pulse trains (G, H) to said second means.

3. A time measuring circuit as claimed in claim 1 or 2, in which said means (13) for detecting the value of the periodic waveform(s) on termination of the gate signal comprises an analogue-to-digital converter (13) connected to said second means to convert the detected value into a digital value.

4. A time measuring circuit as claimed in claim 1, 2, or 3, wherein said second means comprises first and second integration circuits (11, 12) connected to said first means and to said gate signal generator (3) to integrate pulses of the first and second clock pulse trains (G, H) respectively, to provide first and second periodic waveforms in the form of respective first and second integrated signals, the detected value of one of the first and second integrated signals depending on the duration of the gate signal.

5. Atime measuring circuit as claimed in claim 1, 2 or 3, wherein said second means comprises a voltage generator (90) for generating positive and negative voltage signals (+V_s, -V_s) having the same voltage, a selector means (100) connected to said voltage generator for producing a positive voltage signal in response to pulses of one (H) of the first and second clock pulsetrains (G, H) and for producing a negative voltage signal in response to pulses of the other (G) of the first and second clock pulse trains (G, H), and an integration circuit (110) connected to said selector means and to said gate signal generator to charge in response to the positive voltage signal from said selector means and to discharge in response to the negative voltage signal from said selector means thereby to provide said periodic waveform.

6. Atime measuring circuit as claimed in claim 2, or claim 3, 4 or 5 when appended to claim 2, wherein said complementary-output element comprises a JK flip-flop (2) responsive to the clock pulse (A) from said oscillator means for producing said first and second clock pulse trains (G, H) and said gate means includes first and second NAND gates (4, 5) connected to receive the first and second clock pulse trains and the gate signal.

7. A time measuring circuit as claimed in any preceding claim, wherein said means for providing an output comprises a microcomputer (14).