EP0079884A1 - Split load circuit - Google Patents

Split load circuit

Info

Publication number
EP0079884A1
EP0079884A1 EP19810901777 EP81901777A EP0079884A1 EP 0079884 A1 EP0079884 A1 EP 0079884A1 EP 19810901777 EP19810901777 EP 19810901777 EP 81901777 A EP81901777 A EP 81901777A EP 0079884 A1 EP0079884 A1 EP 0079884A1
Authority
EP
European Patent Office
Prior art keywords
load
logic
node
terminal
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19810901777
Other languages
German (de)
French (fr)
Inventor
Robert James Proebsting
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of EP0079884A1 publication Critical patent/EP0079884A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors

Definitions

  • the present invention pertains to driver circuits and more particularly to such circuits which drive a plurality of loads having different speed requirements.
  • Driver circuits/ such as push-pull type circuits are frequently utilized in the design of integrated circuits.
  • One type of integrated circuit which uses push-pull driver circuits is a random access memory fabricated with metal oxide semiconductor field effect transistors (MOSFET).
  • MOSFET metal oxide semiconductor field effect transistors
  • a driver circuit receives a single input signal and simultaneously drive a plurality of nodes each of which is an independent load. It has heretofore been a conventional practice to design the driver transistors of a push-pull circuit to be sufficiently powerful to drive all of the loads in parallel to meet the fastest logic speed transition requirement.
  • a selected embodiment of the present invention comprises a split load circuit which includes a first load having a first logic speed transition requirement and a second load having a second logic speed transition requirement which is slower than the first, logic speed transition requirement.
  • the first and second loads are operative in response to coincident logic state inputs.
  • First circuitry is connected to receive at least one logic input signal for producing therefrom a first driver signal which is provided to drive the first load.
  • the first circuitry is fabricated in relation to the first logic speed transition requirement such that the first driver signal meets the first logic speed transition requirement.
  • Second circuitry is connected to receive at least said one logic input signal for producing therefrom a second driver signal which is provided to drive the second load.
  • the second circuitry is fabricated in relation to the second logic speed transition requirement such that the second driver signal meets the second logic speed transition requirement.
  • the first and second driver signals have coincident logic states.
  • FIGURE 1 is a schematic diagram of a push-pull driver circuit in accordance with the present invention
  • FIGURE 2 is a logic diagram of a further embodiment of a push-pull circuit in accordance with the present invention.
  • FIGURE 3 is a schematic diagram of optional circuitry for the first stage of the push-pull circuit illustrated in FIGURE 2.
  • FIGURE 1 A first.embodiment of the present invention is illustrated in FIGURE 1 and is designated generally by the reference numeral 10.
  • the split load push-pull circuit 10 receives a logic level input signal through a node 12 with the input signal having first and second logic states. The inverse of the input signal is transmitted through a node 14.
  • Node 14 is connected to the gate terminal of a depletion mode pull-up transistor 16 which has the drain terminal thereof connected to a first power terminal 18 and the source terminal thereof connected to a node 20.
  • Node 12 is connected to the gate terminal of an enhancement mode pull-down transistor 22 which has the drain terminal thereof connected to node 20 and the source terminal thereof connected to a second power terminal 24 which serves as the circuit ground.
  • Node 14 is further connected to the gate terminal of a second depletion mode pull-up transistor 26 which has the drain terminal thereof connected to the first power terminal 18 and the source terminal thereof connected to a node 28.
  • Node 12 is further connected to the gate terminal of a second enhancement mode pull-down transistor 30 which has the drain terminal thereof connected to node 28 and the source terminal thereof connected to the second power terminal 24.
  • Node 20 is connected to a high speed load 32 and node 28 is connected to a low speed load 34.
  • the high speed load 32 is a circuit element, such as the gates of one or more pull-up transistors which must be driven to have relatively high speed signal logic transitions in order to achieve the desired operation of the load circuit.
  • the low speed load 34 such as the gates of one or more large pull-down transistors is a circuit which is driven at a rate that is slower than that of load 32.
  • the loads 32 and 34 are both responsive to
  • OMPI the input signal and are driven to corresponding logic states.
  • load 32 is a low capacitance load with a high logic transition speed requirement while load 34 is a much higher capacitive load but has a significantly lower speed requirement.
  • the circuit 10 can be utilized in a MOSFET circuit such as, for example, a random access memory.
  • the FET's 16, 22, 26 and 30 would have the minimum channel lengths as limited by the manufacturing process utilized. Currently this is approximately 3.0 microns.
  • the width of transistors 16 and 26 can typically be 25 microns while the pull-down transistors 22 and 30 would each have 5 to 10 times the width of the corresponding pull-up transistor connected thereto however the size can vary substantially depending on the load.
  • the high speed load 32 can typically have a logic transition speed requirement that is substantially greater than that of the 'low speed load 34.
  • Circuit 10 basically functions as an inverter in which the loads 32 and 34 are driven to the opposite logic state from that of the input signal at node 12.
  • transistors 22 and 30 will be turned on thereby pulling nodes 20 and 28 essentially to ground.
  • transistors 16 and 26 When the input signal at node 12 is high the complement signal at node 14 will be at a low state. This low state is transmitted to the gate terminals of transistors 16 and 26. Since these transistors are depletion mode devices they will remain essentially turned on. However, transistors 16 and 26 are much narrower than the corresponding pull-down transistors 22 and 30 and therefore have a higher resistance. There will thus be a DC current flow through transistors 16 and 22 as well -as transistors 26 and 30. The nodes 20 and 28 are pulled close to ground potential due to the lower impedance of . transistors 22 and 30 relative to transistors 16 and 26.
  • node 12 When node 12 is driven to a low voltage state transistors 22 and 30 will be turned off thereby isolating nodes 20 and 28 from ground.
  • the complement signal at node 14 is driven to a high voltage state thereby affirmatively turning on transistors 16 and 26 to pull nodes 20 and 28 up to the supply voltage V .
  • the nodes 20 and 28 can be brought essentially to the voltage of the power supply due to the use of the depletion mode transistors 16 and 26.
  • the loads 32 and 34 which must have coincident logic inputs, are driven from separate nodes of the circuit 10 and therefore can transition from one logic state to another at different rates. It has heretofore been a general practice to drive the loads 32 and 34 through a single node and make the driving transistors sufficiently strong, wide, to .drive the total capacitive load at the speed required for the load having the fastest speed requirement. In many situations there exists two separate loads one of which has low capacitance and requires a high speed transition and the other of which has a higher capacitance but can tolerate a low speed transition. If these loads are combined with a common node 25 has heretofore been the practice of the size of the driving transistors is that required to drive the total capacitance at the high speed. By splitting the loads, as shown in circuit 10, the speed requirements can be met while using much smaller driver transistors. Since the load requiring high speed transistors has low capacitance and the load having high capacitance can derive low speed transistors.
  • circuit 44 shown in FIGURE 2.
  • a logic level input signal is provided to a node 46.
  • Node 46 is connected to the gate terminals of enhancement mode,
  • OMPI pull-down transistors 48, 50 and 52 The drain terminal of transistor 48 is connected to a node 54.
  • the source terminals of transistors 48, 50 and 52 are each connected to a second power terminal 56 which is the circuit ground.
  • Node 54 is connected to the source and gate terminals of a depletion mode pull-up transistor 60 which has the drain terminal thereof connected to a first power terminal 62, V cc .
  • Node 54 is further connected to the gate terminals of depletion mode pull-up transistors 64 and 66 which have the drain terminals thereof connected to the first power terminal 62.
  • the source terminal of transistor 64 is connected to a node 68 and the source terminal of transistor 66 is connected to a node 70.
  • the drain terminals of transistors 50 and 52 are connected respectively to the nodes 62 and 70.
  • Node 68 is connected to a high speed load 72 and node 70 is connected to a low speed load 7-4.
  • Loads 72 and 74 correspond respectively. to the loads 32 and 34 described above.
  • the transistors 60, 64 and 66 each have a channel width of approximately 25 microns while each of the transistors 48, 50 and 52 have a channel width of approximately 250 microns.
  • the high speed load 72 has a capacitance of approximately 1 picofarad and the requirement that the transition speed be approximately one nanosecond.
  • the low speed load 74 has a capacitive load of approximately 10 picofarads and the requirement that it be driven from one logic state to another in 10 nanoseconds.
  • Circuit 44 can be adapted to have a plurality of inputs so that circuit 44 could operate as a logic gate. For example, a parallel transistor could be added to each of the transistors 43, 50 and 52 with the gates of the added transistors connected in parallel to a second input. This would produce a two input NOR gate.
  • Circuit 44 functions essentially as an inverter wherein the input signal provided to node 46 must provide an inverted logic state to loads 72 and 74.
  • node 46 When node 46 is driven to a high voltage level, essentially V cc , transistors 48, 50 and 52 will be turned on thereby pulling corresponding nodes 54, 68 and 70 essentially to ground.
  • the depletion mode transistors 60, 64 and 66 will remain turned on as node 54 is pulled down.
  • transistors 60, 64 and 66 have a much smaller channel width than the corresponding transistors 48, 50 and 52, the impedance of transistors 60, 64 and 66 will be much greater.
  • nodes 54, 68 and 70 will be driven to a low voltage which is a function of the ratios of the resistances of the pull-up transistors and the pull-down transistors in each pair. Therefore, nodes 54, 68 and 70 are pulled essentially to ground likewise pulling the inputs to loads 72 and 74 essentially to ground.
  • transistors 48, 50 and 52 will be turned off thereby isolating nodes 54, 68 and 70 from ground. Since depletion transistor 60 has the gate and source terminals tied together it will remain turned on thereby pulling node 54 up to cc . This provides an affirmative gate drive for transistors 60, 64 and 66 thereby pulling nodes 68 and 70 up to V . This in turn pulls the inputs to loads 72 and 74 up to cc .
  • transistor 64 will have an impedance of approximately 1,000 ohms. Since load 72 has the capacitance of 1 picofarad it can be driven from the low to the high voltage state in one nanosecond as required.
  • the transistor 66 likewise has an impedance of approximately
  • transistor 66 requires 10 nanoseconds in which to pull load 74 from a low to a high voltage state. This meets the requirements of the low speed load 74.
  • transistors 64 and 66 do not necessarily have the same impedance.
  • the prior technique would be to combine transistors 64 and 66 and to combine transistors 50 and 52 thereby making a single node of • nodes 68 and 70.
  • the new transistor replacing 64 and 66 would need to have a resistance of approximately 91 ohms which would require a width of approximately 275 microns.
  • the two 25 micron transistors which can be employed by the use of the present invention and further substantially reduces power consumption.
  • the pull-down transistor since the pull-down transistor must be 10 times the width of the corresponding pull-up transistor, the reduction in size of the pull-up transistor produces a proportional reduction in size of the pull-down transistor.
  • the power consumption of the split load circuit of the present invention is substantially less than that of previous corresponding circuits since the current drawn by the depletion loads is directly proportional to the width of the transistors. There is thus a power saving in the same ratio as the space saving. For this example there is thus a saving in space and power by a factor of approximately five.
  • the transistor 60 would likewise have to be enlarged in order to drive the increased gate capacitance of th-e combined transistor.
  • the present invention is applicable where a plurality of loads have the requirement that they be driven to the same logic levels but that one node must be driven at a substantially faster rate than the other node. Under these conditions the circuit of the present invention provides a substantial savings in area on an integrated circuit chip.
  • the depletion mode transistors 60, 64 and 66 shown in FIGURE 1 can be replaced by enhancement mode transistors if there is no requirement to pull the inputs to the loads all the way up to V .
  • enhancement transistors would provide an advantage by eliminating DC current flow when transistors 48, 50 and 52 are turned on. In certain applications which can utilize the circuit of the present invention it is desirable to utilize only enhancement mode transistors. This can be accomplished by utilizing the boot strap circuit 80 illustrated in FIGURE 3 in place of the transistor pair 48 and 60 shown in FIGURE 2.
  • the input signal is provided to the node 46 as in FIGURE 2.
  • Node 46 is connected to the gate terminal of an enhancement mode pull-down transistor 82 which has the drain terminal thereof connected to the node 54.
  • the source terminal of transistor 82 is connected to ground.
  • An enhancement mode transistor 84 has the drain terminal thereof connected to the power terminal 62, V , the gate terminal thereof connected to a node 86 and the source terminal thereof connected to node 54.
  • a bootstrap capacitor 88 is connected between node 86 and node 54.
  • An enhancement mode transistor 90 has the drain and gate terminals thereof connected to the power terminal 62 and the source terminal thereof connected to node 86. ' The operation of circuit 80 is now described in reference to FIGURE 3.
  • Transistor 90 acts as a diode which pulls node 86 to within one transistor threshold voltage ( m) of V .
  • the voltage across capacitor 88 is essentially v cc ⁇ v rp*
  • circuit 80 in FIGURE 3 provides the full supply voltage to the node 54 as did the depletion transistor 60, but without the use of depletion transistors.
  • node 54 is connected to the gates on now enhancement transistor 64 and 66.
  • input 46 When input 46 is high the node 54 is low and is less than one V T from ground.
  • Transistors 64 and 66 are turned off thereby dissipating no power.
  • Nodes 68 and 70 are then at a low state.
  • transistor 82 When input 46 is low transistor 82 is turned off so that node 54 goes to V cc as described above which pulls nodes 68 and 70 to
  • V -Vm enhancement transistors 64 and 66 In a second configuration the gates of enhancement transistors 64 and 66 of FIGURE 2 are connected to node 86 of FIGURE 3.
  • transistor 82 When input goes high transistor 82 is turned on pulling the gates of transistors 64 and 66 to near ground. But since node 86 is at V cc - m there is power dissipation through transistors 64 and 50 as well as through transistor 66 and 52. Nodes 68 and 70 are at a low state.
  • input 46 goes low node 54 switches to V bootstrapping node 86 above V as described above so that the gates of ohms current transistors 64 and 66 are above V thereby pulling nodes 68 and 70 all the way to V .
  • each of the transistors described herein is an enhancement mode, N-channel device.
  • the circuits of the present invention can equally well be constructed and operated with P-channel transistors or with CMOS technology.
  • the present invention provides a reduction in circuit area and power required for driving loads which have substantially different speed requirements but the loads must be driven to the same logic state by a single input signal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

Un circuit a charge divisee (44) sert a porter une charge a haute vitesse (72) et une charge a faible vitesse (74) au meme etat logique en reponse a un ou plusieurs signaux d'entree. Un signal d'entree est applique aux terminaux de portes des transistors de refoulement (48, 50, 52). L'inverse du signal d'entree est applique aux terminaux de portes des transistors de remontage (64, 66). La charge a haute vitesse (72) est connectee entre le transistor de remontage (64) et le transistor de refoulement (50) et la charge a faible vitesse (74) est connectee entre le transistor de remontage (66) et le transistor de refoulement (52). Lorsque le signal d'entree au point nodal d'entree (46) est porte d'un etat de tension a un autre, les charges (92, 74) sont transmises a des vitesses differentes en fonction de la capacitance et de l'impedance de la charge et des dimensions des transistors de remontage (64, 66) et des transistors de refoulement (50, 52). Les charges (72, 74) sont transmises independamment de maniere a pouvoir utiliser des transistors de remontage et de refoulement beaucoup plus petits a la place d'un transistor unique de remontage et d'un transistor unique de refoulement qui devraient autrement posseder des dimensions beaucoup plus grandes afin de satisfaire aux exigences de vitesse de la charge a vitesse elevee (72) et de charger la capacitance elevee de la charge a faible vitesse (74). La consommation de puissance se trouve en outre sensiblement reduite a la suite de la reduction de la surface des transistors.A split load circuit (44) is used to carry a high speed load (72) and a low speed load (74) in the same logic state in response to one or more input signals. An input signal is applied to the door terminals of the discharge transistors (48, 50, 52). The inverse of the input signal is applied to the door terminals of the winding transistors (64, 66). The high speed load (72) is connected between the winding transistor (64) and the discharge transistor (50) and the low speed load (74) is connected between the winding transistor (66) and the discharge transistor (52). When the input signal at the input node (46) is carried from one voltage state to another, the charges (92, 74) are transmitted at different speeds depending on the capacitance and the impedance of the load and the dimensions of the winding transistors (64, 66) and the discharge transistors (50, 52). The charges (72, 74) are transmitted independently so as to be able to use much smaller winding and driving transistors in place of a single winding transistor and a single driving transistor which would otherwise have very large dimensions. larger to meet the speed requirements of the high speed load (72) and to charge the higher capacitance of the low speed load (74). Power consumption is also significantly reduced as a result of the reduction in the area of the transistors.

Description

SPLIT LOAD CIRCUIT
TECHNICAL FIELD
The present invention pertains to driver circuits and more particularly to such circuits which drive a plurality of loads having different speed requirements.
OMPI BACKGROUND ART
Driver circuits/ such as push-pull type circuits, are frequently utilized in the design of integrated circuits. One type of integrated circuit which uses push-pull driver circuits is a random access memory fabricated with metal oxide semiconductor field effect transistors (MOSFET). In these integrated circuits there are applications in which it is required that a driver circuit receive a single input signal and simultaneously drive a plurality of nodes each of which is an independent load. It has heretofore been a conventional practice to design the driver transistors of a push-pull circuit to be sufficiently powerful to drive all of the loads in parallel to meet the fastest logic speed transition requirement.
As integrated circuits have become more dense there is an increasing need to reduce the sizes of the transistors in the circuit to the minimum possible. Therefore, there exists a need for a driver circuit which has minimum size transistors and is capable of driving a plurality of loads which have different logic speed transition characteristics.
OMPI SUMMARY OF THE INVENTION
A selected embodiment of the present invention comprises a split load circuit which includes a first load having a first logic speed transition requirement and a second load having a second logic speed transition requirement which is slower than the first, logic speed transition requirement. The first and second loads are operative in response to coincident logic state inputs. First circuitry is connected to receive at least one logic input signal for producing therefrom a first driver signal which is provided to drive the first load. The first circuitry is fabricated in relation to the first logic speed transition requirement such that the first driver signal meets the first logic speed transition requirement. Second circuitry is connected to receive at least said one logic input signal for producing therefrom a second driver signal which is provided to drive the second load. The second circuitry is fabricated in relation to the second logic speed transition requirement such that the second driver signal meets the second logic speed transition requirement. The first and second driver signals have coincident logic states.
OMPI BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following Description taken in conjunction with the accompanying Drawings in which:
FIGURE 1 is a schematic diagram of a push-pull driver circuit in accordance with the present invention,
FIGURE 2 is a logic diagram of a further embodiment of a push-pull circuit in accordance with the present invention, and
FIGURE 3 is a schematic diagram of optional circuitry for the first stage of the push-pull circuit illustrated in FIGURE 2.
BURE7& DETAILED DESCRIPTION
A first.embodiment of the present invention is illustrated in FIGURE 1 and is designated generally by the reference numeral 10. The split load push-pull circuit 10 receives a logic level input signal through a node 12 with the input signal having first and second logic states. The inverse of the input signal is transmitted through a node 14.
Node 14 is connected to the gate terminal of a depletion mode pull-up transistor 16 which has the drain terminal thereof connected to a first power terminal 18 and the source terminal thereof connected to a node 20.
Node 12 is connected to the gate terminal of an enhancement mode pull-down transistor 22 which has the drain terminal thereof connected to node 20 and the source terminal thereof connected to a second power terminal 24 which serves as the circuit ground.
Node 14 is further connected to the gate terminal of a second depletion mode pull-up transistor 26 which has the drain terminal thereof connected to the first power terminal 18 and the source terminal thereof connected to a node 28.
Node 12 is further connected to the gate terminal of a second enhancement mode pull-down transistor 30 which has the drain terminal thereof connected to node 28 and the source terminal thereof connected to the second power terminal 24.
Node 20 is connected to a high speed load 32 and node 28 is connected to a low speed load 34. The high speed load 32 is a circuit element, such as the gates of one or more pull-up transistors which must be driven to have relatively high speed signal logic transitions in order to achieve the desired operation of the load circuit. The low speed load 34, such as the gates of one or more large pull-down transistors is a circuit which is driven at a rate that is slower than that of load 32. The loads 32 and 34 are both responsive to
OMPI the input signal and are driven to corresponding logic states.' In a typical application load 32 is a low capacitance load with a high logic transition speed requirement while load 34 is a much higher capacitive load but has a significantly lower speed requirement.
The circuit 10 can be utilized in a MOSFET circuit such as, for example, a random access memory. In such an application the FET's 16, 22, 26 and 30 would have the minimum channel lengths as limited by the manufacturing process utilized. Currently this is approximately 3.0 microns. The width of transistors 16 and 26 can typically be 25 microns while the pull-down transistors 22 and 30 would each have 5 to 10 times the width of the corresponding pull-up transistor connected thereto however the size can vary substantially depending on the load. The high speed load 32 can typically have a logic transition speed requirement that is substantially greater than that of the 'low speed load 34.
Operation of the circuit 10 is now. described in reference to FIGURE 1. Circuit 10 basically functions as an inverter in which the loads 32 and 34 are driven to the opposite logic state from that of the input signal at node 12. When the signal at node 12 is driven to a high state, transistors 22 and 30 will be turned on thereby pulling nodes 20 and 28 essentially to ground.
When the input signal at node 12 is high the complement signal at node 14 will be at a low state. This low state is transmitted to the gate terminals of transistors 16 and 26. Since these transistors are depletion mode devices they will remain essentially turned on. However, transistors 16 and 26 are much narrower than the corresponding pull-down transistors 22 and 30 and therefore have a higher resistance. There will thus be a DC current flow through transistors 16 and 22 as well -as transistors 26 and 30. The nodes 20 and 28 are pulled close to ground potential due to the lower impedance of . transistors 22 and 30 relative to transistors 16 and 26.
When node 12 is driven to a low voltage state transistors 22 and 30 will be turned off thereby isolating nodes 20 and 28 from ground. The complement signal at node 14 is driven to a high voltage state thereby affirmatively turning on transistors 16 and 26 to pull nodes 20 and 28 up to the supply voltage V . The nodes 20 and 28 can be brought essentially to the voltage of the power supply due to the use of the depletion mode transistors 16 and 26.
Note that the loads 32 and 34, which must have coincident logic inputs, are driven from separate nodes of the circuit 10 and therefore can transition from one logic state to another at different rates. It has heretofore been a general practice to drive the loads 32 and 34 through a single node and make the driving transistors sufficiently strong, wide, to .drive the total capacitive load at the speed required for the load having the fastest speed requirement. In many situations there exists two separate loads one of which has low capacitance and requires a high speed transition and the other of which has a higher capacitance but can tolerate a low speed transition. If these loads are combined with a common node 25 has heretofore been the practice of the size of the driving transistors is that required to drive the total capacitance at the high speed. By splitting the loads, as shown in circuit 10, the speed requirements can be met while using much smaller driver transistors. Since the load requiring high speed transistors has low capacitance and the load having high capacitance can derive low speed transistors.
A further embodiment of the present invention is illustrated by circuit 44 shown in FIGURE 2. A logic level input signal is provided to a node 46. Node 46 is connected to the gate terminals of enhancement mode,
OMPI pull-down transistors 48, 50 and 52. The drain terminal of transistor 48 is connected to a node 54. The source terminals of transistors 48, 50 and 52 are each connected to a second power terminal 56 which is the circuit ground. Node 54 is connected to the source and gate terminals of a depletion mode pull-up transistor 60 which has the drain terminal thereof connected to a first power terminal 62, Vcc.
Node 54 is further connected to the gate terminals of depletion mode pull-up transistors 64 and 66 which have the drain terminals thereof connected to the first power terminal 62. The source terminal of transistor 64 is connected to a node 68 and the source terminal of transistor 66 is connected to a node 70. The drain terminals of transistors 50 and 52 are connected respectively to the nodes 62 and 70.
Node 68 is connected to a high speed load 72 and node 70 is connected to a low speed load 7-4. Loads 72 and 74 correspond respectively. to the loads 32 and 34 described above.
In a design example of the present invention as illustrated by circuit 44, the transistors 60, 64 and 66 each have a channel width of approximately 25 microns while each of the transistors 48, 50 and 52 have a channel width of approximately 250 microns. The high speed load 72 has a capacitance of approximately 1 picofarad and the requirement that the transition speed be approximately one nanosecond. The low speed load 74 has a capacitive load of approximately 10 picofarads and the requirement that it be driven from one logic state to another in 10 nanoseconds.
Circuit 44 can be adapted to have a plurality of inputs so that circuit 44 could operate as a logic gate. For example, a parallel transistor could be added to each of the transistors 43, 50 and 52 with the gates of the added transistors connected in parallel to a second input. This would produce a two input NOR gate.
-BU RE
OMP The operation of circuit 44 is now described in reference to FIGURE 2. Circuit 44 functions essentially as an inverter wherein the input signal provided to node 46 must provide an inverted logic state to loads 72 and 74. When node 46 is driven to a high voltage level, essentially Vcc, transistors 48, 50 and 52 will be turned on thereby pulling corresponding nodes 54, 68 and 70 essentially to ground. The depletion mode transistors 60, 64 and 66 will remain turned on as node 54 is pulled down. However, since transistors 60, 64 and 66 have a much smaller channel width than the corresponding transistors 48, 50 and 52, the impedance of transistors 60, 64 and 66 will be much greater. Thus, nodes 54, 68 and 70 will be driven to a low voltage which is a function of the ratios of the resistances of the pull-up transistors and the pull-down transistors in each pair. Therefore, nodes 54, 68 and 70 are pulled essentially to ground likewise pulling the inputs to loads 72 and 74 essentially to ground. When node 46 is driven by the input signal to a low • voltage state, transistors 48, 50 and 52 will be turned off thereby isolating nodes 54, 68 and 70 from ground. Since depletion transistor 60 has the gate and source terminals tied together it will remain turned on thereby pulling node 54 up to cc. This provides an affirmative gate drive for transistors 60, 64 and 66 thereby pulling nodes 68 and 70 up to V . This in turn pulls the inputs to loads 72 and 74 up to cc.
The nodes 68 and 70 are isolated from each other such that the transition speeds of the loads are essentially independent. For the design example given above transistor 64 will have an impedance of approximately 1,000 ohms. Since load 72 has the capacitance of 1 picofarad it can be driven from the low to the high voltage state in one nanosecond as required. The transistor 66 likewise has an impedance of approximately
... OMPI ±0
1,000 ohms but the load 74 has a capacitance of 10 picofarads. . Thus, transistor 66 requires 10 nanoseconds in which to pull load 74 from a low to a high voltage state. This meets the requirements of the low speed load 74. Thus, it can be seen that the differing loads, although driven by the same input signal, respond in the times required. Note that transistors 64 and 66 do not necessarily have the same impedance.
It has heretofore been the general practice to drive the loads 72 and 74 by means of a single driving signal. Under such conditions it was required that the driving transistors be made sufficiently large to drive the low speed, high capacitance load as fast as the high speed, low capacitance load. This has required an exceedingly large transistor. For example, the prior technique would be to combine transistors 64 and 66 and to combine transistors 50 and 52 thereby making a single node of •nodes 68 and 70. In order to meet the 1 nanosecond speed requirement of the high speed node while driving the combined capacitance of 11 picofarads, the new transistor replacing 64 and 66 would need to have a resistance of approximately 91 ohms which would require a width of approximately 275 microns. This is in sharp contrast with the two 25 micron transistors which can be employed by the use of the present invention and further substantially reduces power consumption. Further, since the pull-down transistor must be 10 times the width of the corresponding pull-up transistor, the reduction in size of the pull-up transistor produces a proportional reduction in size of the pull-down transistor. The power consumption of the split load circuit of the present invention is substantially less than that of previous corresponding circuits since the current drawn by the depletion loads is directly proportional to the width of the transistors. There is thus a power saving in the same ratio as the space saving. For this example there is thus a saving in space and power by a factor of approximately five.
OMPI If the two transistors 64 and 66 are thus combined as suggested above, the transistor 60 would likewise have to be enlarged in order to drive the increased gate capacitance of th-e combined transistor. Thus, even more area and power is required under the prior technique. It can be seen from the above that the present invention is applicable where a plurality of loads have the requirement that they be driven to the same logic levels but that one node must be driven at a substantially faster rate than the other node. Under these conditions the circuit of the present invention provides a substantial savings in area on an integrated circuit chip. The depletion mode transistors 60, 64 and 66 shown in FIGURE 1 can be replaced by enhancement mode transistors if there is no requirement to pull the inputs to the loads all the way up to V . The use of enhancement transistors would provide an advantage by eliminating DC current flow when transistors 48, 50 and 52 are turned on. In certain applications which can utilize the circuit of the present invention it is desirable to utilize only enhancement mode transistors. This can be accomplished by utilizing the boot strap circuit 80 illustrated in FIGURE 3 in place of the transistor pair 48 and 60 shown in FIGURE 2. The input signal is provided to the node 46 as in FIGURE 2. Node 46 is connected to the gate terminal of an enhancement mode pull-down transistor 82 which has the drain terminal thereof connected to the node 54. The source terminal of transistor 82 is connected to ground. An enhancement mode transistor 84 has the drain terminal thereof connected to the power terminal 62, V , the gate terminal thereof connected to a node 86 and the source terminal thereof connected to node 54.
A bootstrap capacitor 88 is connected between node 86 and node 54.
OMPI An enhancement mode transistor 90 has the drain and gate terminals thereof connected to the power terminal 62 and the source terminal thereof connected to node 86. 'The operation of circuit 80 is now described in reference to FIGURE 3. When the input signal on node 46 is high, low impedance transistor 82 is turned on thereby pulling node 54 to a low state. Transistor 90 acts as a diode which pulls node 86 to within one transistor threshold voltage ( m) of V . Thus the voltage across capacitor 88 is essentially v cc~vrp*
When the input signal drives node 46 low, transistor 82 will be turned off which permits transistor 84 to pull node 54 upward. As node 54 rises in voltage, capacitor 88 raises the voltage on node 86. This permits transistor 84 to pull node 54 to the full supply voltage while node 86 raises to more than one V™ over V . Thus, it can be seen that circuit 80 in FIGURE 3 provides the full supply voltage to the node 54 as did the depletion transistor 60, but without the use of depletion transistors.
In a first configuration node 54 is connected to the gates on now enhancement transistor 64 and 66. When input 46 is high the node 54 is low and is less than one VT from ground. Transistors 64 and 66 are turned off thereby dissipating no power. Nodes 68 and 70 are then at a low state. When input 46 is low transistor 82 is turned off so that node 54 goes to Vcc as described above which pulls nodes 68 and 70 to
V -Vm enhancement transistors 64 and 66. In a second configuration the gates of enhancement transistors 64 and 66 of FIGURE 2 are connected to node 86 of FIGURE 3. When input goes high transistor 82 is turned on pulling the gates of transistors 64 and 66 to near ground. But since node 86 is at V cc- m there is power dissipation through transistors 64 and 50 as well as through transistor 66 and 52. Nodes 68 and 70 are at a low state. When input 46 goes low node 54 switches to V bootstrapping node 86 above V as described above so that the gates of ohms current transistors 64 and 66 are above V thereby pulling nodes 68 and 70 all the way to V .
Note that unless noted otherwise each of the transistors described herein is an enhancement mode, N-channel device. However, the circuits of the present invention can equally well be constructed and operated with P-channel transistors or with CMOS technology. In summary, the present invention provides a reduction in circuit area and power required for driving loads which have substantially different speed requirements but the loads must be driven to the same logic state by a single input signal.
Although two embodiments of the invention have been illustrated in the accompaning Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the scope of the invention.
1jϋREA
OMPI

Claims

1." A split load circuit comprising: a first load having a first logic speed transition requirement; a second load having a second logic speed transition requirement which is slower than said first logic speed transition requirement, said first and said second loads operative in response to coincident logic state inputs; means connected to receive at least one logic input signal for producing therefrom a first driver signal which is provided to drive said first load, said means for producing a first driver signal fabricated in relation to said first logic speed transition requirement such that said first driver signal meets said first logic speed transition requirement; and means connected to receive at least said one logic input signal for producing therefrom a second driver signal which is provided to drive said second load, said means for producing a second driver signal fabricated in relation to said second logic speed transition requirement such that said second driver signal meets said second logic speed transition requirement, said first and said second driver signals having coincident logic states.
^BIJRE
2. A split load circuir, comprising: a irst, load that must be driven to have a relatively high speed logic transition rate; a second load that can be driven to have a lower speed logic transition rate than said first load; a first node which is selectively driven by an input signal to first and second logic states; a second node; means for driving said second node to the opposite logic state from that of said first node; a first pull-up transistor controlled by the logic state at said second node, said first pull-up transistor connected to drive said first load to the first of said logic states; a first pull-down transistor controlled by the logic state at said first node for driving said first load to the second of said logic states; and a second pull-up transistor' controlled by the state at said second node for driving said second load to the first of said logic states; and a second pull-down transistor controlled by the state at said first node for driving said second load to the second of said logic states.
"BU EAU
' 0MPI
3. A split load circuit, comprising: a first load that must be driven to have a relatively high speed logic transition rate; a second load that can be driven to have a lower speed logic transition rate than said first load; a first FET having the gate terminal thereof connected to receive a first input signal which has first and second logic states, the drain terminal thereof connected to a first power terminal and the source terminal thereof connected to said first load for driving said first load to the first of said logic states; a second FET, enhancement mode, having the gate terminal thereof connected to receive a second input signal which is the inverse of said first input signal, the source terminal thereof connected to a second power terminal and the drain terminal thereof connected to said first load for driving said first load to the second of said logic states; a third FET having the gate terminal thereof connected to receive said first input signal, the drain terminal thereof connected to said first power terminal and the source terminal thereof connected to said second load for driving said second load to the first of said logic states; and a fourth FET, enhancement mode, having the gate terminal thereof connected to receive said second input signal, the source terminal thereof connected to said second power terminal and the drain terminal thereof connected to said second load for driving said second load to the second of said logic states.
4. A split load circuit comprising: a first load which must be driven to have a relatively high speed logic transition; a second load which can be driven to have a lower speed logic transition than said first load; a first FET, depletion mode, having the gate and source terminals thereof connected to a first node and the drain terminal thereof connected to a first power terminal; a second FET, enhancement mode, having the gate terminal thereof connected to an input node, the drain terminal thereof connected to said first node and the source terminal thereof connected to a second power terminal; a third FET having the gate terminal thereof connected to said first node, the drain terminal thereof connected to said first power terminal and the source terminal thereof connected to said first load; a fourth FET, enhancement mode, having the gate terminal thereof connected to s≤id input node, the drain terminal thereof connected to said first load and the source terminal thereof connected to said second power terminal; a fifth FET having the gate terminal thereof connected to said first node, the drain terminal thereof connected to said first power terminal and the source terminal thereof connected to said second load; and a sixth FET, enhancement mode, having the gate terminal thereof connected to said input node, the drain terminal thereof connected to said second load and the source terminal thereof connected to said second power terminal.
-BU EAT
OMPI
EP19810901777 1981-05-26 1981-05-26 Split load circuit Withdrawn EP0079884A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1981/000698 WO1982004364A1 (en) 1981-05-26 1981-05-26 Split load circuit

Publications (1)

Publication Number Publication Date
EP0079884A1 true EP0079884A1 (en) 1983-06-01

Family

ID=22161245

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19810901777 Withdrawn EP0079884A1 (en) 1981-05-26 1981-05-26 Split load circuit

Country Status (2)

Country Link
EP (1) EP0079884A1 (en)
WO (1) WO1982004364A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719372A (en) * 1986-02-03 1988-01-12 International Business Machines Corporation Multiplying interface circuit for level shifting between FET and TTL levels

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3218483A (en) * 1964-05-29 1965-11-16 Ibm Multimode transistor circuits
US3378783A (en) * 1965-12-13 1968-04-16 Rca Corp Optimized digital amplifier utilizing insulated-gate field-effect transistors
US3912948A (en) * 1971-08-30 1975-10-14 Nat Semiconductor Corp Mos bootstrap inverter circuit
US3775693A (en) * 1971-11-29 1973-11-27 Moskek Co Mosfet logic inverter for integrated circuits
JPS5198938A (en) * 1975-02-26 1976-08-31
US3995172A (en) * 1975-06-05 1976-11-30 International Business Machines Corporation Enhancement-and depletion-type field effect transistors connected in parallel

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8204364A1 *

Also Published As

Publication number Publication date
WO1982004364A1 (en) 1982-12-09

Similar Documents

Publication Publication Date Title
EP0212584B1 (en) Output circuit device with stabilized potential
US5017807A (en) Output buffer having capacitive drive shunt for reduced noise
US20020149392A1 (en) Level adjustment circuit and data output circuit thereof
US6181165B1 (en) Reduced voltage input/reduced voltage output tri-state buffers
EP0220856A2 (en) Source follower CMOS input buffer
JPH05267603A (en) Integrated circuit
JPS63112893A (en) Semiconductor integrated circuit
US5537059A (en) Output circuit of semiconductor integrated circuit device
US5097148A (en) Integrated circuit buffer with improved drive capability
US5539336A (en) High speed driver circuit with improved off transition feedback
US20030042932A1 (en) Combined dynamic logic gate and level shifter and method employing same
US6084459A (en) Voltage level shifting circuit
US4092548A (en) Substrate bias modulation to improve mosfet circuit performance
JP2000091900A (en) Boot strap type mos driver
US6998668B2 (en) Semiconductor integrated circuit device including a level shifter
US4342928A (en) Circuit and method for voltage level conversion
EP0281113A2 (en) Semi-conductor buffer circuit
JPH11234118A (en) Electronic level shift circuit
JP3256715B2 (en) Current limit output driver
US6236234B1 (en) High-speed low-power consumption interface circuit
EP0079884A1 (en) Split load circuit
JPH10256897A (en) Bus control buffer amplifier
US6919737B2 (en) Voltage-level converter
JPS60236322A (en) Mos transistor circuit
JPH0220922A (en) Bi-mos type logic circuit

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT CH DE FR GB LI LU NL SE

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19830801

RIN1 Information on inventor provided before grant (corrected)

Inventor name: PROEBSTING, ROBERT JAMES