EP0059224B1 - Systeme de codage et de decodage de donnees binaires - Google Patents
Systeme de codage et de decodage de donnees binaires Download PDFInfo
- Publication number
- EP0059224B1 EP0059224B1 EP81902455A EP81902455A EP0059224B1 EP 0059224 B1 EP0059224 B1 EP 0059224B1 EP 81902455 A EP81902455 A EP 81902455A EP 81902455 A EP81902455 A EP 81902455A EP 0059224 B1 EP0059224 B1 EP 0059224B1
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- EP
- European Patent Office
- Prior art keywords
- bit
- data
- bits
- converted
- code
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Definitions
- This invention relates to a binary data encoding system for converting a sequence of binary data to a sequence of binary codes suitable for the recording upon recording the original binary data on a record medium such as a magnetic tape or a magnetic disc, and a decoding system for decoding and converting the sequence of converted binary codes upon reproducing it from the record medium.
- Figure 1 is an explanatory diagram of one example of a conventional encoding system and Figure 1 (a) shows one example of a bit pattern of an original binary data sequence wherein numerals 0 and 1 express logic "0" and "1" respectively and To indicates a bit interval.
- the same Figures (b) and (d) are one example of conventional encoding systems, the same Figure (b) is called an MFM system (modified FM system) and the same Figure (d) is called a 3 PM system (3 position modulation systems).
- MFM system modified FM system
- 3 PM system position modulation systems
- the MFM system is used with magnetic disc devices (3330, 3340,3350 etc.) of IBM firm and the 3 PM system is used with a magnetic disc device (8434) of Uniback firm.
- a conversion algorithm of the MFM system is to convert bits “1" and “0” of an original binary data sequence to "01” and “XO” respectively where "X” becomes a complement logic (1-0 or h 1) of a code bit just preceding thereto. Also a conversion algorithm of the 3 PM system is to divide original data into 3-bit units to convert them to a 6-bit code as shown in the following First Table:
- Figures 1(c) and (e) are waveforms of the recording currents (NRZI signals) for the code sequences encoded according to the MFM system of the same Figure (b) and the 3PM systems of the same Figure (d) respectively.
- values of the expressions (1) and (2) are preferably larger (the abovementioned items (a) and (b)) and also the undermentioned ratio of the spacing between the inversions of maximum magnetization to the period of the demodulating clock signal (the expression (5)) and the undermentioned ratio of the spacing between the inversions of maximum magnetization to that between the inversions of minimum magnetization (the expression (6)) are preferably smaller (the abovementioned items (c) and (d)).
- Japanese Patent Publication A 54-130111 (Application No. 53-36828) describes a binary data encoding system, which divides a binary data sequence at intervals of two bits, and converts the divided two-bit data to codes each consisting of four bits of the same characteristics as the three P.M. coded signals.
- the present invention comprises a binary data encoding system dividing a binary data sequence at intervals of two bits and converting said divided 2-bit data to codes each consisting of four bits, characterised in that data are sensed within a range of six bits immediately preceding the 2-bit data and also within a range of six bits immediately succeeding thereto, said data thus sensed and, in combination with the complement (Y, Z) of the logical sum of either the last two code bits of the preceding 4-bit code or the first two code bits of the succeeding 4-bit code, utilized to convert said 2-bit data to said 4-bit codes in such a way that no less than two to not more than eight "0" code bits are caused to exist between any code bit "1" of said converted code sequence and a code bit "1" next developed therein.
- the invention is a substantial improvement over the MFM system in spacing between the inversions of minimium magnetization, and overthe 3 PM system in ability to produce the demodulating clock signal from a reproduced signal (the spacing between the inversions of maximum magnetization/the period of the demodulating clock signal) and in ability of reproduced waveforms to interfere with one another (the spacing between the inversions of maximium magnetization/the spacing between inversions of minimum magnetization). Also it can decrease the occurrence of errors during the decoding.
- the conversion algorithm is to divide first original data at intervals of two bits and convert those divided 2-bit data to 4-bit codes following the rule of the Third or Fourth Table.
- the ruling properly is to divide original data at intervals of two bits and convert them in accordance with the fundamental conversion table of a Fifth Table.
- Figure 2 is a block diagram of one embodiment to which an encoding system according to the present invention is applied and Figure 4 is a timing chart for explaining its operation.
- the original data are entered into a shift register (6) through an input terminal (1).
- an input terminal 2 has entered thereinto a clock signal b (Figure 4(b)) which signal doubles a clock signal for the original data and further the clock signal b is frequency divided into a signal c with a frequency divided by 2 ( Figure 4(c)) and a signal d with a frequency divided by 4 ( Figure 4(d)) by 1/2 frequency dividers (4) and (5) respectively.
- a shift resistor serial in-parallel out
- the entered original data are delayed one bit at a time with the clock signal c applied to a terminal (T) and delivered through data output terminals (0 7 to Q o ).
- a signal a delivered at that time through the output terminal (Q 2 ) is shown in Figure 4(a).
- Data outputs (0 7 to Q o ) are entered into input terminals (A 7 to A o ) to an ROM (a read only memory, for example, SN74S471 N of TI firm or the like) having an algorithm shown in the undermentioned Sixth Table and a code converted output signal is provided through its output terminals (D 3 to Do).
- This 4-bit output is entered into a shift register (parallel in-serial out) (8) at the resetting terminals (H to E). More specifically, a presetting signal is latched with a synchronized timing signal d ( Figure 4d) applied to a terminal (SFII) for each of 2-bit data to be converted and converted 4-bit codes are delivered, as a serial output signal e ( Figure 4e), to an output terminal (9) by means of the clock signal b ( Figure 4b) applied to the terminal (T).
- the 1/2 frequency dividers (4) and (5) are set in polarity with a synchronization sensing signal (which is entered into an input terminal (3)) such as a data synchronizing signal inserted into the original data sequence for each of predetermined bit lengths.
- the undermentioned Seventh and Eighth Tables are other concrete examples of the conversion algorithm of the novel encoding system.
- the original data are first divided at intervals of two bits and those divided 2-bit data are converted to 4-bit codes following the rule of the Seventh or Eighth Table.
- the Seventh Table is used as patterns when the conversion gives d and k, original data Also original data
- the Eighth Table is a conversion into which the Seventh Table has been partly revised and basically the same as the Seventh Table.
- FIG. 3 is a block diagram of another embodiment to which another encoding system according to the present invention is applied and the timing chart of Figure 4 is also used with that embodiment. Differences between, the other embodiment shown in Figure 3 and the one embodiment shown in Figure 2 reside in that (a) a shift register (6A) has, in addition to the output terminals (Q 7 to Q o ), output terminals (Q 9 to Q 8 ), (b), an OR gate (30), a NOT gate (31) and an AND gate (32) newly added thereto.
- a shift register (6A) has, in addition to the output terminals (Q 7 to Q o ), output terminals (Q 9 to Q 8 ), (b), an OR gate (30), a NOT gate (31) and an AND gate (32) newly added thereto.
- Figure 5 shows a block diagram of one embodiment to which a decoding system according to the present invention is applied and Figure 6 shows a timing chart for explaining the operation thereof.
- a converted code sequence (Figure 4(e)) is entered into an input terminal (10) and a clock signal g ( Figure 6(g)) synchronized therewith is entered into an input terminal (11).
- the clock signal g is frequency divided into a signal i with a frequency divided by 2 ( Figure 6(i)) and a signal j with a frequency divided by 4 ( Figure 6(j)) by 1/2 frequency dividers (17) and (18) respectively.
- the entered converted code sequence is delayed one bit at a time within a shift register (parallel in-serial out) (13) with the clock signal g applied to a terminal (T) and delivered through the output terminals (Q 12 to Q o ).
- Q o designates that output terminal through which a signal largest in delay is delivered, the delay is rendered small in the order of Q 1 , Q 12 .
- a signal A shown in Figure 4(f) is being delivered to the output terminal (Q s ).
- signals at the output terminals (Q o to Q 3 ) are made into the logical sum by a logical sum (OR) gate (15) after which it is entered into an input terminal (A o ) to an ROM (SN 74S471 of TI firm or the like). Also the signals at the output terminals (Q 4 to Q 9 ) are entered into the input terminals (A, to As) while the signals at the output terminals (Q io to Q 12 ) are made into the logical sum by a logic sum (OR) gate (14). Thereafter it entered into the input terminal (Ay).
- the ROM (16) has a decoding conversion algorithm shown in the undermentioned Tenth or Eleventh Tables:
- the decoding algorithm of the Tenth Table is used upon decoding the code sequence converted by the embodiment of Figure 2 and has an algorithm by which a decoding 4-bit codes (specified by the addresses A3 to A 6 ) for the converted code sequence are decoded into the original 2-bit data. in accordance with the conditions for a preceding and a succeeding code pattern (specified by the addresses A 0' , A 1 , A 2 and A 7 ).
- a decoded pattern is delivered to output terminals (Do and D i ).
- a decoded output signal is entered into a shift register (parallel in-serial out) (19) at presetting terminals (G to H).
- the 1/2 frequency dividers (17) and (18) are put in synchronization with each other with a synchronizing signal h (entered into an input terminal (12) and shown in Figure 6(h)) and generate a signal i with a frequency divided by 2 ( Figure 6(i)) and a signal j with a frequency divided by 4 ( Figure 6(j)) respectively.
- the shift register (19) latches presetting input signals thereto that is, signals at input terminals (H and G) with the timing signal j applied to its terminal (SF/L) and also delivers to an output terminal (2) data k (Figure 6(k)) decoded with the demodulating clock signal i applied to its terminal (T).
- the decoding clock signal i is delivered to a clock output terminal (20).
- the decoding algorithm of the Eleventh Table is used in decoding the code sequence converted by the embodiment of Figure 3 and has an algorithm by which decoding 4-bit codes (specified by the addresses A3 to A 6 ) are decoded into the original 2-bit data in accordance with the conditions for a preceding and a succeeding code pattern (specified by the addresses A o , A i , A 2 and A 7 ).
- a decoded pattern is delivered to the output terminals (Do and D 1 ).
- the Third and Fourth Tables for the encoding algorithms used for the purpose of describing the present invention are one concrete example of the present invention and the Seventh and Eighth Tables are other concrete examples of the present invention. Still another encoding algorithm may be used. That is, it is evident that in the encoding system, first, combinations of the original data patterns with the converted codes in the Third and Fourth Tables as well as in the Seventh and Eighth Tables are possible to be any combination of four types of patterns formed of two bits as four types of patterns shown by the original data. Also the logical algorithm and conditions of the converted codes reverse in order with respect to all the data.
- a converted code (Y001) is changed to (100Z) and (E 2 E 1 ) ⁇ (L 1 L 2 ), (L 1 L 2 ) ⁇ (E 2 E 1 ), (L 3 L 4 ) ⁇ (E 4 E 3 ) and (E 4 E 3 ) ⁇ (L 3 L 4 ) are effected.
- Z at that time makes a complement logic of two bit immediately after the code bit Z in the converted code sequence. It is evident that the encoding system of the present invention may be formed of such an encoding method.
- the encoding and decoding systems of the present invention have the excellent ability, as a high density magnetic recording system, as compared with conventional other modulation systems such as in the Second Table, and a construction of the hardware is much simplified. Thus its practical merit is very large.
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc Digital Transmission (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Claims (13)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12445980A JPS5750309A (en) | 1980-09-05 | 1980-09-05 | Encoding and decoding system for binary data |
JP124460/80 | 1980-09-05 | ||
JP12446080A JPS5750310A (en) | 1980-09-05 | 1980-09-05 | Encoding and decoding system for binary data |
JP124459/80 | 1980-09-05 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0059224A1 EP0059224A1 (fr) | 1982-09-08 |
EP0059224A4 EP0059224A4 (fr) | 1984-02-07 |
EP0059224B1 true EP0059224B1 (fr) | 1986-12-03 |
Family
ID=26461138
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP81902455A Expired EP0059224B1 (fr) | 1980-09-05 | 1981-09-04 | Systeme de codage et de decodage de donnees binaires |
Country Status (3)
Country | Link |
---|---|
US (1) | US4496934A (fr) |
EP (1) | EP0059224B1 (fr) |
WO (1) | WO1982000912A1 (fr) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3407832C2 (de) * | 1983-03-03 | 1994-08-11 | Matsushita Electric Ind Co Ltd | Verfahren zum Kodieren und Dekodieren binärer Daten |
JPS59181759A (ja) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | ディジタル符号変換方式 |
GB2141906A (en) * | 1983-06-20 | 1985-01-03 | Indep Broadcasting Authority | Recording of digital information |
US4598326A (en) * | 1983-10-18 | 1986-07-01 | Honeywell Inc. | Digital recording apparatus with disparity reducing encoder |
GB8423165D0 (en) * | 1984-09-13 | 1984-10-17 | Indep Broadcasting Authority | Digital recording/reproducing apparatus |
EP0178813B1 (fr) * | 1984-10-01 | 1993-08-18 | Matsushita Electric Industrial Co., Ltd. | Méthode et appareil pour coder des données numériques |
NL8702905A (nl) * | 1987-12-03 | 1989-07-03 | Philips Nv | Werkwijze en inrichting voor het optekenen van informatie, een registratiedrager, een inrichting voor het uitlezen van de opgetekende informatie, alsmede een codeer- en decodeerschakeling voor toepassing in de opteken- en uitleesinrichting. |
US4908721A (en) * | 1988-05-12 | 1990-03-13 | Digital Equipment Corporation | Improved decoder |
JPH0233221A (ja) * | 1988-07-22 | 1990-02-02 | Matsushita Electric Ind Co Ltd | コード変換装置と復号装置 |
US5014276A (en) * | 1989-02-06 | 1991-05-07 | Scientific Atlanta, Inc. | Convolutional encoder and sequential decoder with parallel architecture and block coding properties |
JP2708859B2 (ja) * | 1989-03-16 | 1998-02-04 | 三洋電機株式会社 | 光ディスク記録装置 |
EP0416930B1 (fr) * | 1989-09-08 | 1997-11-12 | Fujitsu Limited | Circuit de codage et de décodage pour un codage à longueur de course limitée |
DE69026904T2 (de) * | 1989-10-31 | 1997-01-02 | Sony Corp | Schaltung zur digitalen Modulation |
FR2664765B1 (fr) * | 1990-07-11 | 2003-05-16 | Bull Sa | Dispositif de serialisation et de deserialisation de donnees et systeme de transmission numerique de donnees en serie en resultant. |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5311011A (en) * | 1976-07-14 | 1978-02-01 | Sperry Rand Corp | Method and device for coding or decoding binary degital data |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3905029A (en) * | 1970-12-01 | 1975-09-09 | Gen Motors Corp | Method and apparatus for encoding and decoding digital data |
US3906485A (en) * | 1973-06-13 | 1975-09-16 | Ibm | Data coding circuits for encoded waveform with constrained charge accumulation |
US3852687A (en) * | 1973-07-02 | 1974-12-03 | Ibm | High rate digital modulation/demodulation method |
DE2508706C2 (de) * | 1974-05-02 | 1984-10-11 | International Business Machines Corp., Armonk, N.Y. | Schaltungsanordnung zur Codierung von Datenbitfolgen |
US4150404A (en) * | 1975-07-08 | 1979-04-17 | U.S. Philips Corporation | Device for transferring digital information |
US4323931A (en) * | 1976-07-14 | 1982-04-06 | Sperry Corporation | Method and apparatus for encoding and recovering binary digital data |
US4146909A (en) * | 1977-11-21 | 1979-03-27 | International Business Machines Corporation | Sync pattern encoding system for run-length limited codes |
JPS54130111A (en) * | 1978-03-31 | 1979-10-09 | Toshiba Corp | Coding system |
US4337458A (en) * | 1980-02-19 | 1982-06-29 | Sperry Corporation | Data encoding method and system employing two-thirds code rate with full word look-ahead |
JPH05311011A (ja) * | 1992-05-11 | 1993-11-22 | Kanegafuchi Chem Ind Co Ltd | ポリオレフィン系樹脂組成物 |
-
1981
- 1981-09-04 EP EP81902455A patent/EP0059224B1/fr not_active Expired
- 1981-09-04 US US06/355,559 patent/US4496934A/en not_active Expired - Lifetime
- 1981-09-04 WO PCT/JP1981/000218 patent/WO1982000912A1/fr active IP Right Grant
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5311011A (en) * | 1976-07-14 | 1978-02-01 | Sperry Rand Corp | Method and device for coding or decoding binary degital data |
Non-Patent Citations (3)
Title |
---|
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 17, no. 5, October 1974, NEW YORK (US), H. MIESSLER: "Translator for run length limited code", pages 1489-1491 * |
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 1, June 1980, NEW YORK (US), R.E. JENKINS: "1F/2F Phase alignment system", pages 318-319 * |
IEEE TRANSACTIONS ON MAGNETICS, vol. MAG-12, no. 6, November 1976, NEW YORK (US), T. HORIGUCHI et al.: "An optimization of modulation codes in digital recording", pages 740-742 * |
Also Published As
Publication number | Publication date |
---|---|
US4496934A (en) | 1985-01-29 |
EP0059224A4 (fr) | 1984-02-07 |
EP0059224A1 (fr) | 1982-09-08 |
WO1982000912A1 (fr) | 1982-03-18 |
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