EP0034712A3 - Integrated digital semi-conductor circuit - Google Patents
Integrated digital semi-conductor circuit Download PDFInfo
- Publication number
- EP0034712A3 EP0034712A3 EP81100553A EP81100553A EP0034712A3 EP 0034712 A3 EP0034712 A3 EP 0034712A3 EP 81100553 A EP81100553 A EP 81100553A EP 81100553 A EP81100553 A EP 81100553A EP 0034712 A3 EP0034712 A3 EP 0034712A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- conductor circuit
- integrated digital
- digital semi
- semi
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3004565A DE3004565C2 (en) | 1980-02-07 | 1980-02-07 | Integrated digital semiconductor circuit |
DE3004565 | 1980-02-07 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0034712A2 EP0034712A2 (en) | 1981-09-02 |
EP0034712A3 true EP0034712A3 (en) | 1981-09-09 |
EP0034712B1 EP0034712B1 (en) | 1984-02-08 |
Family
ID=6094015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP81100553A Expired EP0034712B1 (en) | 1980-02-07 | 1981-01-26 | Integrated digital semi-conductor circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US4400802A (en) |
EP (1) | EP0034712B1 (en) |
JP (1) | JPS56127998A (en) |
DE (1) | DE3004565C2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57130286A (en) * | 1981-02-06 | 1982-08-12 | Fujitsu Ltd | Static semiconductor memory |
FR2522432A1 (en) * | 1982-02-26 | 1983-09-02 | Radiotechnique Compelec | METHOD FOR OBTAINING RAPID DISCHARGE OF MEMORY MATRIX ROW AND CORRESPONDING DYNAMIC DISCHARGE CIRCUIT |
KR920006985A (en) * | 1990-09-19 | 1992-04-28 | 김광호 | Static load control circuit |
KR960011209B1 (en) * | 1993-12-02 | 1996-08-21 | 삼성전자 주식회사 | Method for reducing the peak current in video ram and samblock |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3736573A (en) * | 1971-11-11 | 1973-05-29 | Ibm | Resistor sensing bit switch |
US3736574A (en) * | 1971-12-30 | 1973-05-29 | Ibm | Pseudo-hierarchy memory system |
US4005393A (en) * | 1974-06-26 | 1977-01-25 | Siemens Aktiengesellschaft | Bipolar semiconductor memory with recharging circuit for capacitively loaded lines |
US4164791A (en) * | 1976-12-17 | 1979-08-14 | Hitachi, Ltd. | Semiconductor memory with equal word line and reference line voltage drop |
US4168490A (en) * | 1978-06-26 | 1979-09-18 | Fairchild Camera And Instrument Corporation | Addressable word line pull-down circuit |
EP0024853A1 (en) * | 1979-08-22 | 1981-03-11 | Fujitsu Limited | Semiconductor memory circuit including a hold current controlling circuit |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5247937U (en) * | 1975-09-29 | 1977-04-05 | ||
JPS5247938U (en) * | 1975-09-29 | 1977-04-05 | ||
JPS5341968A (en) * | 1976-09-29 | 1978-04-15 | Hitachi Ltd | Semiconductor circuit |
FR2443118A1 (en) * | 1978-11-30 | 1980-06-27 | Ibm France | DEVICE FOR POWERING MONOLITHIC MEMORIES |
US4198698A (en) * | 1978-12-06 | 1980-04-15 | Fairchild Camera And Instrument Corporation | Chip select power-down control circuitry |
-
1980
- 1980-02-07 DE DE3004565A patent/DE3004565C2/en not_active Expired
-
1981
- 1981-01-26 EP EP81100553A patent/EP0034712B1/en not_active Expired
- 1981-02-03 US US06/231,005 patent/US4400802A/en not_active Expired - Fee Related
- 1981-02-06 JP JP1675081A patent/JPS56127998A/en active Granted
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3736573A (en) * | 1971-11-11 | 1973-05-29 | Ibm | Resistor sensing bit switch |
US3736574A (en) * | 1971-12-30 | 1973-05-29 | Ibm | Pseudo-hierarchy memory system |
US4005393A (en) * | 1974-06-26 | 1977-01-25 | Siemens Aktiengesellschaft | Bipolar semiconductor memory with recharging circuit for capacitively loaded lines |
US4164791A (en) * | 1976-12-17 | 1979-08-14 | Hitachi, Ltd. | Semiconductor memory with equal word line and reference line voltage drop |
US4168490A (en) * | 1978-06-26 | 1979-09-18 | Fairchild Camera And Instrument Corporation | Addressable word line pull-down circuit |
EP0024853A1 (en) * | 1979-08-22 | 1981-03-11 | Fujitsu Limited | Semiconductor memory circuit including a hold current controlling circuit |
Non-Patent Citations (4)
Title |
---|
IEEE JOURNAL OF SOLID-STATE CIRCUIT, Band SC-13, Nr. 5, Oktober 1978, Seiten 651-656 New York, U.S.A. A. HOTTA et al.: "A high-speed low-power 4096 X 1 Bit Bipolar RAM" * Seiten 652-653, Abschnitt: "III. Cell margin increasing circuitry"; Figur 4 * * |
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Band SC-9, Nr. 5, Oktober 1974, seiten 283-284 New York U.S.A. H. MAYUMI et al.: "A 25-ns read access bipolar 1 kbit TTL RAM" * |
IEEE TRANSACTIONS ON ELECTRON DEVICES, Band ED-26, Nr. 6, Juni New York, U.S.A. K. KAWARADA et al.: "A 4K-bit static 12L memory" * |
SIEMENS FORSCHUNGS- UND ENTWICKLUNGSBERICHT, Band 6, Nr. 2, 1977, Seiten 89-91 Munchen, DE. H. ERNST et al.: "A fast bipolar 1024-bit RAM for high-performance memory systems" * Seiten 88-89, Abschnitt: "2. Circuit design"; Figur 5 * * |
Also Published As
Publication number | Publication date |
---|---|
JPS56127998A (en) | 1981-10-07 |
US4400802A (en) | 1983-08-23 |
DE3004565A1 (en) | 1981-08-13 |
JPH0142079B2 (en) | 1989-09-08 |
EP0034712B1 (en) | 1984-02-08 |
DE3004565C2 (en) | 1984-06-14 |
EP0034712A2 (en) | 1981-09-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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PUAL | Search report despatched |
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AK | Designated contracting states |
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AK | Designated contracting states |
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|
17P | Request for examination filed |
Effective date: 19810929 |
|
ITF | It: translation for a ep patent filed |
Owner name: STUDIO JAUMANN |
|
GRAA | (expected) grant |
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AK | Designated contracting states |
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|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
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STAA | Information on the status of an ep patent application or granted ep patent |
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