EP0017245B1 - Monolithic integrated semiconductor circuit with clock pulse controlled shift register - Google Patents

Monolithic integrated semiconductor circuit with clock pulse controlled shift register Download PDF

Info

Publication number
EP0017245B1
EP0017245B1 EP80101822A EP80101822A EP0017245B1 EP 0017245 B1 EP0017245 B1 EP 0017245B1 EP 80101822 A EP80101822 A EP 80101822A EP 80101822 A EP80101822 A EP 80101822A EP 0017245 B1 EP0017245 B1 EP 0017245B1
Authority
EP
European Patent Office
Prior art keywords
gate
output
register
shift register
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP80101822A
Other languages
German (de)
French (fr)
Other versions
EP0017245A2 (en
EP0017245A3 (en
Inventor
Helmut Rösler
Reinhard Ing. Grad. Gafert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0017245A2 publication Critical patent/EP0017245A2/en
Publication of EP0017245A3 publication Critical patent/EP0017245A3/en
Application granted granted Critical
Publication of EP0017245B1 publication Critical patent/EP0017245B1/en
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H1/00—Details of electrophonic musical instruments
    • G10H1/36—Accompaniment arrangements

Definitions

  • Such a semiconductor circuit is known from US-A-4142433.
  • Such a semiconductor circuit can, for. B. for signal control of electronic devices, for. B. an electronic organ can be used with advantage. So z. B. in such organs, the signal to be evaluated in each case generated by pressing the keys in the manual and passed on from there for evaluation.
  • the automatic generation of a melody accompaniment in an electronic organ requires an automatic recognition of the current state of the game, that is, the recognition of the digital signals generated by the manual. For musical reasons, it is desirable not to let certain playing states, i.e. certain combinations of pressed game keys, influence the generation of the accompaniment. Such a case is e.g. B. given the simultaneous actuation of keys, the associated tones are only apart by a semitone width.
  • the invention is based on the object of specifying a circuit arrangement with which the respective game state is recognized and with which the undesired game states are rendered ineffective.
  • FIGS. 1 to 4. 3 is a semiconductor circuit corresponding to the invention in the block diagram and in FIGS. 1 and 2 an embodiment of the item. 1 and 2 called ring shift registers and in FIG. 4 a system used for generating the signals required for the linkage or regeneration, respectively.
  • the ring shift register shown in FIGS. 1 and 2 is discussed in more detail, although this does not always have to form part of the semiconductor circuit according to the invention. However, its importance is given for many cases, especially when the invention is used for musical purposes.
  • the ring shift register RR shown in FIG. 1 consists of n register cells R; connected in series, the index i passing through the numbers 1, 2, ... n.
  • the individual shift register cells R are designed as quasi-static register cells in the interest of simplifying the circuit, as can be seen from FIG. 2.
  • the accruing, z. B. via the manual of the electronic organ supplied information arrives via the signal input E at - at the same time the feedback of the last register cell R n to the first register cell R 1 mediating OR gate OG to the one input of an AND gate UG, the output of which The first register cell R 1 is provided.
  • the second input of the AND gate UG is controlled by the output of the second register cell R 2 .
  • this output is connected to the second input of the AND gate UG via a negated AND gate (NAND gate) NG.
  • This feedback of the output of a downstream register cell to the input of an upstream register cell has the effect that the input of the upstream register cell, i.e. in the example of register cell R 1 , only receives the signal ONE when the output of the downstream register cell, i.e. in the example of register cell R 2 , a NULL is pending.
  • An auxiliary signal H applied to the second input of the NAND gate NG can also block the AND gate UG if necessary and thus the input of a signal present at the signal input E or via the feedback from the last register cell R n into the first register cell R.
  • the described connection between the output of the register cell R 2 to the AND gate UG and the register cell R has the effect that, due to a ONE pending at the output of the register cell R 2, a pending at the output of the last register cell R n and via the OR Gate OG suppressed ONE to be forwarded, that is, it is eliminated from the information content circulating in the ring shift register RR, so that a correction of the circulating signal is possible in this way by eliminating an undesired ONE.
  • Such a feedback can also be provided between other register cells R i if required be.
  • FIG. 1 also shows a second possibility - to be used as an alternative to the correction option just described - of changing a signal circulating in the ring shift register RR.
  • This is given by an AND gate U ', the output of which is at the reset input R' of the second register cell R 2 and one input of which is at the signal input of the first register cell Ri, while its second input is controlled by an auxiliary signal H if required.
  • This AND gate U ' can only be caused to pass a one to the reset input R * of the register cell R 2 if there is a one at the input of the first register cell R 1 and a corresponding auxiliary signal H at the second input of the AND gate U * . If this is the case, then a ONE present in register cell R 2 is deleted.
  • register cells R 1 , R 2 ,... R n are preferably used as register cells R 1 , R 2 ,... R n . These permit the design of the shift register cells R 1 and R 2 which can be seen in FIG. 2, which are then followed in a similar manner by the register cells R 3 , R 4 ,... R n . Initially, this is still the configuration of the ring shift register RR which is preferably to be used as a signal input and which may possibly be identical to the shift register SR which is used to apply the logic to be described below.
  • the z. B. from the manual of the electronic organ forth signal input E of the ring shift register RR is in an embodiment according to FIG. 2 at an input of a NOR gate G 1 with three inputs, the second input of which is connected to the signal output of the last register cell R n and whose third input is at the output of an AND gate G 4 to be switched by an auxiliary signal H.
  • the output of the first NOR gate (negated OR gate) G 1 leads via a transfer transistor T 1 to be controlled by the clock TM to an inverter G 2 and via this and via a second transfer transistor T 2 to the one input of a second NOR gate G 3 , the second transfer transistor T 2 being controlled by the clock TS. Furthermore, the input of the inverter G 2 is connected to the output of the second NOR gate G 3 via a third transfer transistor T 3 . A clock TSS is provided to control the third transfer transistor T 3 .
  • the output of the second NOR gate G 3 forms the output of the first register cell R i . It is also connected to one input of the previously mentioned AND gate G 4 , the output of which leads back to the first NOR gate G 1 .
  • one first has an input transfer transistor T 4 controlled by the clock TM and an AND gate G 6 provided with three inputs, which is connected with one of its inputs to the output of the first register cell R 1 .
  • the source-drain path of the input transfer transistor T 4 leads on the one hand via the source-drain path of a further transfer transistor T 6 controlled by the clock TSS to the signal output of the second register cell R 2 , on the other hand via the series circuit of an inverter G 5 and a transfer transistor controlled by the clock TS T 5 to the one input of a NOR gate G 7 .
  • This NOR gate G 7 has three inputs, one of which can be controlled via the inverter G 5 , the second through the output of the AND gate G 6 mentioned in the last paragraph and the third via a reset signal.
  • This reset signal is also at the second input of the already mentioned output gate G 3 of the first register stage, which - in contrast to the gate G 7 - is only provided with two inputs.
  • the configuration of the register cells R 3 to R n essentially corresponds to the two cells R 1 and R 2 . So they are also quasi-static register cells.
  • the signal transferred from the respective upstream register cell via a transfer transistor controlled by the clock TM passes via an inverter and a further transfer transistor controlled by the clock TS to the input of a NOR gate, which at the same time forms the output of the cell in question.
  • the output of the input transfer transistor of the relevant register cell Rj controlled by the clock TM is directly connected to the signal output of the NOR gate of the relevant cell.
  • Another input of this NOR gate is used to apply reset pulses.
  • an AND gate corresponding to the AND gate of register cell R 2 can be provided.
  • a ring shift register RR shown in FIG. 2 is able, in a manner similar to an arrangement according to FIG. 1, to correct undesired dual combinations in the fed-in signal, such as those e.g. B. occur while pressing adjacent game buttons in the organ manual, and perform a clean signal of the actual system according to the invention.
  • 12 tone names C, CIS, D, DIS, etc.
  • the intervals between the tones are decisive.
  • the digital signals generated via the manual are successful conditions via the input E into the ring shift register RR, the information already circulating in it being retained with the exception of the signal parts suppressed as a result of the corrective measures mentioned.
  • the semiconductor circuit shown in FIG. 3 forms the core of the invention. This will now be described in more detail.
  • a shift register SR which is preferably to be controlled by a ring shift register RR according to FIG. 2 or FIG. 1 in parallel operation or is identical to this, forms the input of the circuit shown in FIG. 3.
  • This shift register SR like the shift register RR, must also be freed of information contained in it before start-up, which is brought about by a reset signal supplied by a common clock generator.
  • a clock generator which is suitable for supplying the clock pulse sequences TM, TS and TSS, z. B.
  • a clock according to the patent application P 2 845 379.4 (VPA 78 P 1 191; title: digital integrated semiconductor circuit) can be used.
  • the course of the clocks TM, TS and TSS can also be found in this application.
  • the cells of the shift register SR in FIG. 3 and the shift register SRG in FIG. 4 are expediently designed as quasi-static register cells. All these cells and also the further circuit parts provided in an arrangement according to the invention are expediently designed using MOS-IC technology.
  • At least the output of two register cells S i of the shift register SR and in the preferred case the outputs of all register cells S; are connected to the logic L effecting a signal masking, while the individual register cells S i receive their information in parallel operation through the respectively assigned register cell R; of the ring shift register RR received.
  • each of the outputs of the individual register cells is S; of the shift register SR each connected to an input of the logic L.
  • the logic is composed in the usual way of elementary gates, in particular AND gates, OR gates, NAND gates, NOR gates, inverters or exclusive OR gates, in order to implement the desired logic function.
  • the internal circuitry of the logic L is often designed such that a signal for fixing the counter reading of the dual counter Z only appears at the output of the logic for a certain signal present in the shift register SR.
  • the outputs of the two last-mentioned AND gates A 1 and A 2 are each at one of the two inputs of an intermediate gate LA 1 , z. B. an OR gate, which forms a secondary output of the logic L, which is used to control an auxiliary system, for. B. the system shown in Fig. 4, is provided.
  • the main output of the logic L is given in the example by an OR gate 0, the individual inputs of each of one of the intermediate gates LA; the logic L are controlled. This main output serves to fix the counter reading of a digital counter, ie pulse counter Z in the manner already defined above.
  • the clock generator TG provided for clock control of the shift register SR serving to apply the logic L and possibly also the ring shift register RR outputs the clock pulses serving for the clock supply of the shift register SR at the same time to the counting input of a dual counter Z, the Q outputs of which in each case to the first input of an AND -Gatters A are placed, the other input of which is controlled by the main output of the logic L, that is to say by the output of the OR gate 0.
  • OR gate 0 as the output of the logic L means that the counter reading of the dual counter Z is fixed each time, that is to say is passed on as a signal via the AND gate A when sent to ei nem the intermediate gate LA; a signal appears, which may be important for the further system for synchronization reasons.
  • the configuration of the output of the logic L is provided by an AND gate or a NOR gate.
  • a read-only memory ROM is provided, which is occupied in the respectively required manner, that is to say programmed, and is also designed as a matrix memory.
  • Each column line S of this read-only memory ROM which is designed in a known manner, is connected to the signal output of one AND gate UN each.
  • These AND gates UN are divided into groups G of the same size, each of which is one of the signal outputs of those already mentioned and through the intermediate gates LA; the logic L controlled first selection circuit AW 1 are assigned. For example, four such groups G are provided, each containing eight AND gates UN.
  • the first selection circuit AW 1 is set by the logic L, as can be seen from FIG. 3.
  • a further logic acted upon by the secondary outputs of the logic L can be provided in the selection circuit AW I , which ensures that a particular output of the selection circuit AW 1 receives the level ONE, while the other outputs maintain the level ZERO.
  • the number of inputs of the selection circuit AW 1 controlled by the logic L that is to say via its secondary outputs and possibly also via its main output 0, matches the number of its outputs and thus the number of groups G, it is sufficient if everyone by the logic L controlled input of AW 1 controls an AND gate activated by a preselection, through the output of which a flip-flop, e.g. B. RS flip-flop. The nodes of the flip-flop not acted upon by the AND gate then each form an output of the selection AW 1 .
  • the column powers of the read-only memory ROM are assigned to the individual register cells. If you give z. B. in the shift register SRG a signal consisting only of a ONE, it depends on the one hand on the position of the selection circuit and on the other hand by the number of shift cycles given after the introduction of the ONE on the shift register, which parts of the read-only memory ROM are activated.
  • the output gates AG are given as OR gates, each of which has two inputs.
  • the second selection circuit AW 2 can also by logic, for. B. the logic L can be controlled. If the circuit is used to design an electronic organ, however, a manually controlled selection circuit AW 2 will be preferred. she gets then a corresponding, e.g. B. Control task related to the rhythm of the game.
  • the fundamental tone present in the signal present in the shift register SR is determined by the respectively fixed state of the dual counter Z, so that not only the key but also the associated fundamental tone is input into the signal required for controlling the signal generating system SG.
  • This signal then has the task of generating the required accompaniment chord via a digitally controlled tone generator.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Acoustics & Sound (AREA)
  • Multimedia (AREA)
  • Shift Register Type Memory (AREA)
  • Logic Circuits (AREA)
  • Electrophonic Musical Instruments (AREA)

Description

Die Erfindung betrifft eine monolithisch integrierbare digitale Halbleiterschaltung zur Auswertung von aus Gruppen von Dualimpulsen bestehenden Digitalsignalen, bei der der Eingangsteil ein durch einen Taktgeber (TG) getaktetes Schieberegister umfaßt, bei dem die Anzahl der Registerzellen mindestens der Anzahl der Dualstellen der für die Auswertung vorgesehenen Digitalsignale entspricht und der Ausgang mindestens zweier dieser Registerzellen zur Steuerung einer Logikschaltung vorgesehen ist, wobei die Logikschaltung zur Fixierung des Zählstandes eines mit den für den Betrieb des Schieberegisters vorgesehenen Schiebetakten als Zählimpulse beaufschlagten Zählers dient, welcher in Abhängigkeit vom jeweils fixierten Zählstand wenigstens einen weiteren Schaltungsteil steuert.The invention relates to a monolithically integrable digital semiconductor circuit for evaluating digital signals consisting of groups of dual pulses, in which the input part comprises a shift register clocked by a clock generator (TG), in which the number of register cells is at least the number of dual digits of the digital signals provided for the evaluation corresponds and the output of at least two of these register cells is provided for controlling a logic circuit, the logic circuit for fixing the count of a counter acted upon with the shift clocks provided for the operation of the shift register as counting pulses, which controls at least one further circuit part depending on the respectively fixed count .

Aus der US-A-4142433 ist eine derartige Halbleiterschaltung bekannt.Such a semiconductor circuit is known from US-A-4142433.

Eine solche Halbleiterschaltung kann z. B. für die Signalsteuerung elektronischer Geräte, z. B. einer elektronischen Orgel, mit Vorteil eingesetzt werden. So wird z. B. bei solchen Orgeln das jeweils auszuwertende Signal durch die Betätigung der Tasten im Manual erzeugt und von dort für die Auswertung weiter gegeben.Such a semiconductor circuit can, for. B. for signal control of electronic devices, for. B. an electronic organ can be used with advantage. So z. B. in such organs, the signal to be evaluated in each case generated by pressing the keys in the manual and passed on from there for evaluation.

Die automatische Erzeugung einer Melodiebegleitung in einer elektronischen Orgel verlangt eine automatische Erkennung des jeweils vorliegenden Spielzustandes, also die Erkennung der jeweils über das Manual anfallenden Digitalsignale. Aus musikalischen Gründen ist es dabei erwünscht, gewisse Spielzustände, also gewisse Kombinationen von gedrückten Spieltasten, keinen Einfluß auf die Erzeugung der Begleitung nehmen zu lassen. Ein solcher Fall ist z. B. bei der gleichzeitigen Betätigung von Tasten gegeben, deren zugehörigen Töne jeweils nur um eine Halbtonbreite auseinander liegen.The automatic generation of a melody accompaniment in an electronic organ requires an automatic recognition of the current state of the game, that is, the recognition of the digital signals generated by the manual. For musical reasons, it is desirable not to let certain playing states, i.e. certain combinations of pressed game keys, influence the generation of the accompaniment. Such a case is e.g. B. given the simultaneous actuation of keys, the associated tones are only apart by a semitone width.

Der Erfindung liegt die Aufgabe zugrunde, eine Schaltungsanordnung anzugeben, mit welcher der jeweilige Spielzustand erkannt wird, und mit welcher die unerwünschten Spielzustände wirkungslos gemacht werden.The invention is based on the object of specifying a circuit arrangement with which the respective game state is recognized and with which the undesired game states are rendered ineffective.

Diese Aufgabe wird bei einer Halbleiterschaltung der eingangs genannten Art durch die im kennzeichnenden Teil des ersten Patentanspruchs aufgeführten Merkmale gelöst.This object is achieved in a semiconductor circuit of the type mentioned by the features listed in the characterizing part of the first claim.

Mit Hilfe einer der Erfindung entsprechenden Halbleitervorrichtung ist die Möglichkeit gegeben, eine zu der jeweils gespielten Melodie passende Begleitung automatisch zu erzeugen, wobei die entsprechenden Muster für die Begleitung - gesteuert durch den jeweils fixierten Zählstand und entsprechenden Auswahlschaltungen - aus einem entsprechend programmierten Speicher, insbesondere Festwertspeicher, abgerufen werden.With the aid of a semiconductor device according to the invention, there is the possibility of automatically generating an accompaniment suitable for the melody being played, the corresponding patterns for the accompaniment being controlled by the respectively fixed count and corresponding selection circuits from an appropriately programmed memory, in particular read-only memory , can be accessed.

Weiterbildungen der Erfindung ergeben sich aus den Unteransprüchen.Further developments of the invention result from the subclaims.

Die Erfindung wird nun anhand der Fig. 1 bis 4 näher beschrieben. Dabei ist in Fig. 3 eine der Erfindung entsprechende Halbleiterschaltung im Blockschaltbild und in Fig. 1 bzw. 2 eine Ausgestaltung des unter Ziff. 1 und 2 genannten Ringschieberegisters sowie in Fig. 4 eine für die Erzeugung der für die Verknüpfung bzw. Regeneration ggf. benötigten Signale dienende Anlage dargestellt. Zunächst wird auf das in Fig. 1 und 2 dargestellte Ringschieberegister näher eingegangen, obwohl dieses nicht jedesmal einen Bestandteil der erfindungsgemäßen Halbleiterschaltung bilden muß. Seine Bedeutung ist jedoch für viele Fälle, insbesondere beim Einsatz der Erfindung für musikalische Zwecke gegeben.The invention will now be described with reference to FIGS. 1 to 4. 3 is a semiconductor circuit corresponding to the invention in the block diagram and in FIGS. 1 and 2 an embodiment of the item. 1 and 2 called ring shift registers and in FIG. 4 a system used for generating the signals required for the linkage or regeneration, respectively. First, the ring shift register shown in FIGS. 1 and 2 is discussed in more detail, although this does not always have to form part of the semiconductor circuit according to the invention. However, its importance is given for many cases, especially when the invention is used for musical purposes.

Das in Fig. 1 dargestellte Ringschieberegister RR besteht aus n hintereinander geschalteten Registerzellen R;, wobei der Index i die Zahlen 1, 2, ... n durchläuft. Die einzelnen Schieberegisterzellen R; sind im Interesse der Schaltungsvereinfachung als quasistatische Registerzellen ausgebildet, wie dies aus Fig. 2 ersichtlich ist.The ring shift register RR shown in FIG. 1 consists of n register cells R; connected in series, the index i passing through the numbers 1, 2, ... n. The individual shift register cells R; are designed as quasi-static register cells in the interest of simplifying the circuit, as can be seen from FIG. 2.

Die jeweils anfallende, z. B. über das Manual der elektronischen Orgel gelieferte Information gelangt über den Signaleingang E an ein - zugleich die Rückkopplung der letzten Registerzelle Rn auf die erste Registerzelle R1 vermittelndes ODER-Gatter OG an den einen Eingang eines UND-Gatters UG, dessen Ausgang zur Beaufschlagung der ersten Registerzelle R1 vorgesehen ist. Der zweite Eingang des UND-Gatters UG wird vom Ausgang der zweiten Registerzelle R2 gesteuert. Hierzu ist dieser Ausgang über ein negiertes UND-Gatter (NAND-Gatter) NG mit dem zweiten Eingang des UND-Gatters UG verbunden.The accruing, z. B. via the manual of the electronic organ supplied information arrives via the signal input E at - at the same time the feedback of the last register cell R n to the first register cell R 1 mediating OR gate OG to the one input of an AND gate UG, the output of which The first register cell R 1 is provided. The second input of the AND gate UG is controlled by the output of the second register cell R 2 . For this purpose, this output is connected to the second input of the AND gate UG via a negated AND gate (NAND gate) NG.

Diese Rückkopplung des Ausgangs einer nachgeschalteten Registerzelle auf den Eingang einer vorgeschalteten Registerzelle bewirkt, daß der Eingang der vorgeschalteten Registerzelle, also im Beispielsfalle der Registerzelle R1, nur dann das Signal EINS erhält, wenn am Ausgang der nachgeschalteten Registerzelle, also im Beispielsfalle der Registerzelle R2, eine NULL anhängig ist.This feedback of the output of a downstream register cell to the input of an upstream register cell has the effect that the input of the upstream register cell, i.e. in the example of register cell R 1 , only receives the signal ONE when the output of the downstream register cell, i.e. in the example of register cell R 2 , a NULL is pending.

Ein am zweiten Eingang des NAND-Gatters NG angelegtes Hilfssignal H kann bei Bedarf ebenfalls das UND-Gatter UG und damit die Eingabe eines am Signaleingang E bzw. über die Rückkopplung aus der letzten Registerzelle Rn anstehenden Signals in die erste Registerzelle R, blockieren.An auxiliary signal H applied to the second input of the NAND gate NG can also block the AND gate UG if necessary and thus the input of a signal present at the signal input E or via the feedback from the last register cell R n into the first register cell R.

Ersichtlich hat die beschriebene Verbindung zwischen dem Ausgang der Registerzelle R2 auf das UND-Gatter UG und die Registerzelle R, die Wirkung, daß aufgrund einer am Ausgang der Registerzelle R2 anhängigen EINS eine am Ausgang der letzten Registerzelle Rn anhängige und über das ODER-Gatter OG weiterzuleitende EINS unterdrückt, also aus dem im Ringschieberegister RR umlaufenden Informationsinhalt ausgeschieden wird, so daß eine Korrektur des umlaufenden Signals auf diese Weise durch die Beseitigung einer unerwünschten EINS möglich ist. Eine solche Rückkopplung kann bei Bedarf auch zwischen anderen Registerzellen Ri vorgesehen sein.Obviously, the described connection between the output of the register cell R 2 to the AND gate UG and the register cell R has the effect that, due to a ONE pending at the output of the register cell R 2, a pending at the output of the last register cell R n and via the OR Gate OG suppressed ONE to be forwarded, that is, it is eliminated from the information content circulating in the ring shift register RR, so that a correction of the circulating signal is possible in this way by eliminating an undesired ONE. Such a feedback can also be provided between other register cells R i if required be.

In Fig. 1 ist außerdem eine zweite - alternativ zu der soeben beschriebenen Korrekturmöglichkeit anzuwendende - Möglichkeit der Veränderung eines im Ringschieberegister RR umlaufenden Signals eingezeichnet. Diese ist durch ein UND-Gatter U' gegeben, dessen Ausgang am Reseteingang R' der zweiten Registerzelle R2 und dessen einer Eingang am Signaleingang der ersten Registerzelle Ri liegt, während sein zweiter Eingang bei Bedarf durch ein Hilfssignal H gesteuert wird. Dieses UND-Gatter U' kann nur beim gleichzeitigen Vorliegen einer Eins am Eingang der ersten Registerzelle R1 und eines entsprechenden Hilfssignals H am zweiten Eingang des UND-Gatters U* zur Weitergabe einer Eins an den Reseteingang R* der Registerzelle R2veranlaßt werden. Ist dies aber der Fall, dann wird eine gleichzeitig in der Registerzelle R2 vorhandene EINS gelöscht.1 also shows a second possibility - to be used as an alternative to the correction option just described - of changing a signal circulating in the ring shift register RR. This is given by an AND gate U ', the output of which is at the reset input R' of the second register cell R 2 and one input of which is at the signal input of the first register cell Ri, while its second input is controlled by an auxiliary signal H if required. This AND gate U 'can only be caused to pass a one to the reset input R * of the register cell R 2 if there is a one at the input of the first register cell R 1 and a corresponding auxiliary signal H at the second input of the AND gate U * . If this is the case, then a ONE present in register cell R 2 is deleted.

Bevorzugt werden, wie bereits erwähnt, als Registerzellen R1, R2, ... Rn sog. quasistatische Registerzellen verwendet. Diese gestatten die aus Fig. 2 ersichtliche Ausgestaltung der Schieberegisterzellen R1 und R2, denen sich dann in ähnlicher Weise die Registerzellen R3, R4, ... Rn anschließen. Dabei handelt es sich zunächst immer noch um die Ausgestaltung des bevorzugt als Signaleingang zu verwendenden Ringschieberegisters RR, das ggf. mit dem zur Beaufschlagung der noch zu beschreibenden Logik dienenden Schieberegister SR identisch sein kann.As already mentioned, so-called quasi-static register cells are preferably used as register cells R 1 , R 2 ,... R n . These permit the design of the shift register cells R 1 and R 2 which can be seen in FIG. 2, which are then followed in a similar manner by the register cells R 3 , R 4 ,... R n . Initially, this is still the configuration of the ring shift register RR which is preferably to be used as a signal input and which may possibly be identical to the shift register SR which is used to apply the logic to be described below.

Der z. B. vom Manual der elektronischen Orgel her zu beaufschlagende Signaleingang E des Ringschieberegisters RR liegt bei einer Ausgestaltung gemäß Fig. 2 an einem Eingang eines NOR-Gatters G1 mit drei Eingängen, dessen zweiter Eingang mit dem Signalausgang der letzten Registerzelle Rn verbunden ist und dessen dritter Eingang am Ausgang eines durch ein Hilfssignal H zu schaltenden UND-Gatters G4 liegt.The z. B. from the manual of the electronic organ forth signal input E of the ring shift register RR is in an embodiment according to FIG. 2 at an input of a NOR gate G 1 with three inputs, the second input of which is connected to the signal output of the last register cell R n and whose third input is at the output of an AND gate G 4 to be switched by an auxiliary signal H.

Der Ausgang des ersten NOR-Gatters (negiertes ODER-Gatter) G1 führt über einen vom Takt TM zu steuernden Transfertransistors T1 an einen Inverter G2 und über diesen und über einen zweiten Transfertransistor T2 an den einen Eingang eines zweiten NOR-Gatters G3, wobei der zweite Transfertransistor T2 durch den Takt TS gesteuert ist. Ferner ist der Eingang des Inverters G2 über einen dritten Transfertransistor T3 mit dem Ausgang des zweiten NOR-Gatters G3 verbunden. Zur Steuerung des dritten Transfertransistors T3 ist ein Takt TSS vorgesehen.The output of the first NOR gate (negated OR gate) G 1 leads via a transfer transistor T 1 to be controlled by the clock TM to an inverter G 2 and via this and via a second transfer transistor T 2 to the one input of a second NOR gate G 3 , the second transfer transistor T 2 being controlled by the clock TS. Furthermore, the input of the inverter G 2 is connected to the output of the second NOR gate G 3 via a third transfer transistor T 3 . A clock TSS is provided to control the third transfer transistor T 3 .

Der Ausgang des zweiten NOR-Gatters G3 bildet den Ausgang der ersten Registerzelle Ri. Er ist außerdem mit dem einen Eingang des bereits genannten UND-Gatters G4 verbunden, dessen Ausgang auf das erste NOR-Gatter G1 zurückleitet.The output of the second NOR gate G 3 forms the output of the first register cell R i . It is also connected to one input of the previously mentioned AND gate G 4 , the output of which leads back to the first NOR gate G 1 .

Bei der zweiten Registerzelle R2 hat man zunächst einen vom Takt TM gesteuerten Eingangs-Transfertransistor T4 sowie ein mit drei Eingängen versehenes UND-Gatter G6, das mit einem seiner Eingänge mit dem Ausgang der ersten Registerzelle R1 verbunden ist. Die Source-Drainstrecke des Eingangs-Transfertransistors T4 leitet einerseits über die Source-Drainstrecke eines vom Takt TSS gesteuerten weiteren Transfertransistors T6 an den Signalausgang der zweiten Registerzelle R2, andererseits über die Serienschaltung eines Inverters G5 und eines vom Takt TS gesteuerten Transfertransistors T5 an den einen Eingang eines NOR-Gatters G7.In the second register cell R 2 , one first has an input transfer transistor T 4 controlled by the clock TM and an AND gate G 6 provided with three inputs, which is connected with one of its inputs to the output of the first register cell R 1 . The source-drain path of the input transfer transistor T 4 leads on the one hand via the source-drain path of a further transfer transistor T 6 controlled by the clock TSS to the signal output of the second register cell R 2 , on the other hand via the series circuit of an inverter G 5 and a transfer transistor controlled by the clock TS T 5 to the one input of a NOR gate G 7 .

Dieses NOR-Gatter G7 hat drei Eingänge, von denen der eine über den Inverter G5, der zweite durch den Ausgang des im letzten Absatz erwähnten UND-Gatters G6 und der dritte durch ein Resetsignal steuerbar ist. Dieses Resetsignal liegt außerdem am zweiten Eingang des bereits erwähnten Ausgangsgatters G3 der ersten Registerstufe, das - im Gegensatz zum Gatter G7 ― nur mit zwei Eingängen versehen ist.This NOR gate G 7 has three inputs, one of which can be controlled via the inverter G 5 , the second through the output of the AND gate G 6 mentioned in the last paragraph and the third via a reset signal. This reset signal is also at the second input of the already mentioned output gate G 3 of the first register stage, which - in contrast to the gate G 7 - is only provided with two inputs.

Ein Unterschied zwischen der zweiten und ersten Registerzelle ist auch hinsichtlich der beiden UND-Gatter G4 und G6 gegeben, da das UND-Gatter G6 der zweiten Registerzelle R2 mit drei Eingängen versehen und sein Ausgang zur Mitsteuerung des den Ausgang der zweiten Registerzelle R2 bildenden NOR-Gatters G7 vorgesehen ist. Der dritte Eingang des Gatters G6 ist durch die Taktsignale TS gesteuert.There is also a difference between the second and first register cells with regard to the two AND gates G 4 and G 6 , since the AND gate G 6 of the second register cell R 2 has three inputs and its output for controlling the output of the second register cell R 2 forming NOR gate G 7 is provided. The third input of the gate G 6 is controlled by the clock signals TS.

Die Ausgestaltung der Registerzellen R3 bis Rn entspricht im wesentlichen der beiden Zellen R1 und R2. Sie sind also ebenfalls quasistatische Registerzellen.The configuration of the register cells R 3 to R n essentially corresponds to the two cells R 1 and R 2 . So they are also quasi-static register cells.

Das über einen vom Takt TM gesteuerten Transfertransistor von der jeweils vorgeschalteten Registerzelle übernommene Signal gelangt über einen Inverter und einen vom Takt TS gesteuerten weiteren Transfertransistor an den Eingang eines NOR-Gatters, welches zugleich den Ausgang der betreffenden Zelle bildet. Ferner ist der Ausgang des vom Takt TM gesteuerten Eingangs-Transfertransistors der betreffenden Registerzelle Rj, also sein Drain, unmittelbar mit dem Signalausgang des NOR-Gatters der betreffenden Zelle verbunden. Ein weiterer Eingang dieses NOR-Gatters dient der Beaufschlagung mit Resetimpulsen. Schließlich kann ein dem UND-Gatter der Registerzelle R2 entsprechendes UND-Gatter vorgesehen sein.The signal transferred from the respective upstream register cell via a transfer transistor controlled by the clock TM passes via an inverter and a further transfer transistor controlled by the clock TS to the input of a NOR gate, which at the same time forms the output of the cell in question. Furthermore, the output of the input transfer transistor of the relevant register cell Rj controlled by the clock TM, that is to say its drain, is directly connected to the signal output of the NOR gate of the relevant cell. Another input of this NOR gate is used to apply reset pulses. Finally, an AND gate corresponding to the AND gate of register cell R 2 can be provided.

Auch die in Fig. 2 dargestellte Ausgestaltung eines Ringschieberegisters RR ist in der Lage, in ähnlicher Weise wie eine Anordnung gemäß Fig. 1, eine Korrektur unerwünschter Dualkombinationen in dem eingespeisten Signal, wie sie z. B. beim gleichzeitigen Drücken benachbarter Spieltasten im Orgelmanual auftreten, vorzunehmen und ein bereinigtes Signal der eigentlichen Anlage gemäß der Erfindung zuzuführen. Für den Fall der Anwendung auf ein elektronisches Musikgerät sind nämlich 12 Tonnamen (C, CIS, D, DIS, usw.) sowie die Intervalle zwischen den Tönen ausschlaggebend. Für diesen Fall wird man sowohl für das seriell zu beaufschlagende Ringschieberegister RR als auch für das zur Steuerung der Logik dienende Schieberegister SR mindestes 12 Registerzellen R; vorstehen. Die über das Manual erzeugten Digitalsignale gelangen über den Eingang E in das Ringschieberegister RR, wobei auch die bereits in diesem umlaufende Information mit Ausnahme der infolge der genannten Korrekturmaßnahmen unterdrückten Signalteile erhalten bleibt.The configuration of a ring shift register RR shown in FIG. 2 is able, in a manner similar to an arrangement according to FIG. 1, to correct undesired dual combinations in the fed-in signal, such as those e.g. B. occur while pressing adjacent game buttons in the organ manual, and perform a clean signal of the actual system according to the invention. In the case of application to an electronic music device, 12 tone names (C, CIS, D, DIS, etc.) and the intervals between the tones are decisive. In this case, at least 12 register cells R; both for the ring shift register RR to be acted upon serially and for the shift register SR used for controlling the logic; protrude. The digital signals generated via the manual are successful conditions via the input E into the ring shift register RR, the information already circulating in it being retained with the exception of the signal parts suppressed as a result of the corrective measures mentioned.

Die in Fig. 3 dargestellte Halbleiterschaltung bildet den Kern der Erfindung. Diese wird nun näher beschrieben.The semiconductor circuit shown in FIG. 3 forms the core of the invention. This will now be described in more detail.

Ein bevorzugt durch ein Ringschieberegister RR gemäß Fig. 2 oder Fig. 1 im Parallelbetrieb zu steuerndes oder mit diesem identisches Schieberegister SR bildet den Eingang der in Fig. 3 dargestellten Schaltung. Auch dieses Schieberegister SR ist, ebenso wie das Schieberegister RR, vor Inbetriebnahme von einer in ihm enthaltenen Information zu befreien, was durch ein von einem gemeinsamen Taktgeber geliefertes Resetsignal bewirkt wird. Als Taktgeber, der zur Lieferung der Taktimpulsfolgen TM, TS und TSS geeignet ist, kann z. B. ein Taktgeber entsprechend der Patentanmeldung P 2 845 379.4 (VPA 78 P 1 191; Titel: Digitale integrierte Halbleiterschaltung) verwendet werden. Den Verlauf der Takte TM, TS und TSS kann man ebenfalls dieser Anmeldung entnehmen.A shift register SR, which is preferably to be controlled by a ring shift register RR according to FIG. 2 or FIG. 1 in parallel operation or is identical to this, forms the input of the circuit shown in FIG. 3. This shift register SR, like the shift register RR, must also be freed of information contained in it before start-up, which is brought about by a reset signal supplied by a common clock generator. As a clock generator, which is suitable for supplying the clock pulse sequences TM, TS and TSS, z. B. a clock according to the patent application P 2 845 379.4 (VPA 78 P 1 191; title: digital integrated semiconductor circuit) can be used. The course of the clocks TM, TS and TSS can also be found in this application.

Zu bemerken ist ferner, daß auch die Zellen des Schieberegisters SR in Fig. 3 und des Schieberegisters SRG in Fig. 4 zweckmäßig als quasistatische Registerzellen ausgestaltet sind. Alle diese Zellen und auch die weiteren bei einer Anordnung gemäß der Erfindung vorgesehenen Schaltungsteile sind zweckmäßig in MOS-IC-Technik ausgeführt.It should also be noted that the cells of the shift register SR in FIG. 3 and the shift register SRG in FIG. 4 are expediently designed as quasi-static register cells. All these cells and also the further circuit parts provided in an arrangement according to the invention are expediently designed using MOS-IC technology.

Mindestens der Ausgang zweier Registerzellen Si des Schieberegisters SR und im bevorzugten Fall die Ausgänge aller Registerzellen S; sind an die eine Signalmaskierung bewirkende Logik L angeschlossen, während die einzelnen Registerzellen Si ihre Information im Parallelbetrieb durch die jeweils zugeordnete Registerzelle R; des Ringschieberegisters RR erhalten.At least the output of two register cells S i of the shift register SR and in the preferred case the outputs of all register cells S; are connected to the logic L effecting a signal masking, while the individual register cells S i receive their information in parallel operation through the respectively assigned register cell R; of the ring shift register RR received.

Die durch das Schieberegister SR beaufschlagte Logik L hat die Aufgabe, aufgrund der jeweils in das Schieberegister SR gelangenden Information einen durch die Schiebetaktimpulse des Schieberegisters SR als Zählimpulse gesteuerten Digitalzähler, insbesondere Dualzähler Z, zusätzlich zu steuern, indem sie nach Maßgabe ihrer Einstellung und ihres Aufbaus für die Fixierung dieses Zählerstandes sorgt. Bestimmend hierbei ist die Aufgabe, die die Halbleiterschaltung zu erfüllen hat, so daß die Funktion und damit der Aufbau der Logik L verschieden sein kann.The logic L acted upon by the shift register SR has the task of additionally controlling a digital counter, in particular dual counter Z, controlled by the shift clock pulses of the shift register SR, in particular dual counter Z, by virtue of the information arriving in the shift register SR by adjusting them in accordance with their setting and structure ensures the fixation of this meter reading. The determining factor here is the task which the semiconductor circuit has to fulfill, so that the function and thus the structure of the logic L can be different.

In dem auf die Orgel zugeschnittenen Beispielsfall ist jeder der Ausgänge der einzelnen Registerzellen S; des Schieberegisters SR an je einen Eingang der Logik L angeschlossen. Die Logik ist in üblicher Weise aus Elementargattern, insbesondere UND-Gattern, ODER-Gattern, NAND-Gattern, NOR-Gattern, Invertern bzw. Exklusiv-ODER-Gattern zusammengesetzt, um die gewünschte logische Funktion zu realisieren. Häufig ist die innere Schaltung der Logik L so ausgebildet, daß nur bei einem bestimmten im Schieberegister SR vorliegenden Signal am Ausgang der Logik ein Signal zur Fixierung des Zählerstandes des Dualzählers Z erscheint.In the example tailored to the organ, each of the outputs of the individual register cells is S; of the shift register SR each connected to an input of the logic L. The logic is composed in the usual way of elementary gates, in particular AND gates, OR gates, NAND gates, NOR gates, inverters or exclusive OR gates, in order to implement the desired logic function. The internal circuitry of the logic L is often designed such that a signal for fixing the counter reading of the dual counter Z only appears at the output of the logic for a certain signal present in the shift register SR.

Bei dem Ausführungsbeispiel nach Fig. 3 ist der Signalausgang der ersten Registerzelle S, und die Signalausgänge aller übrigen Registerzellen S; - mit Ausnahme der letzten Registerzelle Sm ― an je einen Eingang eines UND-Gatters A1 derart gelegt, daß das UND-Gatter A1 durch die Zellen S1 bis Sm 1 gesteuert ist und demnach nur beim gleichzeitigen Auftreten einer EINS an den Ausgängen dieser - wie bereits bemerkt als quasistatische Schieberegisterzellen ausgestalteten - Registerzellen S1 bis Sm-1 am Ausgang des UND-Gatters A1 eine EINS erscheint. Ferner ist der Ausgang der ersten Registerzelle S1 und der Ausgang der letzten Registerzelle Sm an je einen der beiden Eingänge eines weiteren UND-Gatters A2 angelegt. Die Ausgänge der beiden zuletzt genannten UND-Gatter A1 und A2 liegen an je einem der beiden Eingänge eines Zwischengatters LA1, z. B. eines ODER-Gatters, welches einen Sekundärausgang der Logik L bildet, der zur Steuerung einer Hilfsanlage, z. B. der in Fig. 4 dargestellten Anlage, vorgesehen ist.3, the signal output of the first register cell S, and the signal outputs of all other register cells S; - With the exception of the last register cell S m - placed on one input of an AND gate A 1 in such a way that the AND gate A 1 is controlled by the cells S 1 to Sm 1 and therefore only when a ONE occurs at the outputs this - as already noted as a quasi-static shift register cell - register cells S 1 to S m- 1 a ONE appears at the output of the AND gate A 1 . Furthermore, the output of the first register cell S 1 and the output of the last register cell S m are each applied to one of the two inputs of a further AND gate A 2 . The outputs of the two last-mentioned AND gates A 1 and A 2 are each at one of the two inputs of an intermediate gate LA 1 , z. B. an OR gate, which forms a secondary output of the logic L, which is used to control an auxiliary system, for. B. the system shown in Fig. 4, is provided.

Die Logik L enthält weitere Gatter, falls die der Gesamtanlage zugrundeliegende Aufgabe dies erforderlich macht. Jedoch soll von der näheren Darstellung diesbezüglicher Einzelheiten Abstand genommen werden, da sie für die Erfindung nicht wesentlich sind und ihre nähere Darstellung für einen konkreten Fall zu viel Raum beanspruchen würde. Es genügt, darauf hinzuweisen, daß den UND-Gattern A1 und A2 entsprechende logische Gatter oder Strukturen vorgesehen und durch das Schieberegister SR in jeweils verschiedener Weise angesteuert sind. Der Ausgang dieser einzelnen Unterstrukturen ist jeweils wieder durch ein Zwischengatter LA2, LA3 usw. gegeben, die wiederum als Sekundärausgänge für verschiedene Aufgaben herangezogen werden können.The logic L contains further gates if the task on which the overall system is based makes this necessary. However, the detailed description of relevant details should be avoided since they are not essential for the invention and their detailed representation would take up too much space for a specific case. It suffices to point out that corresponding logic gates or structures are provided for the AND gates A 1 and A 2 and are controlled in different ways by the shift register SR. The output of these individual substructures is again given by an intermediate gate LA 2 , LA 3 etc., which in turn can be used as secondary outputs for various tasks.

Der Hauptausgang der Logik L ist im Beispielsfall durch ein ODER-Gatter 0 gegeben, dessen einzelne Eingänge durch je eines der Zwischengatter LA; der Logik L gesteuert sind. Dieser Hauptausgang dient zur Fixierung des Zählerstandes eines Digitalzählers, also Impulszählers Z in der bereits oben definierten Weise.The main output of the logic L is given in the example by an OR gate 0, the individual inputs of each of one of the intermediate gates LA; the logic L are controlled. This main output serves to fix the counter reading of a digital counter, ie pulse counter Z in the manner already defined above.

Der zur Taktsteuerung des der Beaufschlagung der Logik L dienenden Schieberegisters SR und ggf. auch des Ringschieberegisters RR vorgesehene Taktgeber TG gibt die zur Taktversorgung des Schieberegisters SR dienenden Taktimpulse zugleich an den Zähleingang eines Dualzählers Z, dessen Q-Ausgänge jeweils an den ersten Eingang eines UND-Gatters A gelegt sind, dessen anderer Eingang durch den Hauptausgang der Logik L, also durch den Ausgang des ODER-Gatters 0 gesteuert ist. Die Verwendung eines ODER-Gatters 0 als Ausgang der Logik L führt dazu, daß jedesmal der Zählerstand des Dualzählers Z fixiert, d. h. über die UND-Gatter A als ein Signal weitergegeben wird, wenn an einem der Zwischengatter LA; ein Signal erscheint, was aus Synchronisierungsgründen für die weitere Anlage ggf. von Bedeutung ist. Andererseits sind Fälle denkbar, bei denen die Ausgestaltung des Ausgangs der Logik L durch ein UND-Gatter oder ein NOR-Gatter angebracht ist.The clock generator TG provided for clock control of the shift register SR serving to apply the logic L and possibly also the ring shift register RR outputs the clock pulses serving for the clock supply of the shift register SR at the same time to the counting input of a dual counter Z, the Q outputs of which in each case to the first input of an AND -Gatters A are placed, the other input of which is controlled by the main output of the logic L, that is to say by the output of the OR gate 0. The use of an OR gate 0 as the output of the logic L means that the counter reading of the dual counter Z is fixed each time, that is to say is passed on as a signal via the AND gate A when sent to ei nem the intermediate gate LA; a signal appears, which may be important for the further system for synchronization reasons. On the other hand, cases are conceivable in which the configuration of the output of the logic L is provided by an AND gate or a NOR gate.

Der durch die Wirkung der UND-Gatter A fixierte Zählstand des Dualzählers Z wird im Beispielsfall in einen Schreib-Lesespeicher SLS eingeschrieben, um ggf. auch an anderen Stellen der Halbleiterschaltung verwendet zu werden. Außerdem liegt dieser fixierte Zählstand entweder durch unmittelbare Verbindung der Ausgänge der UND-Gatter A oder durch Vermittlung des Schreib-Lesespeichers SLS an den zur Beaufschlagung eines Rechenwerkes RW, z. B. eines Addierers, dienenden Eingängen desselben.The count of the dual counter Z, which is fixed by the action of the AND gates A, is written into a read-write memory SLS in the example, so that it can also be used at other points in the semiconductor circuit. In addition, this fixed count is either by direct connection of the outputs of the AND gate A or by switching the read-write memory SLS to the application of a computer RW, z. B. an adder, serving inputs thereof.

Andererseits sind die durch die Zwischengatter LA; gegebenen Sekundärausgänge der Logik L zur Steuerung einer Hilfsschaltung, z. B. einer Auswahlschaltung AW1, vorgesehen, welche die Aufgabe hat, eine Anlage zu aktivieren, welche die für die arithmetische Verknüpfung im Rechenwerk noch benötigten weiteren Signale liefert. Diese mit ROM bezeichnete Anlage ist in Fig. 4 dargestellt. Schließlich dient das bei Beaufschlagung des Rechenwerks RW anfallende Ergebnis zur Steuerung weiterer Teile der Anlage, z. B. eines Signalerzeugers SG.On the other hand, those through the intermediate gates LA; given secondary outputs of the logic L for controlling an auxiliary circuit, for. B. a selection circuit AW 1 is provided, which has the task of activating a system that provides the additional signals still required for the arithmetic linkage in the arithmetic unit. This system, designated ROM, is shown in FIG. 4. Finally, the result obtained when the arithmetic unit RW is applied serves to control other parts of the system, e.g. B. a signal generator SG.

Bei der in Fig. 4 dargestellten Vorrichtung zur Erzeugung der dem Rechenwerk RW außer dem Zählstand des Dualzählers Z noch zuzuführenden Verknüpfungssignale ist ein Festwertspeicher ROM vorgesehen, der in der jeweils erforderlichen Weise belegt, also programmiert, und außerdem als Matrix-Speicher ausgestaltet ist.In the device shown in FIG. 4 for generating the link signals to be supplied to the arithmetic logic unit RW in addition to the count of the dual counter Z, a read-only memory ROM is provided, which is occupied in the respectively required manner, that is to say programmed, and is also designed as a matrix memory.

Jede Spaltenleitung S dieses in bekannter Weise ausgestalteten Festwertspeichers ROM ist mit dem Signalausgang je eines UND-Gatters UN verbunden. Diese UND-Gatter UN sind in gleichgroße Gruppen G aufgeteilt, die jeweils einem der Signalausgänge der bereits erwähnten und durch die Zwischengatter LA; der Logik L gesteuerten ersten Auswahlschaltung AW1 zugeteilt sind. Beispielsweise sind vier solche Gruppen G vorgesehen, die jeweils acht UND-Gatter UN enthalten.Each column line S of this read-only memory ROM, which is designed in a known manner, is connected to the signal output of one AND gate UN each. These AND gates UN are divided into groups G of the same size, each of which is one of the signal outputs of those already mentioned and through the intermediate gates LA; the logic L controlled first selection circuit AW 1 are assigned. For example, four such groups G are provided, each containing eight AND gates UN.

Die erste Auswahlschaltung AW1 wird, wie aus Fig. 3 hervorgeht, durch die Logik L eingestellt. Hierzu kann in der Auswahlschaltung AWI eine durch die Sekundärausgänge der Logik L beaufschlagte weitere Logik vorgesehen sein, welche dafür sorgt, daß jeweils ein bestimmter Ausgang der Auswahlschaltung AW1 den Pegel EINS erhält, während die übrigen Ausgänge den Pegel NULL behalten. Falls die Zahl der durch die Logik L, also über deren Sekundärausgänge und ggf. auch über deren Hauptausgang 0, gesteuerten Eingänge der Auswahlschaltung AW1 mit der Anzahl ihrer Ausgänge und damit der Anzahl der Gruppen G übereinstimmt, genügt es, wenn jeder durch die Logik L gesteuerter Eingang von AW1 je ein durch eine Vorwahl aktiviertes UND-Gatter steuert, durch dessen Ausgang je ein Flip-Flop, z. B. RS-Flip-Flop, gestellt wird. Die nicht durch das UND-Gatter beaufschlagte Knoten des Flip-Flops bildet dann je einen Ausgang der Auswahl AW1.The first selection circuit AW 1 is set by the logic L, as can be seen from FIG. 3. For this purpose, a further logic acted upon by the secondary outputs of the logic L can be provided in the selection circuit AW I , which ensures that a particular output of the selection circuit AW 1 receives the level ONE, while the other outputs maintain the level ZERO. If the number of inputs of the selection circuit AW 1 controlled by the logic L, that is to say via its secondary outputs and possibly also via its main output 0, matches the number of its outputs and thus the number of groups G, it is sufficient if everyone by the logic L controlled input of AW 1 controls an AND gate activated by a preselection, through the output of which a flip-flop, e.g. B. RS flip-flop. The nodes of the flip-flop not acted upon by the AND gate then each form an output of the selection AW 1 .

Die Steuerung der UND-Gatter UN der einzelnen Gruppen G durch den jeweils zugeordneten Ausgang der ersten Auswahlschaltung AW1 ist dadurch gegeben, daß der eine der beiden Eingänge jedes UND-Gatter UN der betreffenden Gruppe G mit dem dieser Gruppe zugeteilten Ausgang der Auswahlschaltung AW1 verbunden ist. Zur Steuerung der zweiten Eingänge jedes der UND-Gatter UN dient ein, insbesondere vom Taktgeber TG versorgtes, weiteres Schieberegister SRG. Vorgesehen ist dabei, daß eine der Anzahl der UND-Gatter UN in den einzelnen Gruppe G entsprechende Anzahl von Registerzellen dieses (ggf. ebenfalls als Ring ausgestalteten) Schieberegisters SRG allen Gruppen G gemeinsam zugeteilt ist, indem durch den Ausgang jeder dieser Registerzellen jeweils nur ein einziges UND-Gatter UN jeder Gruppe G gesteuert und dabei jedes UND-Gatter UN jeweils nur einer Registerzelle zugeordnet ist. Damit ist durch Betätigung der Auswahlschaltung AW1 eine Zuordnung der Spaltenleistungen des Festwertspeichers ROM zu den einzelnen Registerzellen gegeben. Gibt man z. B. in das Schieberegister SRG ein nur aus einer EINS bestehendes Signal ein, so hängt es einerseits von der Stellung der Auswahlschaltung und andererseits durch die nach der Einführung der EINS auf das Schieberegister gegebene Anzahl von Schiebetakten ab, welche Teile des Festwertspeichers ROM aktiviert sind.The control of the AND gates UN of the individual groups G by the respectively assigned output of the first selection circuit AW 1 is provided in that the one of the two inputs of each AND gate UN of the group G in question with the output of the selection circuit AW 1 assigned to this group connected is. A further shift register SRG, in particular supplied by the clock generator TG, is used to control the second inputs of each of the AND gates UN. It is envisaged that a number of register cells corresponding to the number of AND gates UN in the individual group G of this (possibly also configured as a ring) shift register SRG is allocated to all groups G by the output of each of these register cells only one single AND gate UN controlled each group G and each AND gate UN is assigned to only one register cell. By actuating the selection circuit AW 1, the column powers of the read-only memory ROM are assigned to the individual register cells. If you give z. B. in the shift register SRG a signal consisting only of a ONE, it depends on the one hand on the position of the selection circuit and on the other hand by the number of shift cycles given after the introduction of the ONE on the shift register, which parts of the read-only memory ROM are activated.

Die Informationsausgabe aus dem Festwertspeicher ROM erfolgt über die Zeilenleitungen Z, die jeweils an den Eingang je eines UND-Gatters UN" gelegt sind. Die Gesamtzahl dieser UND-Gatter UN' ist in ähnlicher Weise wie die Zahl der UND-Gatter UN in - durch jeweils einen Ausgang einer zweiten Auswahlschaltung AW2 gesteuerte - Gruppen G" mit jeweils derselben Anzahl von UND-Gattern UN* unterteilt. Während der eine Eingang des einzelnen UND-Gatters UN* durch die ihm zugeordnete Zeilenleitung Z gesteuert ist, ist der andere Eingang mit dem der betreffenden Gruppe zugeteilten Ausgang der zweiten Auswahlschaltung AW2 verbunden.The information output from the read-only memory ROM takes place via the row lines Z, which are each connected to the input of one AND gate UN ". The total number of these AND gates UN 'is in a manner similar to the number of AND gates UN each an output of a second selection circuit AW 2 controlled - groups G "each with the same number of AND gates UN * divided. While one input of the individual AND gate UN * is controlled by the row line Z assigned to it, the other input is connected to the output of the second selection circuit AW 2 assigned to the group in question.

Ferner ist eine der Anzahl der UND-Gatter UN* in den einzelnen Gruppen G" entsprechende Zahl von einander gleichen Ausgangsgattern AG mit jeweils einer der Anzahl der Gruppen G` entsprechenden Zahl von logischen Eingängen gegeben. Die Signalausgänge dieser Ausgangsgatter AG dienen der Beaufschlagung des Rechenwerks RW der in Fig. 3 dargestellten Anordnung.Furthermore, there is a number of identical output gates AG corresponding to the number of AND gates UN * in the individual groups G ″, each with a number of logic inputs corresponding to the number of groups G`. The signal outputs of these output gates AG are used to load the arithmetic logic unit RW of the arrangement shown in Fig. 3.

Bei dem in Fig. 4 dargestellten Ausführungsbeispiel sind die Ausgangsgatter AG als ODER-Gatter gegeben, die jeweils zwei Eingänge aufweisen. Die zweite Auswahlschaltung AW2 kann ebenfalls durch eine Logik, z. B. die Logik L gesteuert sein. Im Falle der Anwendung der Schaltung auf die Ausgestaltung einer elektronischen Orgel wird man jedoch eine manuell gesteuerte Auswahlschaltung AW2 vorziehen. Sie bekommt dann eine entsprechende, z. B. auf den Spielrhythmus bezogene Steuerungsaufgabe.In the embodiment shown in FIG. 4, the output gates AG are given as OR gates, each of which has two inputs. The second selection circuit AW 2 can also by logic, for. B. the logic L can be controlled. If the circuit is used to design an electronic organ, however, a manually controlled selection circuit AW 2 will be preferred. she gets then a corresponding, e.g. B. Control task related to the rhythm of the game.

Die durch das Rechenwerk RW gesteuerte Signalerzeugungsanlage SG kann z. B. durch einen durch die Ausgangssignale des Rechenwerks RW zu adressierenden Speicher gegeben sein, der insbesondere als Festwertspeicher ausgebildet ist.The signal generation system SG controlled by the arithmetic unit RW can, for. B. be given by the output signals of the arithmetic unit RW to be addressed, which is designed in particular as a read-only memory.

Die in den Fig. 1 bis 4 dargestellte Halbleiterschaltung ist u. a. zur Erkennung des jeweils vorliegenden Spielzustandes im Manual einer elektronischen Orgel und zur selbsttätigen Erzeugung der zu der jeweils gespielten Melodie passenden Begleitung geeignet. Hierzu wird das vom Manual in Form von Digitalimpulsen abgegebene Signal im Ringschieberegister RR von bezüglich der Erzeugung der Begleitung unerwünschten Signalteilen befreit und über die Logik L die Tonart erkannt und der jeweils erkannten Tonart entsprechende Begleitungsfiguren aus dem Festwertspeicher ROM hervorgeholt und über die zweite Auswahlschaltung AW2 entsprechend dem gewünschten bzw. gespielten Rhythmus ausgefiltert und die entsprechende Steuerungsinformation an das Rechenwerk RW gegeben.The semiconductor circuit shown in FIGS. 1 to 4 is suitable, inter alia, for recognizing the current playing state in the manual of an electronic organ and for automatically generating the accompaniment suitable for the melody being played. For this purpose, the signal emitted by the manual in the form of digital pulses in the ring shift register RR is freed from signal parts which are undesirable with regard to the generation of the accompaniment, and the key is recognized via the logic L and accompanying figures corresponding to the respectively recognized key are extracted from the read-only memory ROM and via the second selection circuit AW 2 filtered out according to the desired or played rhythm and given the corresponding control information to the arithmetic unit RW.

Andererseits wird durch den jeweils fixierten Zustand des Dualzählers Z der in dem jeweils im Schieberegister SR vorliegenden Signal vorhandene Grundton ermittelt, so daß also nicht nur die Tonart sondern auch der zugehörige Grundton in das zur Steuerung der Signalerzeugungsanlage SG erforderliche Signal eingegeben wird. Diesem Signal obliegt dann die Aufgabe, über einen digital gesteuerten Tonerzeuger den jeweils erforderlichen Begleitungsakkord zu generieren.On the other hand, the fundamental tone present in the signal present in the shift register SR is determined by the respectively fixed state of the dual counter Z, so that not only the key but also the associated fundamental tone is input into the signal required for controlling the signal generating system SG. This signal then has the task of generating the required accompaniment chord via a digitally controlled tone generator.

Mit dem Einschalten der Anlage ist, wie auch sonst bei Digitalschaltungen üblich, eine selbsttätige Rücksetzung in den Ausgangszustand verbunden, wie bereits Abhandlung der Fig. 2 angedeutet wurde. Dies gilt insbesondere für die Schieberegister RR, SR und SRG sowie für den Dualzähler Z. Aber auch während des Betriebes der Anlage kann eine - insbesondere in periodischen Abständen erfolgende - Rücksetzung erforderlich sein. Diese wird im allgemeinen nach den für die Gesamtanlage geltenden Gesichtspunkten bemessen, von der die Halbleiterschal- tung gemäß der Erfindung im allgemeinen nur ein Teil ist.When the system is switched on, as is also usual with digital circuits, an automatic reset to the initial state is connected, as was already indicated in the treatment of FIG. 2. This applies in particular to the shift registers RR, SR and SRG as well as for the dual counter Z. But even during operation of the system, a reset - in particular at periodic intervals - may be necessary. This is generally calculated according to the rules applicable to the overall system point of view, from which the semiconducting t according erschal- tung the invention in general only a part.

Claims (21)

1. A monolithically integrable digital semiconductor circuit for the analysis of digital signals which comprise groups of dual pulses, wherein the input component comprises a shift register (SR) which is pulsed by means of a clock pulse generator (TG), in which the number of register cells (S;) corresponds at least to the number of the dual digits of the digital signals provided for analysis, and the output of at least two of these register cells (S;) is provided for the control of a logic circuit (L), where the logic circuit serves to fix the count of a counter (Z) which is fed with the shift clock pulses, provided for the operation of the shift register (SR) , by way of counting pulses, and which controls at least one further circuit component (SLS) in dependence upon the fixed count in question, characterised in that the input component comprises a signal input (E) for the serial supply of the digital signals to a ring shift register (RR), that means are provided for the parallel transfer of these signals from the ring shift register (RR) into the shift register (SR) provided for the supply of the logic circuit (L), and that the output of at least one register cell of the ring shift register (RR) can be fed-back to the input of the relevant register cell (Ri) or the register cell (Ri-1) which precedes this register cell (Ri) in the ring via a logic gate (NG; U"; G4; G6) which is to be simultaneously supplied with an auxiliary signal (H).
2. A digital semiconductor circuit as claimed in claim 1, characterised in that the number of the register cells (Ri) of the ring shift register (RR) and the number of the register cells (Si) of the shift register (SR), which is provided for the supply of the logic circuit, corresponds at least to the maximum number of digital places of the signals to be processed (data words).
3. A digital semiconductor circuit as claimed in claim 1 or 2, characterised in that the register cells (Ri, Si) of the two shift registers (RR, SR) are quasi-static shift register cells.
4. A digital semiconductor circuit as claimed in claim 3, characterised in that for the clock pulse supply of the individual shift registers (RR and SR), there is provided a clock pulse generator (TG) which supplies three different clock pulse sequences (TM, TS, TSS) which are permanently assigned to one another in respect of their phase positione.
5. A digital semiconductor circuit as claimed in one of the claims 1 to 4, characterised in that the further circuit component, which is controlled by means of the pulse counter (Z), is designed as a write-read store (SLS).
6. A digital semiconductor circuit as claimed in one of the claims 1 to 5, characterised in that the further circuit component, which is controlled by means of the pulse counter, is designed as a calculating unit (RW), in particular as an adder.
7. A digital semiconductor circuit as claimed in one of the claims 1 to 6, characterised in that the shift register (SR), which directly supplies the logic circuit (L), is likewise designed as a ring shift register.
8. A digital semiconductor circuit as claimed in one of the claims 1 to 7, characterised in that it is produced in integrated MOS technology.
9. A semiconductor circuit as claimed in one of the claims 3 to 8, characterised in that the signal input of a register cell, arranged in series in the ring shift register (RR) in the direction of the signal transfer, for example the first register cell (Ri), is connected to the first input of an AND-gate (U*), which is also controlled by means of an auxiliary signal (H), and the output of this AND-gate (U*) is connected to the reset input of a following register cell, e. g. the second register cell (R2).
10. A semiconductor circuit as claimed in one of the claims 3 or 9, characterised in that the output of a register cell, which follows in the ring shift register (RR) in the direction of the signal transfer, e. g. the second register cell (R2), is connected to the first input of a NAND-gate (NG) which moreover can be controlled by means of the auxiliary signal (H) and whose output is connected via an AND-logic-link (UG) to the input of a preceding register cell, e. g. the first register cell (Ri).
11. A semiconductor circuit as claimed in one of the claims 1 to 10, characterised in that the signal input (E) of the ring shift register (RR) is connected to a first-OR-gate (OG), which is controlled by means of the signal output of the last register cell (Rn), and the output of this OR-gate (OG) is provided either for the direct control of the first register cell (Ri) or for the indirect control of the first register cell (Ri) via an AND-gate (UG).
12. A semiconductor circuit as claimed in claim 3 and 11, characterised in that the input of the first register cell (Ri) is formed by a NOR-gate (Gi) which has three inputs, that one input of this NOR-gate (G1) is connected to the signal input (E) of the ring shift register (RR), a second input is connected to the output of an AND-gate (G4) which is controlled by means of the output of the first register cell (Ri) and by means of the auxiliary signal (H), and a last input of this NOR-gate (Gi) is connected to the signal output of the last register cell (Rn) of the ring shift register (RR).
13. A semiconductor circuit as claimed in claims 1 to 12, characterised in that in the logic unit (L) at least a section of the signal outputs of the shift register (SR) which controls the logic unit, are each connected to an input of a combination of at least two AND-gates (Ai, A2), and the outputs of these AND-gate (A1, A2) are combined via an intermediate gate (LA;) which forms a secondary output of the logic unit (L).
14. A semiconductor circuit as claimed in claim 13, characterised in that the intermediate gates (LA1) are combined via an output gate (0) which is designed in particular as an OR-gate and which forms the main output of the logic unit (L).
15. A semiconductor circuit as claimed in claim 13 or 14, characterised in that the intermediate gates (LA1) are designed at least in part as OR-gates.
16. A semiconductor circuit as claimed in claim 14 or 15, characterised in that the intermediate gates (LAi) and the output gate (0) lead at their output end to a signal selection circuit (AW1), with which a read-only store (ROM), designed as a matrix store, can be addressed, and that the store outputs are connected to the calculating unit (RW) for supply with items of control information.
17. A semiconductor circuit as claimed in the claims 1 to 16, characterised in that those outputs (Q), which convey the count, of the dual counter (Z), which is controlled by means of a clock pulse generator (TG) in common with the shift register (SR) which controls the logic unit (L), are each provided to supply the calculating unit (RW), in each case via an AND-gate (A), which is controlled by means of the output of the logic unit (L), either directly or via write-read store (SLS).
18. A semiconductor circuit as claimed in the claims 13 to 17, characterised in that each column line (S) of the read-only store (ROM) is connected to the signal output of an AND-gate (UN), that moreover the total number of these AND-gate (UN) is divided into groups (G) of equal size, and each of these groups (G) is assigned to a signal output of the first signal selection circuit (AW;) which is to be set by means of the logic unit (L), that moreover a clock-pulse- controlled further shift register (SRG), (e. g. ring shift register), is provided, which is supplied with a digital signal, and a number of register cells of this shift register (SRG), corresponding to the number of AND-gates (UN) in the individual groups (G), are each connected to an AND-gate (UN) of each of the groups (G) in such manner that when the individual register cell is actuated by means of an appropriate signal being passed, in each of the groups G only one AND-gate (UN) responds.
19. A semiconductor circuit as claimed in claim 18, characterised in that each row line (Z) of the read-only-matrix store (ROM) is connected to the first input of an AND-gate (UN'), and the total number of these AND-gates (UN*) is divided into groups (G') of equal size which are each assigned to a signal output of a second selection circuit (AW2), that for this purpose the other input of the AND-gates (UN*), which are combined in a group (G'), is connected to the associated signal output of a second selection circuit (AW2), that moreover a number of output gates (AG), which are identical to one another, which number corresponds to the number of AND-gates (UN) in the individual groups (G'), is provided having a number of signal inputs which corresponds to the number of groups (G'), and in each case one signal input of each of these output gates (AG) is connected to the output of an ANG-gate (UN*) of each group (G*).
20. A semiconductor circuit as claimed in claim 19, characterised in that the output gates (AG) are provided for the control of a calculating unit (RW), which is simultaneously supplied with the count which is fixed via the logic (L).
21. A device as claimed in claim 20, characterised in that the output gates (AG) are designed as OR-gates.
EP80101822A 1979-04-10 1980-04-03 Monolithic integrated semiconductor circuit with clock pulse controlled shift register Expired EP0017245B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19792914518 DE2914518A1 (en) 1979-04-10 1979-04-10 MONOLITHICALLY INTEGRATED SEMICONDUCTOR CIRCUIT
DE2914518 1979-04-10

Publications (3)

Publication Number Publication Date
EP0017245A2 EP0017245A2 (en) 1980-10-15
EP0017245A3 EP0017245A3 (en) 1981-12-02
EP0017245B1 true EP0017245B1 (en) 1985-07-31

Family

ID=6067991

Family Applications (1)

Application Number Title Priority Date Filing Date
EP80101822A Expired EP0017245B1 (en) 1979-04-10 1980-04-03 Monolithic integrated semiconductor circuit with clock pulse controlled shift register

Country Status (4)

Country Link
US (1) US4403334A (en)
EP (1) EP0017245B1 (en)
JP (1) JPS55140900A (en)
DE (1) DE2914518A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4402244A (en) * 1980-06-11 1983-09-06 Nippon Gakki Seizo Kabushiki Kaisha Automatic performance device with tempo follow-up function
US4612659A (en) * 1984-07-11 1986-09-16 At&T Bell Laboratories CMOS dynamic circulating-one shift register
JP2560317Y2 (en) * 1993-09-09 1998-01-21 大同ほくさん株式会社 Bathtub

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3530284A (en) * 1968-03-25 1970-09-22 Sperry Rand Corp Shift counter having false mode suppression
US3716725A (en) * 1971-01-04 1973-02-13 Chicago Musical Instr Co Ring counter
US3889568A (en) * 1974-01-31 1975-06-17 Pioneer Electric Corp Automatic chord performance apparatus for a chord organ
US4019417A (en) * 1974-06-24 1977-04-26 Warwick Electronics Inc. Electrical musical instrument with chord generation
DE2539950C3 (en) * 1975-09-09 1981-12-17 Philips Patentverwaltung Gmbh, 2000 Hamburg Automatic bass chord
JPS52137314A (en) * 1976-05-13 1977-11-16 Kawai Musical Instr Mfg Co Ltd Code discriminator of automatic player
JPS5333113A (en) * 1976-09-09 1978-03-28 Nippon Gakki Seizo Kk Priority selector
US4099048A (en) * 1976-11-09 1978-07-04 Westinghouse Electric Corp. Count logic circuit
US4300430A (en) * 1977-06-08 1981-11-17 Marmon Company Chord recognition system for an electronic musical instrument
US4282786A (en) * 1979-09-14 1981-08-11 Kawai Musical Instruments Mfg. Co., Ltd. Automatic chord type and root note detector

Also Published As

Publication number Publication date
DE2914518A1 (en) 1980-10-23
US4403334A (en) 1983-09-06
EP0017245A2 (en) 1980-10-15
JPS55140900A (en) 1980-11-04
EP0017245A3 (en) 1981-12-02

Similar Documents

Publication Publication Date Title
DE2851628A1 (en) DIGITAL COMPUTER
EP0038947A2 (en) Programmable logic array
DE3444770A1 (en) ELECTRONIC VOLUME CONTROL CIRCUIT
DE2750344C2 (en) Logic circuit for operating any subset of a plurality of devices
DE3427669C2 (en) Signal processing circuit
DE3743586C2 (en)
EP0628832A2 (en) Integrated circuit with register stages
EP0017245B1 (en) Monolithic integrated semiconductor circuit with clock pulse controlled shift register
DE3018509C2 (en) Shift register
DE3007824A1 (en) PROGRAMMABLE FREQUENCY DIVIDER
EP0021084B1 (en) Solid-state integrated semi-conductor memory
DE3511375C2 (en)
DE2133729C3 (en) Arrangement with a cascade connection of a number of storage elements
DE2850652C2 (en) Digital semiconductor circuit
EP0030034B1 (en) Digital semiconductor circuit for an electronic organ
EP0043093B1 (en) Digital semiconductor circuit for an electronic organ
DE4422784C2 (en) Circuit arrangement with at least one circuit unit such as a register, a memory cell, a memory arrangement or the like
DE2722981B2 (en) Digital filter for binary signals
DE1524122A1 (en) Electronic data processing system with time allocation of memory access
DE3036849C1 (en) Circuit arrangement for controlling microinstructions with different execution times
DE2836873C2 (en) Random access storage system
DE4007615A1 (en) ROM CIRCUIT
EP0019865B1 (en) Digital semiconductor circuit
EP0025511A2 (en) Control device for executing instructions
DE1524160B2 (en) CIRCUIT ARRANGEMENT FOR OVERLAPPED CONTROL OF THE DATA FLOW IN DATA PROCESSING SYSTEMS

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): FR GB

17P Request for examination filed

Effective date: 19810410

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Designated state(s): FR GB

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): FR GB

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19881118

GBPC Gb: european patent ceased through non-payment of renewal fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19881229

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST