EP0011576A1 - Polyphone Syntheseschaltung für periodische Signale unter Anwendung digitaler Techniken - Google Patents

Polyphone Syntheseschaltung für periodische Signale unter Anwendung digitaler Techniken Download PDF

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Publication number
EP0011576A1
EP0011576A1 EP79400886A EP79400886A EP0011576A1 EP 0011576 A1 EP0011576 A1 EP 0011576A1 EP 79400886 A EP79400886 A EP 79400886A EP 79400886 A EP79400886 A EP 79400886A EP 0011576 A1 EP0011576 A1 EP 0011576A1
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Prior art keywords
block
memory
synthesizer
generator
group
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EP79400886A
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English (en)
French (fr)
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EP0011576B1 (de
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Christian Jacques Deforeit
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Deforeit Christian Jacques
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Individual
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Priority claimed from FR7832727A external-priority patent/FR2442485A1/fr
Priority claimed from FR7907339A external-priority patent/FR2452145A2/fr
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Priority to AT79400886T priority Critical patent/ATE3918T1/de
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    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H7/00—Instruments in which the tones are synthesised from a data store, e.g. computer organs
    • G10H7/08—Instruments in which the tones are synthesised from a data store, e.g. computer organs by calculating functions or polynomial approximations to evaluate amplitudes at successive sample points of a tone waveform
    • G10H7/10—Instruments in which the tones are synthesised from a data store, e.g. computer organs by calculating functions or polynomial approximations to evaluate amplitudes at successive sample points of a tone waveform using coefficients or parameters stored in a memory, e.g. Fourier coefficients
    • G10H7/105—Instruments in which the tones are synthesised from a data store, e.g. computer organs by calculating functions or polynomial approximations to evaluate amplitudes at successive sample points of a tone waveform using coefficients or parameters stored in a memory, e.g. Fourier coefficients using Fourier coefficients

Definitions

  • the present invention relates to a polyphonic synthesizer of periodic signals, using digital techniques and more generally electronic, polyphonic musical instruments comprising one or more of such a synthesizer.
  • Each periodic signal results from a succession of digital samples produced in particular from a memory of waveform samples, read at variable frequency, and then converted into an analog form.
  • the present invention relates to a synthesizer in which the samples are read at variable frequency, from several pulse signals produced by generators included in the synthesizer.
  • the synthesizer behaves like a set of independent signal generators controlled from a set of memories which each contain at least the amplitude of an output signal.
  • the synthesizer performs, in 1 s an t each memory, a digital-analog conversion, to convert the amplitude data read and an instantaneous phase value, into an analog, positive or negative, voltage or current step.
  • An object of the present invention is to eliminate this drawback by eliminating the synthesis of the signals not requested. Also, during operation, only the memories relating to the signals to be produced are used.
  • Another object of the present invention is to take advantage of the time savings achieved to allow the synthesis of additional signals or to increase the number of possible periodic signals.
  • the invention solves the problem of limiting the work of the synthesizer to the production of the only signals requested, by organizing the data in the control memories so that there is a sequence between those data. Only the significant data are included in this sequence. The reading of the data in the control memories, from the pulse generators and the production of the corresponding samples, therefore take place according to the determined sequence, which is executed repeatedly.
  • the external operating means of the synthesizer can modify the sequence of data in the control memories at any time and replace it with a new sequence. They can also modify data used in the summary without changing the flow.
  • each control memory must contain, in addition to the data used for the production of a sample, additional information which is read by the control means of the synthesizer and is used by them to determine the next memory in the sequence.
  • all of the control memories are divided into memory groups res, pulse generator, each group additionally containing an additional memory for containing a common submultiple of the instantaneous phase of several periodic signals and each memory comprising an area for receiving addressing information from another Memory of the same group.
  • control memory is divided into groups determined by construction, limits the number of elementary sound components associated with each generator to the number of memories of a group minus one. As all the groups are rarely all used together, a greater or lesser number of memories remain unused most of the time.
  • control memories of the synthesizer are no longer divided into groups, each memory being able to be assigned to any generator.
  • Each memory includes addressing information from another memory, for carrying out the sequence.
  • control memories are not limited to that listed previously. This allows the lar ges possibilities for synthesizer commands by simple write operations in RAM.
  • the present invention provides a significant reduction in these writing operations due to the sequence. Likewise, the internal operations of the synthesizer are reduced.
  • Optimizing the read and convert operations also increases the design flexibility of the synthesizer.
  • the size of the memory groups can be modified to increase or decrease the number of possible signals, without increasing the complexity of the operation.
  • the number of generators and groups can vary, allowing the synthesis of new series of signals whose frequencies are not necessarily in relation to those of other generators.
  • the frequencies of these generators can be variable or random.
  • the total processing time of the synthesizer operations is constantly reduced to a minimum and the use of the memories is optimal.
  • the reduction in processing time makes it possible to reduce the time difference between the change of state of a generator and the calculation of the samples of the corresponding sound components.
  • a digital musical synthesizer is built around a waveform memory containing a digital representation, point by point, of a period (or a portion of a period, if there are symmetries) d 'a periodic waveform.
  • the input for addressing the memory receives so-called “phase” signals and the output delivers the data or signals of corresponding "amplitude".
  • the waveform memory therefore transcodes a digital signal phase into a digital amplitude signal, which is then converted to analog form.
  • digital phase signals must be applied successive to waveform memory. The latter then delivers successive amplitude signals applied to the digital-analog converter. These analog signals are filtered to eliminate quantization noise and the analog waveform is rendered.
  • the waveform memory may contain a differential representation of this waveform. Each numerical value represents the difference between the amplitude of the point considered of the waveform and that of the previous point.
  • the digital to analog converter is then followed by an integrator which renders the final waveform.
  • This type of synthesis has the advantage of allowing the use of digital information of reduced size (8-bit words for amplitude) without sacrificing the quality of the final result equivalent to that of a direct synthesis using size information. larger (16 bit).
  • the first method consists in transmitting, to this memory, addressing signals at a constant frequency (very high) but whose phase difference between two consecutive addressed values varies according to the final frequency to be produced. Although requiring only a single clock for all frequencies, this method requires complex circuits necessarily combined with the control circuits of the synthesizer (keyboard, pedals, game selection circuits, etc.).
  • the second method consists in transmitting to the sample memory variable frequency addressing signals directly proportional to the frequency to be produced, this making it possible to address the memory with constant phase differences whatever the frequency.
  • the synthesizer must include several generators which can be integrated and a logic for associating the generators and the control data.
  • the present invention relates to a synthesizer using the second synthesis method (multiple frequencies) in combination with a differential representation of the amplitude data, preferably.
  • This virtual keyboard then constitutes a physical border between the synthesizer and the rest of the musical instrument.
  • Such a synthesizer lends itself particularly well to an association with a microcomputer vis-à-vis which it behaves like a simple peripheral.
  • the virtual keyboard is now the essential organ of the synthesizer from which all the commands come. It includes a set of memories which can therefore be addressed from inside the synthesizer for synthesis operations, and from outside the synthesizer for synthesis commands (controls of the frequencies and amplitudes of the signals to be produced).
  • the user accesses the virtual keyboard via an IT system which is not the subject of this request.
  • An action on a key or pedal of the instrument is detected by the computer system, which determines actions on several memories of the "virtual keyboard", according to a program recorded in the computer system.
  • This makes it possible to obtain the production of complex signals which are the sum of several elementary periodic signals of the synthesizer In particular, if these periodic signals are sinusoids, the synthesis carried out is an additive synthesis or Fourier synthesis.
  • Figure 1 shows the block diagram of the synthesizer according to the invention.
  • the synthesizer is coupled to an external microcomputer system M via a set of connections called "bus" 2.
  • This bus transmits address selection signals, data signals and control signals of writing and possibly reading, for of the synthesizer.
  • the microcomputer system is connected to one or more K organ keyboard, and also, if necessary, to a pedal board of buttons, pull tabs, or any device for entering data or events or for presenting information, which is not shown.
  • the microcomputer system places data in the memories of the virtual keyboard 1, according to the events which it takes into account (pressing or releasing of the keys, buttons, drawbars, etc.), of a recorded program and descriptive data of the tones or timbres of the sounds which are produced by the synthesizer.
  • the virtual keyboard 1 comprises a set of memories which are selected using an address memory 3. Access to these memories is made, on the one hand from the microcomputer, and on the other hand from the other synthesizer circuits. Multiplexer circuits, not shown in the figure, allow these two accesses, avoiding conflicts.
  • This virtual keyboard 1 is divided into groups.
  • the inte addressing of a group memory is done using two signals, one, I, to designate the group and the other N, to designate the memory in group I.
  • the synthesizer also comprises a determined number of rectangular signal generators designated as a whole by the reference 6.
  • rectangular signal is meant any binary signal, square signal or impulse signal.
  • generators of periodic signals whose repetition frequencies are distributed according to the 12 semitones of an octave, and also 4 generators of variable frequency, either with analogical control by tension or current, or with com digital command.
  • One of these generators can also be a noise generator, that is to say a generator at random frequency.
  • the number of groups is equal to that of the generators.
  • the selection of the memories of a group by the read control means at the same time entails the selection of the signal from a generator, using a multiplexer 7.
  • the selection address of said group is kept in a memory 8.
  • This selection address is applied on the one hand to the multiplexer 7 for the selection of the signal of a generator and on the other hand, to the address memory 3 for the selection of the corresponding group.
  • the memories 8 and 3 can moreover be combined.
  • the signal from the selected generator is used to increment. instantaneous phase data common to the signals produced by the entire corresponding group.
  • an incrementation and memory circuit 9 is coupled to the multiplexer 7, by means of a control circuit -10, and to the virtual keyboard 1. The details of the structure and operation of these circuits will appear in the following.
  • the calculation circuit 11 receives the instantaneous phase incremented and memorized by the circuit 9, the octave rank number 0 and the waveform number F read in a memory of a group of the virtual keyboard and delivers the value ⁇ A an amplitude step.
  • the circuit 11 includes for example a memory of waveform samples which automatically delivers the data ⁇ A read at an address formed by the aforementioned digital input signals.
  • the multiplication circuit 12 performs the multiplication of the value ⁇ A by the amplitude value A read in the memory of the virtual keyboard and delivers the numerical value ⁇ A.
  • the converter 13 transforms this value ⁇ A into an analog step of current or voltage which is then amplified in 14 and diffused by 15.
  • Figure 2 describes the structure of the virtual keyboard. This structure is important. It allows to understand the functioning of the synthesizer as a whole
  • the virtual keyboard is divided into 16 memory groups, as many groups as there are generators 6. Each group is itself divided into 16 memory blocks of 16 bits each.
  • Each memory block is further divided into four words, of 4 bits each (it is this last division which separates on figure 1).
  • each word contains at least one piece of information.
  • the blocks are read one by one and the information they contain is transferred and used by other circuits.
  • the address memory 3 selects, by its content, a block of the virtual keyboard, from among the 256.
  • the selection address has 2 parts, a 4-bit part specifying the group number I and a 4-bit part specifying the number N of a block in the group.
  • the four words it contains relate respectively, from left to right, to the number N1 of the next block to be read in the group (4 bits), to the number I 'of the next group when the processing relating to this group is completed. , and of the two parts (high and low) of the instantaneous phase ⁇ of the fundamental signal.
  • Reading this block therefore makes it possible to obtain the 3 pieces of information Nl, I 'and ⁇ in parallel.
  • each block is not limited to the only described above.
  • an analog output channel number, etc. can be specified.
  • the value N2 is used to specify the new block to be read in the group.
  • Reading this new block makes it possible to acquire new data F, 0, A and N3 and so on.
  • the sequence of the reading of the blocks of a group is such that all the blocks of the group are not necessarily read. If an N value is never specious in this block, the corresponding block will be ignored. Similarly, the reading of the block is sequential, but the order in which this reading is made is not necessarily the order of the values of N.
  • FIG. 3 represents a flowchart which describes the sequence of the functions of the synthesizer.
  • the synthesizer performs a test, 21 to find out whether the generator number 1 (selected by the multiplexer 7) has changed state.
  • the complete processing of the data of a group is therefore only carried out every half-period of the corresponding generator.
  • An active signal is only issued by the exclusive OR if the two inputs are different.
  • circuit 10 does not deliver any active signal to the circuit 9, it then controls the transmission, by the circuit 8, of the following value I to the address memory 3.
  • the synthesis of the analog levels of the signals of the block previously read n was therefore not carried out.
  • the next generator test is then performed (functions 20 and 21, Figure 3) and so on.
  • FIG. 4 gives the detail of the structure of the converter.
  • phase ⁇ , harmonic or octave 0 and waveform F values are applied simultaneously to a circuit 30.
  • This circuit 30 generates an address applied to a step memory 31.
  • This memory contains in makes successive samples of one or more waveforms, in differential representation.
  • the amplitude difference ⁇ A lu is added to the previous amplitude to obtain the new amplitude of the analog signal.
  • a multiplier circuit 12 performs the product of the value 5 A by the actual amplitude A read in the block of the virtual keyboard 1.
  • the result ⁇ A is then applied to two analog digital converters 32 and 33 controlled one or the other by a control circuit 35.
  • This variant makes it possible to be able to deliver different signals to several different analog outputs, the number of ecant outputs, of course, given only by way of example.
  • analog outputs are also made from information contained in the virtual calendar. For example, only three bits are used for choosing one of eight waveforms, the fourth bit being assigned to the choice of the analog channel.
  • control circuit 35 is for example a flip-flop.
  • One of the outputs of the flip-flop authorizes the transmission of data to a converter, while the other output prohibits transmission to the other converter.
  • the structure of the converters is known, this having already been described in the aforementioned French patent application No. 77 202 45, in particular in FIG. 4.
  • they each include an adder-subtractor circuit, an up-down counter and a circuit integrator.
  • Amplifiers 36 and 37 and loudspeakers 38 and 39 are followed respectively.
  • Analog filtering circuits having particular frequency responses can obviously be inserted in each analog channel.
  • Such filtering circuits called “formants”
  • the synthesizer has a sufficient number of analog output channels to separate the complex signals from each other.
  • the circuit 35 is constituted, for example by a decoder circuit.
  • the phase value 9 is multiplied by the value 0 for the production of harmonics. In the case where the number J corresponds to the octaves with respect to the fundamental, phase 9 simply undergoes a number of shifts to the left equal to the number 0.
  • the multiplier circuit 12 can also be constituted by a read only memory.
  • the digital input values ⁇ A and A constitute the address of a value in memory. This value is then the product Ax ⁇ A.
  • An improved converter structure makes it easier to obtain a higher number of analog output channels.
  • all of the up-down-counter circuits are replaced by a commercial digital-analog converter circuit, for example a current 8-bit model.
  • This converter is then followed by a demultiplexer circuit which also receives the channel selection information read in the memory of the virtual keyboard.
  • the channel selection control circuit is no longer necessary, this selection being carried out directly in the demultiplexer which generally includes an incorporated decoding circuit.
  • Each output channel of the demultiplexer is then connected to the input of an integrator with the same characteristic as the integrator of the converter described above.
  • each analog output channel can, in addition, include filtering circuits adapted to a L ype signal or stamp.
  • the improved converter operates as follows: during a cycle for reading the memories of a group, the beginning of the cycle is devoted to the incrementation of the phase of the fundamental. At the input of the converter, there is therefore no data to convert during the start of the cycle, and this for a few microseconds. Then, as the data is read in the other memories of the group, the converter successively receives the data read and delivers as output a series of analog samples of well defined constant duration. These samples are then distributed by the demultiplexer to the integrators which then deliver a signal whose level (voltage or current) varies proportionally (in magnitude and in sign) to the amplitude of the samples applied.
  • the essential advantage of this structure of the converter lies in the fact that the successive samples delivered by the converter all come from the same group, and that between each series of samples there passes a sufficient time interval to extinguish all the possible instabilities in the circuits, due in particular to defects in the linearity of the conversion, significant rise times, etc. This results in better immunity of the synthesizer to the intermodulation of signals between groups, this thanks to the structure of the virtual keyboard, and to the course of the cycle of readings of the data which it contains.
  • FIG. 5 describes another exemplary embodiment in which the division into groups of the memory of the virtual keyboard is no longer predetermined. Indeed, in the previous embodiment, each group has a fixed number of memory blocks, which limits the number of elementary sound components associated with each generator. According to this new variant, the size of the groups is no longer determined in advance, but results from the sequence. As all the groups are, in practice, never all used at the same time, for the same memory capacity of the virtual keyboard, a greater number of sound components can be created in the groups used.
  • Each group of blocks then contains a main block and secondary blocks, each main block containing, at least, a block identification word, a word relating to a generator number, a word relating to the common submultiple of the phase. instantaneous of several periodic signals, a word containing an address pointer to another main block and a word containing an address pointer to another main or secondary block, and each secondary block containing, at least, an identification word block, a word relating to the amplitude of a periodic signal, a word relating to the harmonic or octave rank of said signal and a word containing an address pointer to another secondary or main block.
  • the pointers are used by the sequential chaining means so that each block read contains a pointer to a next block to be read. Only the blocks containing useful information are thus addressed and read and these blocks can be located at any position in the memories.
  • the chain produced is in fact a double chain: a chain of main blocks and a chain of secondary blocks.
  • the virtual keyboard 1 is also coupled to a microcomputer bus 2 which can read or write digital data there. Multiplexing means not shown allow access to the memories of the virtual keyboard by the bus or by the synthesizer.
  • the virtual keyboard is divided into 256 memory blocks, for example. Each block can be addressed separately and the address of a block is defined by an 8-bit set.
  • An address register 3 therefore contains, for each operation, the address of a block, and the blocks are read one by one, successively.
  • Each block is divided into several words which are addressed in parallel: these words are designated by the references 101, 102, 103, 104, 105, 106 and 107 for the two types of blocks (main and secondary).
  • the length of each word can be arbitrary; it only depends on the number of values that the quantity considered can take.
  • the main blocks contain the generator number and instantaneous phase information, at least, as well as an identification bit of the main type (1 for example).
  • Secondary blocks contain at least octave or harmonic number, waveform type, amplitude and output channel number information, as well as a secondary type identification bit (bit 0 for example).
  • Each main block relates to a generator while each secondary block relates to a sound component of the output signal.
  • Each main block further comprises two words which respectively contain a primary address pointer and a secondary address pointer.
  • Each primary pointer designates the address of another main block, either directly (absolute addressing) or indirectly (relative addressing). To simplify the presentation, we will assume that each pointer contains an absolute address.
  • Each secondary pointer designates the address of another secondary or main block
  • each secondary block includes a word containing a secondary address pointer, designating the address of another secondary or main block.
  • the secondary pointers of the clock 110 periodically generates pulses which are applied to register 3.
  • a pulse pulse; the address (the selected pointer) is recorded in register 3 and this then begins addressing the block located by this address.
  • the virtual keyboard therefore delivers either a first series of this data, a second series of data, and respectively leads to a first series of operations; or a second series of operations.
  • the synthesizer circuits which are connected to the virtual keyboard can therefore receive two types of information, only one of which can be taken into account.
  • the block identification bits before the same location in the two boce then serve as a barrier to distinguish the information of a main block from that of a secondary block, and other psrt; to validate or inhibit certain synthesizer operations.
  • the generator number 1 (word 103) is applied by connection 124 to a transition detector 5 which receives all the signals from the generators 6.
  • the instantaneous sub-multiple ⁇ (words 104 for the most significant and 105 for the least significant) is applied to the increment and memory circuit 9 by the bi-directional connections 125 and 126.
  • the state of the selected generator is compared with the least significant bit ⁇ o of the phase applied to detector 5, to detect a change of state of the generator.
  • the block type identification bit (word 101) is also applied to detector 5 (connection 122) in order to authorize detection only if it is a main block.
  • Connection 127 transmits a command for selection of secondary status to selector 4.
  • phase ⁇ memorized by the in circuit. incrementation 9, is applied 22 an address calculation circuit lll.
  • the octave number word 102) is also information comes out of combined form send a memory of shape of end 112 from which a sample is extracted which is applied to a multiplier circuit 12.
  • This circuit receives at the same time the value of amplituge A (word 104) by connection 125 the result of the product is applied a digital to analog converter is.
  • the secondary block identification bit (word 101) is applied to the converter to validate the conversion only in this case. There is therefore no conversion when the main block is read.
  • a demitiplexer 109 controlled by the output channel number (word 105), receives the analog output signal from the converter 13 and directs this signal to 1 one of the integrators. 114, 115 ; etc., 119
  • All these operations are carried out in a duration less than the period of the clock 110.
  • the register 3 addresses a new block which can be either another secondary block or another main block.
  • FIG. 6 represents a flowchart explaining the operation of the reading and conversion control means, according to the sequence of the synthesizer of FIG. 5.
  • the generator number I (word 103 in Figure 1) is applied to the transition detector 5 to test the state of the corresponding generator (test 130 in Figure 2).
  • the detector emits a primary pointer selection signal (block 131 in figure 6) and the generator tests continue (loop 130 - 131 - 130 - 131, etc.) until the detection of a change of state of a generator.
  • the generator has changed state.
  • the instantaneous phase value ( ⁇ ) is first incremented (132) then the secondary pointer is selected (133) making it possible to address a series of secondary blocks.
  • Figure 7 shows the detail of the transition detector circuit 3
  • It essentially comprises a multiplexer circuit 51 which receives the generator signals on the one hand .. and the number 1 (word 103), on the other hand as a selection command
  • the generators 6 re-read square signals if this output 55 of the multiplexer is a binary signal.
  • the identification bit (word 101) is also applied to a validation input 56 so that only a main block can select a generator
  • circuit 52! ? exelusif 52 receive the output signal from the multiplier as well as the lowest bis bet ⁇ of the instantaneous phase.
  • circuit 52 The output of circuit 52 is connected to a non-inverting input of an AND circuit 53 and to an inverting input of an AND circuit 54.
  • the block identification signal (101) is also applied to non-inverting inputs of the AND circuits 53 and 54.
  • the output of ET 53 controls the phase increment circuit 9. Indeed, the output of this circuit can only be active (at state 1 in this case) if the selected block is a main block (signal 101 to 1) and if the designated generator has changed state (output at 1 of exclusive OR 52).
  • ET 54 controls the selection of primary or secondary pointers (selector 4).
  • the output of ET 54 is at state 0, commanding the selection of a secondary block.
  • the selection of a primary pointer is only obtained if the block read is of the main type and if the corresponding generator has not changed state.
  • This second variant of the invention makes it possible to improve the speed of calculation of the sound elements of the synthesizer without limiting the number of sound elements for each generator.
  • the aaresse one partIe of the aeresse of the biees of memories can be used for the means of conversion in the same title gue the contents of these blocks that is possible for example for the number 1 of generator and / if the rank of this variant decreases the flexibility of use of the memories, but reduces the number of memories required. Likewise, a different arrangement of the data in these memories is possible.

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EP79400886A 1978-11-21 1979-11-20 Polyphone Syntheseschaltung für periodische Signale unter Anwendung digitaler Techniken Expired EP0011576B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT79400886T ATE3918T1 (de) 1978-11-21 1979-11-20 Polyphone syntheseschaltung fuer periodische signale unter anwendung digitaler techniken.

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR7832727 1978-11-21
FR7832727A FR2442485A1 (fr) 1978-11-21 1978-11-21 Synthetiseur numerique polyphonique de signaux periodiques
FR7907339 1979-03-23
FR7907339A FR2452145A2 (fr) 1979-03-23 1979-03-23 Synthetiseur polyphonique de signaux periodiques

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EP0011576A1 true EP0011576A1 (de) 1980-05-28
EP0011576B1 EP0011576B1 (de) 1983-06-22

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US (1) US4279186A (de)
EP (1) EP0011576B1 (de)
DD (1) DD147288A5 (de)
DE (1) DE2965764D1 (de)
ES (1) ES486146A1 (de)
NO (1) NO793756L (de)

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JPS5632188A (en) * 1979-08-24 1981-04-01 Sony Corp Waveform synthesizer
DE3023580C2 (de) * 1980-06-24 1982-04-01 Matth. Hohner Ag, 7218 Trossingen Verfahren zur Phasensynchronisation digital synthetisierter Töne eines Musikinstruments und Schaltungsanordnung zur Durchführung des Verfahrens
EP0102169B1 (de) * 1982-07-19 1987-09-16 Matsushita Electric Industrial Co., Ltd. Gerät zum Lesen von Wellen
DE3331176C1 (de) * 1983-08-30 1990-01-25 WERSI-electronic GmbH & Co KG, 5401 Halsenbach Vorrichtung zur digitalen Erzeugung der Klänge von Instrumenten, insbesondere Schlagzeugklängen
JP2819948B2 (ja) * 1992-07-16 1998-11-05 ヤマハ株式会社 楽音信号記録再生装置
US5444818A (en) * 1992-12-03 1995-08-22 International Business Machines Corporation System and method for dynamically configuring synthesizers

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FR2153149A1 (de) * 1969-10-30 1973-05-04 North American Rockwell
US4023454A (en) * 1975-08-28 1977-05-17 Kabushiki Kaisha Dawai Gakki Seisakusho Tone source apparatus for an electronic musical instrument
FR2344907A1 (fr) * 1976-03-16 1977-10-14 Deforeit Christian Instrument de musique electronique polyphonique
FR2396375A1 (fr) * 1977-07-01 1979-01-26 Deforeit Christian Synthetiseur polyphonique de signaux periodiques et instrument de musique electronique comportant un tel synthetiseur

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US3955459A (en) * 1973-06-12 1976-05-11 Nippon Gakki Seizo Kabushiki Kaisha Electronic musical instrument
JPS5651632B2 (de) * 1974-09-17 1981-12-07
US4177706A (en) * 1976-09-08 1979-12-11 Greenberger Alan J Digital real time music synthesizer
US4193332A (en) * 1978-09-18 1980-03-18 Richardson Charles B Music synthesizing circuit

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FR2153149A1 (de) * 1969-10-30 1973-05-04 North American Rockwell
US4023454A (en) * 1975-08-28 1977-05-17 Kabushiki Kaisha Dawai Gakki Seisakusho Tone source apparatus for an electronic musical instrument
FR2344907A1 (fr) * 1976-03-16 1977-10-14 Deforeit Christian Instrument de musique electronique polyphonique
FR2396375A1 (fr) * 1977-07-01 1979-01-26 Deforeit Christian Synthetiseur polyphonique de signaux periodiques et instrument de musique electronique comportant un tel synthetiseur

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ES486146A1 (es) 1980-06-16
NO793756L (no) 1980-05-22
US4279186A (en) 1981-07-21
DE2965764D1 (en) 1983-07-28
DD147288A5 (de) 1981-03-25
EP0011576B1 (de) 1983-06-22

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