EP0000472B1 - High-density integrated semiconductor device comprising a diode-resistor structure - Google Patents

High-density integrated semiconductor device comprising a diode-resistor structure Download PDF

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Publication number
EP0000472B1
EP0000472B1 EP78100195A EP78100195A EP0000472B1 EP 0000472 B1 EP0000472 B1 EP 0000472B1 EP 78100195 A EP78100195 A EP 78100195A EP 78100195 A EP78100195 A EP 78100195A EP 0000472 B1 EP0000472 B1 EP 0000472B1
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EP
European Patent Office
Prior art keywords
resistor
area
pinch
diode
doping
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Expired
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EP78100195A
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German (de)
French (fr)
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EP0000472A1 (en
Inventor
Wilfried Klein
Erich Dipl.-Ing. Klink
Volker Dipl.-Phys. Rudolph
Friedrich Dipl.-Ing. Wernicke
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/0788—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type comprising combinations of diodes or capacitors or resistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

Definitions

  • the invention relates to a highly integrated semiconductor arrangement containing a diode / resistor configuration according to the preamble of claim 1, which can preferably be used as a separating diode interacting with the selection lines of an integrated memory arrangement with a high-impedance leakage resistance.
  • a constant endeavor in the development of integrated semiconductor circuit concepts is to design the individual or more circuit elements to be as space-saving as possible in order to be able to accommodate as many circuit elements or functions as possible on a semiconductor chip.
  • Such increases in the degree of integration have a directly favorable effect on the costs, the reliability, etc. of the products produced from them.
  • US Pat. No. 3,631,311 deals with an integrated semiconductor circuit arrangement which provides a transistor with a base leakage resistance integrated directly therewith.
  • the resistance area extends on one side into the surrounding insulation area, whereby an external resistance connection can also be saved.
  • the leakage resistance integrated together with the transistor base is known as a pinch or. Dumbbell resistor designed.
  • Such a pinch resistor is a double-diffused resistor, in which the line channel of the actual resistance region is constricted in its cross section by introducing a further doping region of the opposite conductivity type. Relatively high-resistance values can thus be achieved without this being associated with an otherwise inevitably high semiconductor area requirement when the sheet resistance is used.
  • the invention solves the problem of specifying a space-saving integrated semiconductor arrangement for a diode / resistor configuration which, in particular, requires as few external connection contacts and interconnection conductors as possible and can be produced by means of conventional method steps.
  • the resistance should be able to be designed for high resistance values, as are required for leakage resistors and have the lowest possible parasitic capacitance.
  • the invention provides for the extremely extensive integration of a Schottky diode with a pinch resistor connected thereto, the pinch-off doping region of which also represents the cathode connection doping region of the Schottky diode.
  • the Schottky contact is formed simultaneously with the resistance connection by a common metal electrode overlapping the associated P / N junction.
  • the additional contact for the resistor can also be saved by extending the resistance area into the surrounding isolation doping area, via which the corresponding voltage supply then takes place when the resistor is used as a discharge resistor.
  • the pinch resistor has a P feasibled doped resistance area within a surrounding N-type semiconductor material in a surrounding area, that the pinch-doping region of the pinch resistor is arranged relatively between the two ends of the resistance area highly doped N conductive area, the penetration depth of which is less than that of the resistance area.
  • the diode / resistor configuration constructed according to the measures of the invention is distinguished by an extremely small need for active semiconductor area, since it manages with a minimum of external connections and interconnections while avoiding intermediate isolation.
  • the available high resistance value with only a small parasitic capacitive influence allows a versatile application, for. B. as a isolation diode / leakage resistance combination with low own power dissipation.
  • the diode D is a Schottky diode with the anode connection A and the cathode connection K.
  • the resistor R With the anode connection A, the resistor R is connected, to the other connection of which a reference voltage VR can be applied. If the resistor R is used as a bleeder resistor, VR can, for example, be the most negative voltage occurring in the circuit.
  • the symbol used for the resistor R in FIG. 1 is intended to indicate that this is a (known pinch resistor with a pinch-off region in the course of the resistor area).
  • FIG. 2A now shows a particularly advantageous exemplary embodiment for the highly integrated embodiment of the circuit shown in FIG. 1 as a semiconductor arrangement.
  • FIG. 2B additionally shows a cross-sectional illustration along the section line designated in FIG. A2.
  • the cross-sectional illustration in FIG. 2B is expanded in the sense of a perspective illustration.
  • the diode / resistor combination according to the invention can be produced by means of conventional methods which are conventional in the field of integrated semiconductor circuits, which is why there is no need to go into this in the present context.
  • buried doping regions in the form of the known subcollector regions can be provided in the substrate 1, but are not shown in the present case for the sake of clarity.
  • an epitaxial layer of the opposite conductivity type is usually applied to the substrate 1 using known epitaxy methods and is divided into individual, delimited surrounding areas 3 made of N-conducting semiconductor material by frame-shaped separation doping areas 2. These delimited surrounding areas 3 of the epitaxial layer serve in a known manner to accommodate the semiconductor components to be formed therein.
  • both the diode D and the resistor R integrated therewith are arranged in such a delimited surrounding area 3 made of N-conducting semiconductor material.
  • the resistor R consists of the elongated P conductively doped resistance region 4, the cross section of which is constricted in the manner customary for pinch resistors by introducing a constriction doping region 5 of the opposite conductivity type, in the present case made of N + conductive semiconductor material.
  • the constriction doping region has a smaller penetration depth than the resistance region 4.
  • the pinch-up doping region 5 extends beyond the width of the resistance region 4 (at 6), so that there it is in connection with the semiconductor material surrounding the resistance region 4 in the surrounding region 3 of the same conductivity type.
  • the conventional doping methods such as diffusion or ion implantation, can be used to produce the resistance region 4 and the pinch-up doping region 5.
  • the resistance area 4 is equipped with a metal electrode A on a vein, in the exemplary embodiment of FIG. 2 at the right end.
  • This metal electrode A forms an ohmic contact with the P-conducting resistance region 4. It is particularly advantageous in the context of the present invention to design the metal electrode A as an overlapping contact, so that it also extends beyond the resistance region 4 into the surrounding N conductive material of the surrounding region 3. As a result, in the present case, a rectifying Schottky contact is formed on the N-conducting semiconductor material of the surrounding area 3 by the metal electrode A in addition to an ohmic contact in the resistance area 4.
  • connection contact formed as a metal electrode for the external connection.
  • This metal electrode is designated K because the cathode of the Schottky diode D is accessible from the outside.
  • the metal electrode K can consist of the same metal as the metal contact A, because the degree of doping of the cutoff Nürdot ists Society 5 is higher than the semiconductor material in the surrounding area 3, so that the metal electrode K forms an ohmic contact.
  • the production of the metal contact A and the metal electrode K can be carried out by means of conventional methods, for. B. by means of aluminum vapor deposition, sputtering, etc., take place. In this context, it should also be noted that both the formation of the doping regions and the metallizations can be carried out together with the corresponding method steps for the further circuit elements to be produced on the same semiconductor chip.
  • the P conductive resistance area 4 can be made simultaneously with the base doping, the pinch-up doping area 5 with the emitter doping and the contacting with the other metallizations for the connections and conductor tracks on the chip.
  • the circuit D shown in FIG. 1 completes the diode D with its external connections A and K and the resistor R connected to the anode connection A.
  • the resistor R as a bleed resistor for the most negative potential occurring in the circuit, the otherwise required contact on the resistance region 4 can finally be saved according to a special embodiment of the invention in that the resistance region 4 with its other end, in the exemplary embodiment shown on the left to extends into the separation doping area 2 surrounding the surrounding area 3. Since the isolation doping regions 2 for the formation of blocked P / N junctions are generally at the lowest potential occurring in the circuit, the resistor R receives the corresponding voltage supply at its connection for the reference potential VR, without providing a special area-consuming additional contact to have to.
  • the diode / resistor combination shown in FIG. 1 can thus be implemented with an extraordinarily high integration density and only two external contacts, which, compared to a conventional design of such a circuit part, results in a considerable saving in area, which is based on a true-to-scale area comparison with the aid of FIG .3 should be illustrated.
  • FIG. 3 shows a conventional, integrated semiconductor arrangement for the circuit part shown in FIG. 1.
  • the same extension parts were used.
  • the same design guidelines, ie distance regulations, minimum area sizes etc. were used as in Fig. 2A.
  • the pinch resistor with its P-conducting resistance region 9 and the pinch-off doping region 10 and the two outer connections 11 and 12 is formed in a first insulated semiconductor region 8.
  • the Schottky diode is made in a second semiconductor region 13 from N conductive semiconductor material.
  • the metal electrode 14 forms the Schottky junction for the anode, while the further metal electrode 15 on the N + conductive doping region 16 forms an ohmic contact for the cathode of the Schottky diode.
  • a comparison of the area of the conventional embodiment according to FIG. 3 with the embodiment according to a preferred embodiment of the invention according to FIG. 2A results in an area saving of approximately 54% if the diode / resistor configuration according to FIG. 1 is integrated according to the invention.
  • FIG. 4 shows as an application example the use of the diode / resistor configuration according to the invention in the control area of a semiconductor memory.
  • FIG. 4 shows a section of a memory arrangement which is limited to a bit line pair BLO, BL1.
  • BLO bit line pair
  • BL bit line pair
  • all word and bit selection lines must be charged or brought to defined DC voltage potentials for the idle state after each access period by means of a clocked control logic.
  • a series of transistors are provided as current sinks and current sources, which are controlled by a schematically indicated circuit 17. Via the circuit 17, the base connections of the transistors 18, 19 and 20 can be selected in the absence of the reference potential VR, z. B. the smallest potential occurring in the circuit can be pulled down. The voltage drop across the isolating diode is neglected.
  • Each such group of transistors belonging to a bit line pair or to a word line can be decoupled from the corresponding transistors of another bit line pair or another word line by means of the diode / resistor configuration shown in the boxed area 21 according to FIG. 1.
  • all decoupling diodes D are biased in the reverse direction on the chip concerned, so that write-in or. Readout processes can be carried out.
  • a leakage resistance R is also parallel to the Anode connection of the decoupling diode D is provided. So that only the lowest possible current can flow through the bleeder resistor in the selection case, the bleeder resistor R should have the highest possible resistance value and the most parasitic capacitance. These properties go directly into the switching times that can be achieved and the power loss.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Static Random-Access Memory (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Description

Die Erfindung bezieht sich auf eine hochintegrierte Halbleiteranordnung enthaltend eine Dioden-/Widerstandskonfiguration gemäß dem Oberbegriff des Patentanspruchs 1, die vorzugsweise als mit den Auswahlleitungen einer integrierten Speicheranordnung zusammenwirkende Trenndiode mit einem hochohmigen Ableitwiderstand Anwendung finden kann.The invention relates to a highly integrated semiconductor arrangement containing a diode / resistor configuration according to the preamble of claim 1, which can preferably be used as a separating diode interacting with the selection lines of an integrated memory arrangement with a high-impedance leakage resistance.

Ein ständiges Bestreben bei der Entwicklung integrierter Halbleiterschaltungskonzepte besteht darin, die einzelnen oder mehreren Schaltungselemente möglichst flächensparend auszulegen, um so auf einem Halbleiterchip möglichst viele Schaltungselemente bzw.-funktionen unterbringen zu können. Derartige Erhöhungen des Integrationsgrades wirken sich unmittelbar günstig auf die Kosten, die Zuverlässigkeit etc. der daraus hergestellten Produkte aus.A constant endeavor in the development of integrated semiconductor circuit concepts is to design the individual or more circuit elements to be as space-saving as possible in order to be able to accommodate as many circuit elements or functions as possible on a semiconductor chip. Such increases in the degree of integration have a directly favorable effect on the costs, the reliability, etc. of the products produced from them.

In der US-PS 3 631 311 ist beispielsweise eine integrierte Halbleiterschaltungsanordnung behandelt, die einen Transistor mit einem unmittelbar damit integrierten Basisableitwiderstand vorsieht. Der Widerstandsbereich erstreckt sich dabei einseitig bis in den umgebenden Isolationsbereich, wodurch zusätzlich ein äußerer Widerstandsanschluß eingespart werden kann. In einer ähnlichen Konfiguration ist nach der Veröffentlichung im IBM Technical Disclosure Bulletin Vol. 11, N° 11, April 1969, Seite 1439 der zusammen mit der Transistorbasis integrierte Ableitwiderstand als sog. Pinch-bzw. Dumbbell-Widerstand ausgelegt. Bei einem solchen Pinch-Widerstand handelt es sich um einen doppeltdiffundierten Widerstand, bei dem der Leitungskanal des eigentlichen Widerstandsbereiches durch Einbringung eines weiteren Dotierungsbereichs vom entgegengesetzten Leitfähigkeitstyp in seinem Querschnitt eingeschnürt wird. Damit lassen sich relativ hochohmige Widerstandswerte erreichen, ohne daß damit ein ansonsten bei Ausnutzung des Bahnwiderstandes zwangsläufiger hoher Halbleiterflächenbedarf verbunden wäre.For example, US Pat. No. 3,631,311 deals with an integrated semiconductor circuit arrangement which provides a transistor with a base leakage resistance integrated directly therewith. The resistance area extends on one side into the surrounding insulation area, whereby an external resistance connection can also be saved. In a similar configuration, according to the publication in IBM Technical Disclosure Bulletin Vol. 11, N ° 11, April 1969, page 1439, the leakage resistance integrated together with the transistor base is known as a pinch or. Dumbbell resistor designed. Such a pinch resistor is a double-diffused resistor, in which the line channel of the actual resistance region is constricted in its cross section by introducing a further doping region of the opposite conductivity type. Relatively high-resistance values can thus be achieved without this being associated with an otherwise inevitably high semiconductor area requirement when the sheet resistance is used.

Schließlich ist in der DT-Auslegeschrift 1 808 342 sowie in der US-PS 4 005 469 eine relativ hochintegrierte Kombination eines Transistors mit einer zugehörigen Antisättigungsdiode angegeben. Dabei wird durch einen übergreifenden Metallkontakt gleichzeitig auf dem Halbleitermaterial des einen Leitfähigkeitstyps ein ohmscher sowie auf dem umgebenden Halbleitermaterial vom anderen Leitfähigkeitstyp ein gleichrichtender Schottky-Kontakt gebildet.Finally, a relatively highly integrated combination of a transistor with an associated anti-saturation diode is specified in DT-1,808,342 and in US Pat. No. 4,005,469. An overlapping metal contact simultaneously forms an ohmic Schottky contact on the semiconductor material of one conductivity type and a rectifying Schottky contact on the surrounding semiconductor material.

Die Erfindung, wie sie in den Ansprüchen gekennzeichnet ist, löst die Aufgabe, eine möglichst flächensparende integrierte Halbleiteranordnung für eine Dioden-/Widerstandskonfiguration anzugeben, die insbesondere mit möglichst wenig äußeren Anschlußkontakten und Zwischenverbindungsleiterzügen auskommt und mittels konventioneller Verfahrensschritte hersteilbar ist. Dabei soll der Widerstand für hohe Widerstandswerte auslegbar sein, wie sie für Ableitwiderstände benötigt werden und eine möglichst geringe parasitäre Kapazität aufweisen.The invention, as characterized in the claims, solves the problem of specifying a space-saving integrated semiconductor arrangement for a diode / resistor configuration which, in particular, requires as few external connection contacts and interconnection conductors as possible and can be produced by means of conventional method steps. The resistance should be able to be designed for high resistance values, as are required for leakage resistors and have the lowest possible parasitic capacitance.

Zusammengefaßt sieht die Erfindung die extrem weitgehende Integration einer Schottky-Diode mit einem damit verbunden Pinch-Widerstand vor, dessen Abschnürdotierungsbereich gleichzeitig das Kathodenanschlußdotierungsgebiet der Schottky-Diode darstellt. Der Schottky-Kontakt wird dabei gleichzeitig mit dem Widerstandsanschluß durch eine gemeinsame den zugehörigen P/N-Übergang überlappende Metallelektrode gebildet. Schließlich läßt sich auch der weitere Kontakt für den Widerstand dadurch einsparen, daß man den Widerstandsbereich bis in den umgebenden Trenndotierungsbereich hinein erstreckt, über den dann die entsprechende Spannungszufuhr beim Einsatz des Widerstandes als Ableitwiderstand erfolgt.In summary, the invention provides for the extremely extensive integration of a Schottky diode with a pinch resistor connected thereto, the pinch-off doping region of which also represents the cathode connection doping region of the Schottky diode. The Schottky contact is formed simultaneously with the resistance connection by a common metal electrode overlapping the associated P / N junction. Finally, the additional contact for the resistor can also be saved by extending the resistance area into the surrounding isolation doping area, via which the corresponding voltage supply then takes place when the resistor is used as a discharge resistor.

In diesem Zusammenhang ist festzustellen, daß des erste Teil des Anspruchs 1 (Oberbegriff) sowie die besondere Ausführungsart nach Anspruch 4 aus der Zeitschnift IMB Technical Disclosure Bulletin, Vol. 14, Juin 1971, N° 1, Seite 236, bekannt ist.In this context, it should be noted that the first part of claim 1 (generic term) and the special embodiment according to claim 4 are known from the Zeitschnift IMB Technical Disclosure Bulletin, Vol. 14, Juin 1971, N ° 1, page 236.

Ferner ist im Hinblick auf Anspruch 9 aus dieser Literaturstelle bekannt, daß der Pinch-Widerstand einen Pleitend dotierten widerstandsbereich innerhalb eines umgebenden N-Leitenden Halbleitermaterials in einem Umgebungsbereich aufweist, daß der Abschnürdotierungsbereich des Pinch-Widerstandes ein zwischen den beiden Enden des Widerstands bereichs angeordneter relativ hochdotierter N Leitender Bereich ist, dessen Eindringtiefe geringer als die des Widerstandsbereichs ist.Furthermore, with regard to claim 9, it is known from this literature reference that the pinch resistor has a Pleitend doped resistance area within a surrounding N-type semiconductor material in a surrounding area, that the pinch-doping region of the pinch resistor is arranged relatively between the two ends of the resistance area highly doped N conductive area, the penetration depth of which is less than that of the resistance area.

Die nach den Maßnahmen der Erfindung aufgebaute Dioden-/Widerstandskonfiguration zeichnet sich durch einen außerordentlich geringen Bedarf an aktiver Halbleiterfläche aus, da sie unter Vermeidung einer Zwischen-isolation mit einem Minimum an äußeren Anschlüssen und Zwischenverbindungen auskommt. Der zur Verfügung stehende hohe Widerstandswert mit nur geringem parasitären kapazitiven Einfluß erlaubt eine vielseitige Anwendbarkeit, z. B. als Trenndioden-/Ableitwiderstandskombination mit geringem eigenen Verlustleistungsverbrauch.The diode / resistor configuration constructed according to the measures of the invention is distinguished by an extremely small need for active semiconductor area, since it manages with a minimum of external connections and interconnections while avoiding intermediate isolation. The available high resistance value with only a small parasitic capacitive influence allows a versatile application, for. B. as a isolation diode / leakage resistance combination with low own power dissipation.

Die Erfindung wird im folgenden anhand von Ausführungs- und Anwendungsbeispielen die einen Wog zur Ausführung der Erfindung angeben, unter Zuhilfenahme der Zeichnungen näher erläutert.The invention is explained in more detail below with reference to exemplary embodiments and application examples which indicate a wave for carrying out the invention with the aid of the drawings.

Es zeigen :

  • Fig. 1 das elektrische Ersatzschaltbild der Dioden-/Widerstandskombination ;
  • Fig. 2A u. 2B ein bevorzugtes Ausführungsbeispiel der Erfindung in einer Draufsicht sowie einem perspektivischen Querschnitt durch die zugehörige Halbleiterstruktur ;
  • Fig. 3 eine Draufsicht auf eine konventionell integrierte Dioden-/Widerstandskombination, mit der die Erfindung vergleichbar ist und
  • Fig. 4 das elektrische Schaltbild einer Speicheransteuerung zur Erläuterung der vorteilhaften Anwendung der Erfindung.
Show it :
  • Figure 1 shows the electrical equivalent circuit of the diode / resistor combination.
  • 2A and. 2B shows a preferred exemplary embodiment of the invention in a plan view and a perspective cross section through the associated semiconductor structure;
  • Fig. 3 is a plan view of a conventionally integrated diode / resistor combination with which the invention is comparable and
  • Fig. 4 shows the electrical diagram of a spoke ran control to explain the advantageous application of the invention.

Fig. 1 zeigt das elektrische Ersatzschaltbild der Dioden-/Widerstandskonfiguration, die nach den Maßnahmen der Erfindung besonders vorteilhaft im Sinne einer hohen Integrationsdichte als Halbleiteranordnung ausgebildet werden kann. Bei der Diode D handelt es sich um eine Schottky-Diode mit dem AnondenanschlußA und dem Kathodenanschluß K. Mit dem Anodenanschluß A ist der Widerstand R verbunden, an dessen anderem Anschluß eine Referenzspannung VR anlegbar ist. Bei einer Benutzung des Widerstandes R als Ableitwiderstand, kann VR beispielsweise die negativste in der Schaltung vorkommende Spannung sein. Das für den Widerstand R in Fig. 1 benutzte Symbol soll darauf hinweisen, daß es sich dabei um einen (an sich bekannten Pinch-Widerstand mit einem Abschnürdotierungsbereich im Verlauf des Widerstandsbereiches handelt.1 shows the electrical equivalent circuit diagram of the diode / resistor configuration, which according to the measures of the invention can be embodied particularly advantageously in the sense of a high integration density as a semiconductor arrangement. The diode D is a Schottky diode with the anode connection A and the cathode connection K. With the anode connection A, the resistor R is connected, to the other connection of which a reference voltage VR can be applied. If the resistor R is used as a bleeder resistor, VR can, for example, be the most negative voltage occurring in the circuit. The symbol used for the resistor R in FIG. 1 is intended to indicate that this is a (known pinch resistor with a pinch-off region in the course of the resistor area).

Fig.2A zeigt nun eine besonders vorteilhaftes Ausführungsbeispiel für die hochintegrierte Ausführung der in Fig. 1 gezeigten Schaltung als Halbleiteranordnung. Fig.2B zeigt ergänzend dazu Querschnittsdarstellung entlang der in Fig. A2 bezeichneten Schnittlinie. Zur weiteren Verdeutlichung des Aufbaus der Halbleiteranordnung ist die Querschnittsdarstellung in Fig. 2B im Sinne einer perspektivischen Darstellung erweitert. Die Herstellung der erfindungsgemäßen Dioden-/Widerstandskombination kann mittels konventioneller auf dem Gebiet der integrierten Halbleiterschaltungen üblicher Verfahren erfolgen, weshalb darauf im vorliegenden Zusammenhang nicht näher eingegangen zu werden braucht. So kann beispielsweise von einem P leitenden Halbleitersubstrat 1, z. B. aus einkristallinem Silicium, ausgegengen werden. In dem Substrat 1 können ggf. vergrabene Dotierungsbereiche in Form der bekannten Subkollektorregionen vorgesehen werden, die jedoch im vorliegenden Fall der besseren Übersichtlichkeit wegen nicht dargestellt sind. Auf dem Substrat 1 wird bei bipolaren Halbleiteranordnungen anschließen gewöhnlich mittels bekannter Epitaxieverfahren eine Epitaxieschicht vom entgegengesetzten Leitfähigkeitstyp aufgebracht, die durch rahmenförmige Trenndotierungsbereiche 2 in einzelne, abgegrenzte Umgebungsbereiche 3 aus N leitendem Halbleitermaterial aufgeteilt wird. Diese abgegrenzten Umgebungsbereiche 3 der Epitaxieschicht dienen in bekannter Weise zur Aufnahme der darin auszubildenden Halbleiterbauelemente.2A now shows a particularly advantageous exemplary embodiment for the highly integrated embodiment of the circuit shown in FIG. 1 as a semiconductor arrangement. FIG. 2B additionally shows a cross-sectional illustration along the section line designated in FIG. A2. To further clarify the structure of the semiconductor arrangement, the cross-sectional illustration in FIG. 2B is expanded in the sense of a perspective illustration. The diode / resistor combination according to the invention can be produced by means of conventional methods which are conventional in the field of integrated semiconductor circuits, which is why there is no need to go into this in the present context. For example, a P-conducting semiconductor substrate 1, e.g. B. from single-crystal silicon. If necessary, buried doping regions in the form of the known subcollector regions can be provided in the substrate 1, but are not shown in the present case for the sake of clarity. In the case of bipolar semiconductor arrangements, an epitaxial layer of the opposite conductivity type is usually applied to the substrate 1 using known epitaxy methods and is divided into individual, delimited surrounding areas 3 made of N-conducting semiconductor material by frame-shaped separation doping areas 2. These delimited surrounding areas 3 of the epitaxial layer serve in a known manner to accommodate the semiconductor components to be formed therein.

Im vorliegenden Fall sind in einem solchen abgerenzten Umgebungsbereich 3 aus N leitendem Halbleitermaterial sowohl die Diode D als auch damit integriert der Widerstand R angeordnet. Der Widerstand R besteht aus dem langgestreckten P leitenddotierten Widerstandsbereich 4, dessen Querschnitt in der für Pinch-Widerstände üblichen Art durch Einbringung eines Abschnürdotierungsbereiches5 vom entgegengesetzten Leitfähigkeitstyp, im vorliegenden Fall aus N+ leitendem Halbleitermaterial, eingeschnürt ist. Der Abschnürdotierungsbereich weist dabei eine geringere Eindringtiefe als der Widerstandsbereich 4 auf. In der Querrichtung erstreckt sich der Abschnürdotierungsbereich 5 über die Breite des Widerstandsbereichs 4 hinaus (bei 6), so daß er dort in Verbindung mit dem den Widerstandsbereich 4 umgebenden Halbleitermaterial im Umgebangsbereich 3 vom gleichen Leitfähigkeitstyp steht. Zur Herstellung des Widerstandsbereichs 4 und des Abschnürdotierungsbereichs 5 können die konventionellen Dotierungsverfahren, wie Diffusion oder lonenimplantation, Anwendung finden.In the present case, both the diode D and the resistor R integrated therewith are arranged in such a delimited surrounding area 3 made of N-conducting semiconductor material. The resistor R consists of the elongated P conductively doped resistance region 4, the cross section of which is constricted in the manner customary for pinch resistors by introducing a constriction doping region 5 of the opposite conductivity type, in the present case made of N + conductive semiconductor material. The constriction doping region has a smaller penetration depth than the resistance region 4. In the transverse direction, the pinch-up doping region 5 extends beyond the width of the resistance region 4 (at 6), so that there it is in connection with the semiconductor material surrounding the resistance region 4 in the surrounding region 3 of the same conductivity type. The conventional doping methods, such as diffusion or ion implantation, can be used to produce the resistance region 4 and the pinch-up doping region 5.

Zur Herstellung eines äußeren Anschlusses ist der Widerstandsbereich 4 an einem Einde, im Ausführungsbeispiel der Fig. 2 am rechten Ende, mit einer Metallelektrode A ausgestattet. Diese MetallelektrodeA bildet mit dem P leitenden Widerstandsbereich 4 einen ohmschen Kontakt. Besonders vorteilhaft ist es im Rahmen der vorliegenden Erfindung, die Metallelektrode A als übergreifenden Kontakt auszubilden, so daß sie sich auch über den Widerstandsbereich 4 hinaus in das umgebende N leitende material des Umgebungsbereichs 3 erstreckt. Dadurch ist im vorliegenden Fall durch die Metallelektrode A neben einem ohmschen Kontakt des Widerstandsbereichs4 ein gleichrichtender Schottky-Kontakt auf dem N leitenden Halbleitermaterial des Umgebungsbereichs 3 gebildet. Die für die Erzielung von gleichrichtenden Schottky-Kontakten einzuhaltenden Bedingungen bezüglich der Metall-Halbleiterpaarungen sind in der Halbleitertechnik gut bekannt. Es ist beispielsweise bekannt, daß Metallkontakte aus Aluminium, Platin usw. auf schwach dotiertem N leitendem Silicium einen Schottky-Kontakt bilden. Der somit neben dem ohmschen Kontakt auf dem Widerstandsbereich 4 durch die Ausbildung des Metallkontaktes A als übergreifender Kontakt hergestellte Schottky-Übergang (bei 7) bildet somit gleichzeitig die Anode der in Fig. im Schaltbild dargestellten Schottky-Diode D. Statt üblicherweise zwei Kontakten wird somit nur ein einziger Kontakt benötigt, was eine entsprechende Einsparung an aktiver Halbleiterfläche mit sich bringt.To establish an external connection, the resistance area 4 is equipped with a metal electrode A on a vein, in the exemplary embodiment of FIG. 2 at the right end. This metal electrode A forms an ohmic contact with the P-conducting resistance region 4. It is particularly advantageous in the context of the present invention to design the metal electrode A as an overlapping contact, so that it also extends beyond the resistance region 4 into the surrounding N conductive material of the surrounding region 3. As a result, in the present case, a rectifying Schottky contact is formed on the N-conducting semiconductor material of the surrounding area 3 by the metal electrode A in addition to an ohmic contact in the resistance area 4. The conditions to be met for the achievement of rectifying Schottky contacts with respect to the metal-semiconductor pairings are well known in semiconductor technology. For example, it is known that metal contacts made of aluminum, platinum, etc. form a Schottky contact on weakly doped N-conducting silicon. The Schottky junction (at 7) thus produced in addition to the ohmic contact on the resistance region 4 by forming the metal contact A as a comprehensive contact thus simultaneously forms the anode of the Schottky diode D shown in the circuit diagram only a single contact is required, which results in a corresponding saving in active semiconductor area.

Auf dem Abschnürdotierungsbereich 5 ist ebenfalls eine als Metallelektrode aus gebildete Anschlußkontaktierung für den äußeren Anschluß vorgesehen. Diese Metallelektrode ist mit K bezeichnet, weil über sie die Kathode der Schottky-Diode D nach außen zugänglich ist. Dabei wird nun ausgenutzt, daß der Abschnürdotierungsbereich 5 neben dieser Funktion im Rahmen des Pinch-Widerstandsaufbaus infolge seiner Erstreckung in das N leitende Halbleitermaterial des den Widerstandsbereich 4 umgebenden Umgebungsbereichs 3 gleichzeitig das Kathodenanschlußdotierungsgebiet für die aus dem Metallkontakt A und das N leitende Halbleitermaterial des Umgebungsbereichs 3 gebildete Schottky-Diode darstellt. Die Metallelektrode K kann aus demselben Metall wie der Metallkontakt A bestehen, weil der Dotierungsgrad des Abschnürdotierungsbereichs 5 höher ist als des Halbleitermaterials im Umgebungsbereich 3, so daß die Metallelektrode K einen ohmschen Kontakt bildet. Auch die Herstellung des Metallkontaktes A und der Metallelektrode K kann mittels konventioneller Verfahren, z. B. mittels einer Aluminiumbedampfung, Kathodenzerstäubung usw., erfolgen. In diesem Zusammenhang ist ferner anzumerken, daß sowohl die Ausbildung der Dotierungsbereiche wie auch der Metallisierungen zusammen mit den entsprechenden Verfahrensschritten für die weiteren auf demselben Halbleiterchip herzustellenden Schaltungselemente durchgeführt werden können, wobei z. B. der P leitende Widerstandsbereich 4 gleichzeitig mit der Basisdotierung, der Abschnürdotierungsbereich 5 mit der Emitterdotierung und die Kontaktierung mit den übrigen Metallisierungen für die Anschlüsse und Leiterzüge auf dem Chip vorgenommen werden kann.On the constricting doping region 5 there is also provided a connection contact formed as a metal electrode for the external connection. This metal electrode is designated K because the cathode of the Schottky diode D is accessible from the outside. In this case, use is now made of the fact that the pinch-off doping region 5, in addition to this function in the context of the pinch resistor structure, due to its extension into the N-conducting semiconductor material of the surrounding region 3 surrounding the resistance region 4, simultaneously the cathode connection doping region for the semiconductor region A composed of the metal contact A and the N-conducting semiconductor material Schottky diode formed. The metal electrode K can consist of the same metal as the metal contact A, because the degree of doping of the cutoff Nürdotierungsbereich 5 is higher than the semiconductor material in the surrounding area 3, so that the metal electrode K forms an ohmic contact. The production of the metal contact A and the metal electrode K can be carried out by means of conventional methods, for. B. by means of aluminum vapor deposition, sputtering, etc., take place. In this context, it should also be noted that both the formation of the doping regions and the metallizations can be carried out together with the corresponding method steps for the further circuit elements to be produced on the same semiconductor chip. B. the P conductive resistance area 4 can be made simultaneously with the base doping, the pinch-up doping area 5 with the emitter doping and the contacting with the other metallizations for the connections and conductor tracks on the chip.

Mit dem bisher beschriebenen Aufbau der Halbleiteranordnung sind somit von der in Fig. 1 dargestellten Schaltung die Diode D mit ihren äußeren Anschlüssen A und K sowie der mit dem Anodenanschluß A verbundene Widerstand R fertiggestellt. Bei einem Einsatz des Widerstandes R als Ableitwiderstand zum negativsten in der Schaltung vorkommenden Potential kann schließlich nach einer besonderen Ausführungsart der Erfindung der ansonsten erforderliche Kontakt auf dem Widerstandsbereich 4 dadurch eingespart werden, daß man den Widerstandsbereich 4 mit seinem anderen, im gezeigten Ausführungsbeispiel linken Ende bis in den den Umgebungsbereich 3 umgebenden Trenndotierungsbereich 2 hinein erstreckt. Da die Trenndotierungsbereiche 2 zur Bildung gesperrter P/N- Übergänge in der Regel auf dem niedrigsten in der Schaltung vorkommenden Potential liegen, erhält der Widerstand R auf diese Weise an seinem Anschluß für das Referenzpotential VR die entsprechende Spannungszuführung, ohne einen besonderen flächenaufwendigen zusätzlichen Kontakt vorsehen zu müssen. Dabei kann man sich zunutze machen, daß die Trenndotierungsbereiche 2 infolge ihrer untereinander bestehenden Verbindungen nur einen oder jedenfalls nur wenige Anschlüsse auf dem gesamten Chip erfordern.With the construction of the semiconductor arrangement described so far, the circuit D shown in FIG. 1 completes the diode D with its external connections A and K and the resistor R connected to the anode connection A. When using the resistor R as a bleed resistor for the most negative potential occurring in the circuit, the otherwise required contact on the resistance region 4 can finally be saved according to a special embodiment of the invention in that the resistance region 4 with its other end, in the exemplary embodiment shown on the left to extends into the separation doping area 2 surrounding the surrounding area 3. Since the isolation doping regions 2 for the formation of blocked P / N junctions are generally at the lowest potential occurring in the circuit, the resistor R receives the corresponding voltage supply at its connection for the reference potential VR, without providing a special area-consuming additional contact to have to. One can take advantage of the fact that the isolation doping regions 2 require only one or at least only a few connections on the entire chip due to their interconnections.

Insgesamt ist somit die in Fig. 1 gezeigte Dioden-/Widerstandskombination mit einer außerordentlich hohen Integrationsdichte und lediglich zwei externen Kontakten realisierbar, was Im Vergleich zu einer üblichen Auslegung eines derartigen Schaltungsteils in einer erheblichen Flächeneinsparung resultiert, was anhand eines maßstabsgetreuen Flächenvergleichs unter Zuhilfenahme der Fig.3 veranschaulicht werden soll.Overall, the diode / resistor combination shown in FIG. 1 can thus be implemented with an extraordinarily high integration density and only two external contacts, which, compared to a conventional design of such a circuit part, results in a considerable saving in area, which is based on a true-to-scale area comparison with the aid of FIG .3 should be illustrated.

Fig.3 zeigt eine konventionelle, integrierte Halbleiteranordnung für den in Fig. 1 gezeigten Schaltungsteil. Dabei wurden dieselben Ausletungsteil. Dabei wurden dieselben Auslegungsrichtlinien, d. h. Abstandsvorschriften, minimale Bereichsgrößen usw. wie in Fig.2A zugrunde gelegt. In Fig. 3 ist in einem ersten isolierten Halbleiterbereich 8 der Pinch-Widerstand mit seinem P leitenden Widerstandsbereich 9 und dem Abschnürdotierungsbereich 10 sowie den beiden äußeren Anschlüssen 11 und 12 ausgebildet. Isoliert davon ist in einem zweiten Halbleiterbereich 13 aus N leitendem Halbleitermaterial die Schottky-Diode hergestellt. Die Metallelektrode 14 bildet dabei den Schottky- Übergang für die Anode, während die weitere Metallelektrode 15 auf dem N+ leitenden Dotierungsbereich 16 einen ohmschen Kontakt für die Kathode der Schottky-Diode bildet. Ein Flächenvergleich der konventionellen Ausführung nach Fig. 3 mit der Ausführung nach einem bevorzugten Ausführungsbeispiel der Erfindung entsprechend Fig. 2A ergibt eine Flächeneinsparung von etwa 54%, wenn man die Dioden-/Widerstandskonfiguration nach Fig. 1 gemäß der Erfindung integriert.FIG. 3 shows a conventional, integrated semiconductor arrangement for the circuit part shown in FIG. 1. The same extension parts were used. The same design guidelines, ie distance regulations, minimum area sizes etc. were used as in Fig. 2A. In FIG. 3, the pinch resistor with its P-conducting resistance region 9 and the pinch-off doping region 10 and the two outer connections 11 and 12 is formed in a first insulated semiconductor region 8. In isolation from this, the Schottky diode is made in a second semiconductor region 13 from N conductive semiconductor material. The metal electrode 14 forms the Schottky junction for the anode, while the further metal electrode 15 on the N + conductive doping region 16 forms an ohmic contact for the cathode of the Schottky diode. A comparison of the area of the conventional embodiment according to FIG. 3 with the embodiment according to a preferred embodiment of the invention according to FIG. 2A results in an area saving of approximately 54% if the diode / resistor configuration according to FIG. 1 is integrated according to the invention.

Mit einer derartig hinsichtlich des Flächenbedarfs attraktiven Integration steht dem mit der Auslegung von integrierten Schaltungen befaßten Fachmann eine Schaltungsanordnung zur Verfügung, die er mit Vorteil in Verbindung mit den verschiedensten Schaltungen einsetzen kann. In Fig. 4 ist als ein Anwendungsbeispiel der Einsatz der erfindungsgemäßen Dioden-/Widerstandskonfiguration im Ansteuerungsbereich eines Halbleiterspeichers dargestellt. Fig. 4 stellt einen Ausschnitt aus einer Speicheranordnung dar, die auf ein Bitleitungspaar BLO, BL1 beschränkt ist. Soweit es darauf im vorliegenden Fall nicht ankommt, sind die entsprechenden Schaltungsteile lediglich schematisch angedeutet, z. B. die Speicherzellen, Ausgangsverstärker usw. Um bei derartigen Halbleiterspeichern zu kurzen Zykluszeiten bei niedriger Verlustleistungsaufnahme zu kommen, müssen alle Wort-und Bit-Auswahlleitungen nach jeder Zugriffsperiode durch eine getaktete Kontrollogik auf definierte Gleichspannungspotentiale für den Ruhezustand aufgeladen bzw. gebracht werden. Zu diesem Zweck sind eine Reihe von Transistoren als Stromsenken und Stromquellen vorgesehen, die von einem schematisch angedeuteten Schaltkreis 17 gesteuert werden. Über den Schaltkreis 17 können die Basisanschlüsse der Transistoren 18, 19 und 20 bei nicht vorliegender Selektion auf das Referenzpotential VR, z. B. das kleinste in der Schaltung vorkommende Potential, heruntergezogen werden. Der Spannungsabfall über der Trenndiode sei dabei vernächlässigt. Jede derartige Gruppe von zu einem Bitleitungspaar oder zu einer Wortleitung gehörenden Transistoren ist von den entsprechenden Transistoren eines anderen Bitleitungspaares oder einer anderen Wortleitung durch die in dem eingerahmten Bereich 21 dargestellte Dioden-/Widerstandskonfiguration entsprechend Fig. 1 entkoppelbar. Bei Vorliegen eines Chipauswahlsignals sind alle Entkoppeldioden D auf dem betreffenden Chip in Sperrichtung vorgespannt, so daß für die Speicherzellen auf dem Chip Einschreib-bzw. Auslesevorgänge durchgeführt werden können. Um bei gesperrter Entkoppeldiode D zu gewährleisten, daß die zu nicht selektierten Auswahlleitungen gehörenden Transistoren (entsprechend 18, 19 und 20) nicht zufällig durch einen durch Leckströme bedingten Potentialanstieg am Punkt A (Anode der Entkoppeldiode D) eingeschaltet werden können, ist zusätzlich ein Ableitwiderstand R parallel zum Anodenanschluß der Entkoppeldiode D vorgesehen. Damit über den Ableitwiderstand jedoch im Selektionsfall nur ein möglichst geringer Strom fließen kann, sollte der Ableitwiderstand R einen möglichst hohen Widerstandswert sowie eine möglichst parasitäre Kapazität aufweisen. Diese Eigenschaften gehen nämlich direkt in die erzielbaren Schaltzeiten sowie die Verlustleistung ein.With such an attractive integration with regard to the space requirement, the person skilled in the design of integrated circuits has a circuit arrangement available which he can advantageously use in connection with a wide variety of circuits. 4 shows as an application example the use of the diode / resistor configuration according to the invention in the control area of a semiconductor memory. FIG. 4 shows a section of a memory arrangement which is limited to a bit line pair BLO, BL1. As far as it is not important in the present case, the corresponding circuit parts are only indicated schematically, for. B. the memory cells, output amplifiers, etc. In order to achieve short cycle times with low power dissipation in such semiconductor memories, all word and bit selection lines must be charged or brought to defined DC voltage potentials for the idle state after each access period by means of a clocked control logic. For this purpose, a series of transistors are provided as current sinks and current sources, which are controlled by a schematically indicated circuit 17. Via the circuit 17, the base connections of the transistors 18, 19 and 20 can be selected in the absence of the reference potential VR, z. B. the smallest potential occurring in the circuit can be pulled down. The voltage drop across the isolating diode is neglected. Each such group of transistors belonging to a bit line pair or to a word line can be decoupled from the corresponding transistors of another bit line pair or another word line by means of the diode / resistor configuration shown in the boxed area 21 according to FIG. 1. In the presence of a chip selection signal, all decoupling diodes D are biased in the reverse direction on the chip concerned, so that write-in or. Readout processes can be carried out. To at blocked decoupling diode D to ensure that the transistors belonging to unselected selection lines (corresponding to 18, 19 and 20) cannot be switched on accidentally due to a potential rise at point A caused by leakage currents (anode of the decoupling diode D), a leakage resistance R is also parallel to the Anode connection of the decoupling diode D is provided. So that only the lowest possible current can flow through the bleeder resistor in the selection case, the bleeder resistor R should have the highest possible resistance value and the most parasitic capacitance. These properties go directly into the switching times that can be achieved and the power loss.

Es ist ersichtlich, daß im Rahmen einer integrierten Halbleiterspeicheranordnung eine derartige Entkoppeldioden-/Ableitwiderstandskonfiguration auf möglichst kleinem Raum realisieren lassen muß, um nicht eine Einbuße an auf dem Chip vorzusehenden Speicherzellen in Kauf nehmen zu müssen. Wie oben gezeigt wurde, wird diese außerordenlich hochintegrierte Auslegung durch die Erfindung ermöglicht.It can be seen that in the context of an integrated semiconductor memory arrangement, such a decoupling diode / leakage resistance configuration must be implemented in the smallest possible space in order not to have to accept a loss of memory cells to be provided on the chip. As has been shown above, this extraordinarily highly integrated design is made possible by the invention.

Claims (9)

1. Highly integrated semiconductor arrangement containing a diode-resistor configuration, the resistor (R) being designed as a pinch resistor whose pinch-doping area (5) is larger than the transverse dimension of the resistor area (4) representing the conductive channel, characterized in that in pinch-doping area (5) forms at the same time the cathode contact doping area for the diode (D) designed as a Schottky diode, and that on the resistor area (4) spaced from the pinch-doping area (5) a metal contact (A) extending over the surface on the resistor area (4) is provided which forms an ohmic contact on the resistor area, and a rectifying junction (at 7) for the Schottky diode with the semiconductor material (3) surrounding the resistor area (4) and of the opposite conductivity type, and that at one end of the resistor area (4) a connection for its electrical potential is provided.
2. Highly integrated semiconductor arrangement as claimed in claim 1, characterized in that on the pinch-doping area (5) a contact terminal (K) is provided for the cathode contact of the Schottky diode (D).
3. Highly integrated semiconductor arrangement as claimed in claim 2, characterized in that the pinch-doping area (5) has relative to the surrounding semiconductor material (3) of the same conductivity type a higher doping degree permitting at least the forming of an ohmic contact by a contact terminal designed as metal electrode (K) for the cathode contact of the Schottky diode, with the pinch-doping area (5).
4. Highly integrated semiconductor arrangement as claimed in one of claims 1 to 3, characterized in that the resistor area (4) is arranged in such a manner that at one end it extends into a doping area (2) of the same conductivity type provided primarily for the electric isolation of the diode-resistor configuration, so that the doping area (2) applies to the resistor area (4) its electric potential (VR).
5. Highly integrated semiconductor arrangement as claimed in one of claims 1 to 4, characterized in that the resistor represents a highly ohmic discharge resistor (R) in parallel to the Schottky diode (D.)
6. Highly integrated semiconductor arrangement as claimed in claim 5, characterized in that the discharge resistor (R) prevents in the reversed bias state of the Schottky diode (D) a rise of the potential at the anode of the Schottky diode, and thus prevents the Schottky diode from becoming conductive.
7. Highly integrated semiconductor arrangement as claimed in one of claims 1 to 6, characterized in that the diode-resistor configuration is provided in the selection lines for an electric storage cell arrangement (Fig. 4).
8. Highly integrated semiconductor arrangement as claimed in claim 7, characterized in that via the diode-resistor configuration the selection lines can be electrically separated or connected to or from further circuits for the defined charge or discharge of the selection lines in or between access operations to the storage cells.
9. Semiconductor arrangement as claimed in one of claims 1 to 8, characterized in that the pinch resistor has a P-conductively doped resistor area (4) within a surrounding N-conductive semiconductor material in a surrounding area (3), that the pinch doping area (5) of the pinch resistor is a relatively highly doped N-conductive area arranged between both ends of the resistor area (4) whose junction depth is lower than that of the resistor area (4), and that the metal contact (A) is arranged at one end of the resistor area (4).
EP78100195A 1977-07-26 1978-06-19 High-density integrated semiconductor device comprising a diode-resistor structure Expired EP0000472B1 (en)

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DE19772733615 DE2733615A1 (en) 1977-07-26 1977-07-26 Integrated semiconductor with diode-resistor configuration - has pinch resistor with pinch doped region greater than cross=section of residual resistor doped region
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