DK201470355A1

DK201470355A1 - Interface circuit for a hearing aid and method

Info

Publication number: DK201470355A1
Application number: DKPA201470355A
Authority: DK
Inventors: Henrik Ahrendt
Original assignee: Gn Resound As
Priority date: 2014-06-13
Filing date: 2014-06-13
Publication date: 2016-01-11

Abstract

An interface pad circuit configured for conveying an electrical signal from a semiconductor chip component to a component external to the semiconductor chip component, the interface pad circuit includes: a control circuit; a plurality of semiconductor elements, the semiconductor elements having respective bulk terminals and being controlled by the control circuit; and a connection pad; wherein at least two of the semiconductor elements are configured for providing a plurality of non-zero logic voltage levels to the connection pad; and wherein the control circuit is configured to apply a voltage level to the bulk terminals of the at least two of the semiconductor elements providing the non-zero logic voltage levels, the voltage level applied by the control circuit corresponding to the highest voltage level of the plurality of non-zero logic voltage levels.

Description

INTERFACE CIRCUIT FOR A HEARING AID AND METHODFIELD

This disclosure relates to hearing aids. More specific, it relates to hearingaids comprising multiple integrated electronic circuits.

BACKGROUND

A contemporary hearing aid comprises electronic circuits of very large scaleintegration in order to accommodate the circuits necessary to perform thedesired functionality of the hearing aid while keeping the physical size of thehearing aid as small as possible. This means that the chip or die containingthe semiconductor components of the hearing aid also has to be as small aspossible in order to fit within the hearing aid housing. At the same time thecircuit needs to be optimized to use as little power as possible in order toprolong the life of the battery powering the hearing aid.

Due to a number of practical issues, it is often necessary to distribute thecircuit on several silicon dies and provide interconnections between the partsof the circuit residing on different silicon dies or chips, e.g. in the form ofbonded electrical connections from one chip to another. Interface termi¬nations for these bondings are provided on each chip as larger, metalizedareas denoted pads. During assembly, the pads of different chips on thesame substrate are interconnected by bonding wires, e.g. by soldering orultrasound-welding the bonding wires to the pads forming electrical con¬nections between the wire ends and the pads. The wires and the pads usedin the assembly process are usually made from gold or other noble metalsresistant to corrosion. Transferring digital signals reliably between individualchips usually consumes a lot of power on the chip, mainly because of theparasitic capacitance introduced by the interfacing pads and the associatedcomponents and connections. Since the semiconductor elements present onthe chips are typically MOSFET transistors sensitive to electrostatic dis¬charges (BSD), the inclusion of special ESD protection circuits are alsomandatory when connecting chips to other chips or to peripheral components.

However, the ESD protection circuits also contribute to the parasitic capa¬citance of the interface pad circuit.

SUMMARY

A digital hearing aid circuit may beneficially be capable of operating at morethan one logic voltage level, e.g. during a power-on reset event, where thepads may temporarily provide electrical communication at a higher initial logicvoltage level than the logic voltage level used for nominal operation. When ailparts of the circuit is operating nominally, the voltage level provided by thepads may beneficially be lowered, e.g. to half the voltage of the initial voltagelevel. Thus, the interfacing pads have to be capable of conveying these vol¬tages to the circuits connected thereto whenever needed. Logic voltagelevels for hearing aid circuits may range from 0.5 volts to approximately 3volts.

An interface pad circuit adapted for conveying an electrical signal from asemiconductor chip component to a component external to the semicon¬ductor chip component is devised, the interface pad circuit comprising acontrol circuit, a plurality of semiconductor elements and a connection pad,each semiconductor element of the plurality of semiconductor elementshaving a bulk terminal and being controlled by the control circuit and adaptedfor providing a logic zero voltage level and a plurality of specific, non-zerologic voltage levels to the connection pad, wherein the highest voltage levelof the plurality of the provided logic voltage levels is applied to the bulkterminal of each of the semiconductor elements providing the non-zero logicvoltage levels.

This configuration gives the chip an enhanced drive strength and the capa¬bility of providing a plurality of different, non-zero logic voltage levels. In oneor more embodiments of the interface pad circuit, a set of three semi¬conductor elements in the form of MOSFET transistors is controlled by alogic control circuit in order to provide either a higher voltage level or a lowervoltage level to the interface pad according to requirements. A first PMOS

transistor controls the higher voltage level, an NMOS transistor controls thelogic “zero” voltage level (i.e. 0 volts), and a second PMOS transistor controlsthe lower voltage level. The NMOS transistor and the first PMOS transistorboth have their bulk terminals permanently connected to their respectivesource terminals in order to preserve the threshold capabilities of thetransistors. However, the second PMOS transistor has its bulk terminalconnected to the higher voltage level. All three transistors have their drainterminals connected to the pad output terminal in order to provide the desiredlogic voltage to external components connected thereto.

If the second PMOS transistor providing the lower voltage level were to haveits bulk terminal connected to its source terminal in a fashion similar to thefirst PMOS transistor, this configuration would lead to a situation where thedrain-bulk diode present in the second PMOS transistor would conduct acurrent whenever the first PMOS transistor was turned on and the secondPMOS transistor was turned off due to the voltage difference between thelower and the higher voltage levels exceeding the threshold voltage VT of thesecond PMOS transistor. Therefore, the bulk terminal of the second PMOStransistor needs to be connected to the higher voltage in order for the voltagedifference between the drain and bulk terminals to be smaller than thethreshold voltage. However, this arrangement leads to a degradation of thethreshold voltage of the second PMOS transistor.

In order to counteract the degradation of the threshold of the second PMOStransistor following from the higher bulk voltage potential, this embodimentneeds to utilize a specially designed PMOS transistor due to the fact that thebulk voltage is now higher than the source voltage of the transistor. When thethreshold of the second PMOS transistor is degraded, the transistor has to bemade physically much wider (up to fifteen times wider in worst cases) inorder to keep the drain-source on-resistance Rds of the transistor below itsmaximum allowable value.

The dynamic power requirement of a switching circuit is given by:

Here V denotes a logic Ί” voltage level, f is the switching frequency and C isthe capacitance of the switching circuit. In this context, the term ‘circuit’ maycover single semiconductor elements as well as large, complex circuits. Fromequation (1) it will be obvious that the voltage level V should be as low aspossible in order to minimize the dynamic power dissipation in a transistorsince the dynamic power increases with the voltage squared. In other words,since both the capacitance of the second PMOS transistor is larger due tothe larger physical width and the threshold voltage VT is higher than thenominal voltage of the rest of the hearing aid circuit, as discussed in theforegoing, this design ends up taking up more space on the chip and costinga lot of dynamic power.

If the drain-source on-resistance of the second PMOS transistor is too high itwill put a limitation on the current that can be provided by the transistor, andconsequently, the drive strength of the interface pad circuit will be too low. Inthis embodiment, this may only be alleviated by utilizing a wider transistordesign at the cost of an increase in the area used on the chip by thetransistor and an increase in dynamic power due to the larger parasitic andgate capacitances as a consequence of using the physically iarger transistor.

Thus, a need exists for an interface pad circuit design where these problemsare reduced or eliminated. In order to keep the dynamic power requirementof the interface circuit pad low, an alternative embodiment capable of utilizinga smaller transistor design is described in the following.

Further, an interface pad circuit is devised, said interface pad circuit furtherhaving the control circuit adapted for selectively providing one of the pluralityof non-zero logic voltages to the bulk terminal of each one of thesemiconductor elements, wherein at least one of the voltages provided to thebulk terminal of a particular semiconductor element is substantially equal tothe logic voltage level provided by that particular semiconductor element, and at least another of the voltages provided to the bulk terminal of the samesemiconductor element is substantially equal to the highest logic voltagelevel provided by any semiconductor element feeding the interface pad.

As used in this specification, the term “substantially equal” or similar terms,such as “substantially the same", etc., refers to two items that do not differ bymore than 10%. For example, if a voltage or voltage level is described asbeing “substantially equal to” or “substantially the same as" another voltageor voitage level, that means the two voltages or the two voltage levels do notdiffer by more than 10% (e.g., the two voltages or voltage levels may differ by9%, 5%, 3%, 1%, may be equal, etc.).

In this interface pad circuit, the bulk terminal of each semiconductor elementis thus provided with one of two bulk biasing voltages, if the semiconductorelements are embodied as MOS transistors, the drain-bulk diode of the MOStransistors remains closed when the bulk bias voltage is applied, i.e. noexcess current is drawn, and the on-resistance Rds of the MOS transistorsremains sufficiently low, thus eliminating the need to utilize a wider transistor.This allows for smaller transistor devices to be used for providing the desiredlogic voltage levels on the chip while maintaining the desired drive strength ofthe output pad. As stated in the foregoing, a smaller MOS transistor also hasthe added benefit of a smaller inherent capacitance and therefore a lowerdynamic power requirement.

In an exemplary interface pad circuit, the control circuit is adapted to applythe non-zero logic voltage level being substantially equal to the voltage levelprovided by a particular semiconductor element to the bulk terminal of thatparticular semiconductor element when that particular semiconductor ele¬ment is providing its associated non-zero logic voltage level to the interfacepad, and to apply the highest logic voitage level provided by any semicon¬ductor element feeding the interface pad to the bulk terminal of the particularsemiconductor element when any other semiconductor element of the inter¬face pad is providing its logic voltage level to the interface pad.

This embodiment allows for an arbitrary number of non-zero logic voltagelevels to be provided by the interface pad circuit while maintaining high drivestrength, low dynamic power consumption and a modest physical spacerequirement on the silicon chip.

The subject disclosure also relates to a method of operating an interface padof a microelectronic integrated circuit, said method involving the steps of pro¬viding the microelectronic circuit, said circuit comprising a plurality of semi¬conductor elements each controlling a logic voltage level, wherein eachsemiconductor element of the plurality of semiconductor elements is providedwith one of two bulk biasing voltages, the first bulk biasing voltage being sub¬stantially equal to the logic voltage level provided by that particularsemiconductor element, and the second bulk biasing voltage being substan¬tially equal to the highest logic voltage level provided by any semiconductorof the interface pad, and wherein the first of the two bulk biasing voltages isprovided to the bulk terminal of the particular semiconductor element whenthat particular semiconductor element is controlling the logic voltage levelcorresponding to that semiconductor, and the second of the two bulk biasingvoltages is provided to the bulk terminal of the particular semiconductor ele¬ment when any other semiconductor element of the interface pad is con¬trolling the logic voltage level corresponding to the other semiconductor.

Thus, a method of operating an interface pad of a microelectronic circuit isdevised, enabling the interface pad to drive inputs on other microelectroniccircuits at a plurality of logic voltage levels by controlling the bulk biasing vol¬tage to each semiconductor. The method is therefore of particular interest inoperating electronic circuits in hearing aids. By providing each semiconductorelement with a selection of two different bulk biasing voltages, leakage cur¬rent of the particular semiconductor element may thus be minimized whenthe interface pad is configured to provide logic voltages different from thelogic voltage provided by that particular semiconductor element. Each semi¬conductor element of the interface pad may also be made smaller as aconsequence of this arrangement, thus reducing the dynamic power require- merits of the interface pad. The method is of particular relevance to interfacepads of microelectronic circuits intended for use in hearing aids, where phy¬sical space and available power are severely restricted.

An interface pad circuit configured for conveying an electrical signal from asemiconductor chip component to a component external to the semicon¬ductor chip component, the interface pad circuit includes: a control circuit; aplurality of semiconductor elements, the semiconductor elements havingrespective bulk terminals and being controlled by the control circuit; and aconnection pad; wherein at least two of the semiconductor elements areconfigured for providing a plurality of non-zero logic voltage levels to theconnection pad; and wherein the highest voltage level of the plurality of theprovided logic voltage levels is applied to the bulk terminals of the at leasttwo of the semiconductor elements providing the non-zero logic voltagelevels.

The control circuit may be configured to apply a voltage level to the bulkterminals of the at least two of the semiconductor elements providing thenon-zero logic voltage levels, the voltage level applied by the control circuitcorresponding to the highest voltage level of the plurality of

Optionally, at least one of the semiconductor elements is configured toprovide a logic zero voltage level.

Optionally, the control circuit is configured for selectively providing a first non¬zero logic voltage or a second non-zero logic voltage to the bulk terminal ofone of the semiconductor elements, wherein the first non-zero logic voltage issubstantially equal to the logic voltage level provided by the one of thesemiconductor elements, and the second non-zero logic voltage is sub¬stantially equal to the highest logic voltage level provided by another one ofthe semiconductor elements.

Optionally, the control circuit is configured to apply the first non-zero logicvoltage to the bulk terminal of the one of the semiconductor elements whenthe one of the semiconductor elements is providing its associated non-zerologic voltage level to the interface pad; and wherein the control circuit is configured ίο apply the second non-zero logic voltage to the bulk terminal ofthe one of the semiconductor elements when another one of the semi¬conductor elements is providing its associated logic voltage level to theinterface pad.

Optionally, the voltage level applied by the control circuit is the same orsubstantially the same as the highest voltage level of the plurality of non-zeroiogic voltage levels.

Optionally, the interface pad circuit further includes a first switch configuredto supply a first bulk biasing voltage to the bulk terminal of one of thesemiconductor elements controlled by the control circuit.

Optionally, the interface pad circuit further includes a second switchconfigured to supply a second bulk biasing voltage to the bulk terminal of theone of the semiconductor elements controlled by the control circuit.

Optionally, a first control signal for the first switch and a second control signalfor second switch are mutually exclusive.

Optionally, first switch and the second switch are microelectronic switchesembodied in the interface pad circuit.

Optionally, the semiconductor elements comprises one or more MOStransistors.

Optionally, the control circuit has a logic input terminal, a pad level controlterminal, and a plurality of output terminals for controlling the semiconductorelements.

Optionally, the control circuit is configured to provide mutualiy exclusivecontrol signals to the plurality of semiconductor elements.

A method of operating a microelectronic integrated circuit, the microeiectronic circuit comprising a plurality of semiconductor elements each providing alogic voltage level, the method includes: providing one of the semiconductorelements with a first bulk biasing voltage or a second bulk biasing voltage,the first bulk biasing voltage being substantially equal to the logic voltagelevel provided by the one of the semiconductor elements, and the second buik biasing voltage being substantially equal to the highest logic voltagelevel provided by another one of the semiconductor elements; wherein thefirst buik biasing voltage is provided to the bulk terminal of the one of thesemiconductor elements when the one of the semiconductor elements isproviding its corresponding logic voltage level; and wherein the second bulkbiasing voltage is provided to the bulk terminal of the one of thesemiconductor elements when another one of the semiconductor elements isproviding its corresponding logic voltage level.

Optionally, the semiconductor elements comprise MOS transistors.

Optionally, the microelectronic integrated circuit is configured for use in ahearing aid.

Other and further aspects and features will be evident from reading thefollowing detailed description.

DESCRIPTION OF THE FIGURES

The disclosure will now be described in further detail with reference to the drawings, where fig. 1 is an exemplary schematic diagram of an embodiment of an interface pad circuit, fig. 2 is a functional timing diagram of the control signals for the embodiment shown in fig. 1, fig. 3 is an exemplary schematic diagram of an alternative embodiment of aninterface pad circuit with controlled bulk voltage connections.

fig. 4 is a functional timing diagram of the control signals for the embodimentshown in fig. 3, and fig. 5 is a schematic diagram of an embodiment of an interface pad circuitcapable of handing three different logic voltage levels.

DETAILED DESCRIPTION

Various features are described hereinafter with reference to the figures. Itshould be noted that the figures may or may not be drawn to scale and thatthe elements of similar structures or functions are represented by likereference numerals throughout the figures. It should be noted that thefigures are only intended to facilitate the description of the features. They arenot intended as an exhaustive description of the claimed Invention or as alimitation on the scope of the claimed invention. In addition., an illustratedfeature needs not have all the aspects or advantages shown. An aspect oran advantage described in conjunction with a particular feature is notnecessarily limited to that feature and can be practiced in any other featureseven if not so illustrated or if not so explicitly described.

Fig 1 is a schematic diagram showing the major parts of an interface padcircuit 1 of a microelectronic chip for a hearing aid according to a first embo¬diment. The interface pad circuit 1 comprises a control circuit 2, a first PMOStransistor 3, an NMOS transistor 4, a second PMOS transistor 5 and an inter¬face pad 7. The first PMOS transistor 3 comprises a gate terminal 16, asource terminal 17, a drain terminal 18 and a bulk terminal 19, the NMOStransistor 4 comprises a gate terminal 20, a source terminal 21, a drain ter¬minal 22 and a bulk terminal 23, and the second PMOS transistor 5comprises a gate terminal 24, a source terminal 25, a drain terminal 26 and abulk terminal 27. The gate 24 of the second PMOS transistor 5 is connectedto the control circuit 2 via a first control line 11 carrying the control signalPM2 ctri (asserted LOW), the gate 16 of the first PMOS transistor 3 is con¬nected to the control circuit 2 via a second control line 12 carrying the controlsignal PM 1 ctri (asserted LOW), and the gate 20 of the NMOS transistor 4 isconnected to the control circuit 2 via a third control line 13 carrying the con¬trol signal NMctri (asserted HIGH).

The bulk terminal 19 and the source terminal 17 of the first PMOS transistor3 are connected to a first voltage node 28 carrying a first logic voltage Vddi,the bulk terminal 23 and the source terminal 21 of the NMOS transistor 4 are connected to a common node, the source terminal 25 of the second PMOStransistor 5 is connected to a second voltage node 29 carrying a second logicvoltage Vdd2, and the bulk terminal 27 of the second PMOS transistor 5 isalso connected to the first voltage node 28. In the circuit in fig. 1, the voltageVddi of the first voltage node 28 is larger than the voltage VDd2 of the secondvoltage node 29. The voltage Vddi is thus provided to the bulk terminals ofboth the first PMOS transistor 3 and the second PMOS transistor 5. Thedrain 18 of the first PMOS transistor 3, the drain 22 of the NMOS transistor 4and the drain 26 of the second PMOS transistor 5 are all connected to theinterface pad 7 via an interface output line 15. The control circuit 2 alsocomprises a logic signal input terminal 8 and a VoD2_enabie terminal 9 forcontrolling the behavior of the interface pad circuit 1. The logic signal inputterminal 8 of the control circuit 2 receives a logic input signal from other partsof the chip (not shown), the logic input signal being intended for components(not shown) external to the chip via the interface pad 7 as a logic voltageVddi or VDd2, respectively, suitable for driving external components.

The purpose of the interface pad circuit 1 shown in fig. 1 is to convey digitalvoltages from the silicon chip comprising the interface pad circuit 1 toadjacent chips on the same substrate in e.g. a hearing aid via electric bon¬dings or wires connected to the interface pad 7. Due to different needs of theexternal components at various points in the startup procedure of the hearingaid, the interface pad circuit 1 must be capable of delivering digital signalingat different logic levels, i.e. 0 volts, representing a digital “0”, and Vddi andVdd2> respectively, representing a digital Ί” at two different logic levels.

The control circuit 2 outputs three mutually exclusive control signals, NMctri,PMi ctri and PM2_ctri, respectively, if a (positive asserted) control signal NMctrifrom the third control line 13 of the control circuit 2 is received on the gateterminal 20 of the NMOS transistor 4, the voltage level of the interface pad 7is 0 volts, i.e. a digital “0”. If a (negative asserted) control signal PM1 ctri fromthe second control line 12 of the control circuit 2 is received on the gate ter¬minal 16 of the first PMOS transistor 3, the voltage level of the interface pad 7 is Vddi volts, i.e. a digital “1” of the higher logic level. When a (negative as¬serted) control signal PM2_ctri from the first control line 11 of the control circuit2 is received on the gate terminal 24 of the second PMOS transistor 5, thevoltage level of the interface pad 7 is VDd2 volts, i.e. a digital “1” of the lowerlogic level.

The reason that the bulk terminal 27 of the second PMOS transistor 5 is notconnected to the source terminal 25 of the second PMOS transistor 5 in thesame manner as the first PMOS transistor 3 and the NMOS transistor 4 isthat if the voltage level of the interface pad 7 is above the lower logic levelplus the threshold voltage Vt of the second PMOS transistor 5, the intrinsicdiode present between the drain terminal 26 and the bulk terminal 27 of thesecond PMOS transistor 5 would conduct a current even if the gate 24 of thesecond PMOS transistor 5 was intended to be OFF, leading some of the cur¬rent delivered by the first voltage node 28 directly to the second voltage node29 instead, thus wasting power which could otherwise be used to drive theinterface pad 7. This would be the case when the first PMOS transistor 3 isON, since

Vddi>Vdd2 (2) and PMOSi(ON)=WpAD>VDD2+Vti1 (3)

Thus, the drain-bulk diode of the second PMOS transistor 5 would conduct.

In order to counteract the problems associated with this configuration, theinterface pad circuit 1 of the prior art has the bulk terminal 27 of the secondPMOS transistor 5 connected to Vddi instead of VDd2-

This configuration does, however, create other problems. Since the voltageVddi present on the bulk terminal 27 of the second PMOS transistor 5 ishigher than the voltage Vdd2 present on the source terminal 25 of the secondPMOS transistor 5 whenever the second PMOS transistor 5 is ON, the thres¬ hold voltage V-r of the second PMOS transistor 5 is degraded due to the bulkeffect, thus:

Here, Vtb is the threshold voltage when a substrate voltage is present, Vto isthe value of the threshold voltage when the voitage difference betweensource and bulk is zero, i.e. Vsb=0, and γ and <j>s are PMOS device para¬meters. As may be shown by equation (4), if the bulk potential on a PMOStransistor relative to the source potential on the PMOS transistor goes up,then the threshold voltage Vtb also goes up because of the bulk effect. Oneway to counteract this phenomenon and compensate for the higher ON-resis-tance Rds resulting from the degraded threshold level is to make the secondPMOS transistor 5 physically significantly wider. This has two detrimentaleffects on the interface pad circuit 1. Firstly, a wider transistor occupies agreater area on the chip, ieading to higher production costs, secondly, the re¬sulting increased parasitic capacitance and gate capacitance associated witha physically larger transistor will lead to an increase in dynamic powerconsumption by the transistor, cf. equation (1).

Fig. 2 is a functional timing diagram showing significant voltage levels andmutual timings of the interface pad circuit 1 in fig 1. First from the top downthrough the timing diagram is the binary, digital input signal driving the controlcircuit 2, then the VDD2_enabie signal (asserted positive), the control signalNMctri for the NMOS transistor 4 (asserted positive), the control signal PMi ctricontrolling the first PMOS transistor 3 (asserted negative), the control signalPM2_ ctr: controlling the second PMOS transistor S (asserted negative) and thevoltage level present on the interface pad 7. As stated in the foregoing, Vddiis the higher logic Ί” output level and VDD2 is the lower logic “1” output levelof the interface pad 7. In the following, the functional timing diagram is refe¬renced from left to right.

On the first digital “0” from the left in fig. 2, the NMOS transistor 4 is turnedON and the two PMOS transistors 3 and 5 are both turned OFF. The voltageof the interface pad 7 is zero. On the first digital “1”, the NMOS transistor 4and the second PMOS transistor 5 are both turned OFF, and the first PMOStransistor 3 is turned ON. The voltage level present on the interface pad 7 isVddi due to the fact that the VDD2_enabie signal is still OFF. The second digital“0” has the same effect as the first digital “0”. On the second digital “1”, how¬ever, the VoD2_enabie signal is ON, the NMOS transistor 4 and the first PMOStransistor 3 are both OFF, and the second PMOS transistor 5 is ON. The vol¬tage present on the interface pad 7 is therefore Vdd2- Thus, the interface padcircuit 1 is capable of providing two different, logic “1’’-levels for driving ex¬ternal circuitry.

Even though the interface pad circuit 1 of fig 1 performs its intended function,it has less-than-ideal performance parameters due to the problems of thebulk voltage potential on the bulk terminal 27 of the second PMOS transistor5 being higher than the voltage potential on the source terminal 25 of the se¬cond PMOS transistor 5, as discussed in the foregoing. A more effective andoptimized design for an interface pad circuit for a microelectronic circuit isdescribed in the following.

An alternative design for an interface pad circuit T is disclosed in fig. 3. Theinterface pad circuit 1 ’ shown in fig. 3 has features similar to the circuit 1 offig. 1 apart from the following features: The control circuit 2 has a first bulkbiasing control terminal 33 and a second bulk biasing control terminal 34 forcontrolling the bulk biasing voltage level delivered to the bulk terminal 27 ofthe second PMOS transistor 5. The first bulk biasing control terminal 33carries the signal BVddi and the second bulk biasing control terminal 34carries the signal BVW- The higher bulk biasing voltage Vddi is applied tothe bulk terminal 27 of the second PMOS transistor 5 via a first voltage-controlled switch 35 controlled by the signal from the first bulk biasing controlterminal 33, and the lower bulk biasing voltage VW is applied to the bulkterminal 27 of the second PMOS transistor 5 via a second voltage-controlled switch 36 controlled by the signal from the second bulk biasing controlterminal 34. The voltage-controlled switches 35 and 36 are shown in fig. 3 asplain switches for clarity, but are in fact embodied on-chip as MOS transistorscontrolled by the control circuit 2. The signals BVddi and BVdd2 from the bulkbiasing control terminals 33 and 34 of the control circuit 2 are mutually exclu¬sive.

The effect of this embodiment is that it is possible to control the bulk biasingvoltage level applied to the bulk terminal 27 of the second PMOS transistor 5of the interface pad circuit T in a convenient and simple manner. By con¬trolling the bulk biasing voltage level applied to the bulk terminal 27 of thesecond PMOS transistor 5, several benefits are obtained. One benefit is thatthe problem with the drain-bulk diode of the second PMOS transistor 5 con¬ducting unintentionally is eliminated completely, since the voltage potential ofthe output pad 7 is never allowed to exceed the voltage potential present onthe bulk terminal 27 of the second PMOS transistor 5, and the condition ofequation (3) is therefore not fulfilled. Another benefit is that the degradationof the threshold voltage Vj of the second PMOS transistor 5 is also elimi¬nated, since the voltage potential on the bulk terminal 27 of the secondPMOS transistor 5 is now higher than the voltage potential on the sourceterminal 25 only when the second PMOS transistor 5 is OFF, and equal tothe voltage potential on the source terminal 25 when the second PMOS tran¬sistor 5 is ON. In fact, this permits the second PMOS transistor 5 to be madeconsiderably smaller physically, thus reducing the area on the chip occupiedby the semiconductor device, consequently reducing the correspondingcapacitance of the second PMOS transistor 5, which in turn reduces the dy¬namic power consumed by the device, thus saving energy.

Fig. 4 is a functional timing diagram showing voltage levels and mutualtimings of the interface pad circuit T in fig. 3. The timing diagram in fig. 4 issimilar to the timing diagram shown in fig. 2 apart from the fact that timingsfor the control signals of bulk biasing voltages BVddi and BVdd2 are alsoshown in fig. 4. The control signal for the low bulk biasing voltage terminal BVdd2 follows the control signal VDd2 enable closely, and the control signalBVddi is complementary of that, being OFF whenever the control signalBVdd2 is ON, and vice versa, in other words, when the high logic “1” voltagelevel is used, the high bulk biasing voltage Vddi is provided to the bulk ter¬minal 27 of the second PMOS transistor 5, and when the low logic “V voltagelevel is used, the low bulk biasing voltage Vdd2 is provided to the bulk termi¬nal 27 of the second PMOS transistor 5.

In one embodiment, the physical size of the second PMOS transistor 5 in theinterface pad circuit 1 ’ may be reduced on the chip to about 6-7% of the sizeof the second PMOS transistor 5 in the interface pad circuit 1 without com¬promising on the ON-resistance Rds. If a hearing aid chip comprises e.g. fourinterface pads of the kind shown in fig. 3 for connection to other circuits, thisconfiguration contributes considerably to the smalier size, higher efficiencyand low current consumption of the whole chip. In typical embodiments, theremay be eight or more interface pads available on-chip without an excessiveamount of power being drawn by the circuit.

In another alternative embodiment, the interface pad circuit may be capableof driving external components at three or more different logic voltage levelsall selected by the control circuit 2. One such embodiment is shown in fig. 5,where an interface pad circuit 1” further has a third PMOS transistor 6 pro¬viding a logic voltage VDd3 to the interface pad 7 via a third voltage node 30.

In other respects, the interface pad circuit 1” has features similar to the in¬terface pad circuit 1’ shown in fig. 3. Both the voltage level VW and thevoltage level Vdd3 are lower than the voltage level Vddi· The third PMOStransistor 6 is controlled by the control circuit 2 via a fourth control line 14providing the control signal PM3 cw- A bulk terminal of the third PMOStransistor 6 is connected to a node shared by a third voltage-controlled switch37 and a fourth voltage-controlled switch 38. The control circuit 2 further hasa Vdd3 enable input terminal 10 for controlling the provision of the logic voitageVdd3 to the interface pad 7 and a control terminal 32 carrying the controlsignal BVdd3 for controlling the fourth voltage-controlled switch 38. The purpose of the fourth voitage-controiied switch 38 is to provide the logicvoltage Vdds to the bulk terminal of the third PMOS transistor 6 whenever thelogic output voltage Vdds is to be utilized by the interface pad 7. The purposeof the third voltage-controlled switch 37 is to provide the highest logic voltageVddi to the bulk terminal 31 of the third PMOS transistor 6 whenever eitherVddi or Vdd2 is utilized by the interface pad 7,

When the logic output voltage Vdd i is provided by the interface pad 7, thefirst PMOS transistor 3 is activated by the control circuit 2 via the secondcontrol line 12. In this case, the bulk biasing voltage on the bulk terminal ofthe second PMOS transistor 5 and the third PMOS transistor 6, respectively,is set to VDdi, i.e. the highest bulk biasing voltage, by closing the first voitage-controlled switch 35 and the third voitage-controiled switch 37.

When VDD2 is provided by the interface pad 7, the second PMOS transistor 5is activated by the control circuit 2 via the first control line 11. In this case, thebulk biasing voltage on the bulk terminal of the third PMOS transistor 6 is setto Vddi by closing the third voitage-controiied switch 37, and the bulk biasingvoltage on the bulk terminal of the second PMOS transistor 5 is set to Vdd2by closing the second voitage-controiied switch 36.

When Vdd3 is provided by the interface pad 7, the third PMOS transistor 6 isactivated by the control circuit 2 via the fourth control line 14. In this case, thebulk biasing voltage on the bulk terminal of the second PMOS transistor 5 isset to Vddi by closing the first voitage-controiied switch 35, and the buik bia¬sing voltage on the bulk terminal of the third PMOS transistor 6 is set to Vdd3by dosing the second voltage-controlled switch 38.

In another embodiment, the interface pad circuit comprises a plurality n ofPMOS transistors being adapted for providing one of n corresponding logicvoltage levels Vdd« to the interface pad 7. The control circuit 2 is then adap¬ted for applying the highest bulk biasing voltage VDdi to the bulk terminals ofeach of the n PMOS transistors if another logic voltage level than the logicvoltage level VDDn supplied by the n’th PMOS transistor is provided to the in¬ terface pad 7, and applying the bulk biasing voltage Vdda? to the bulk terminalof the n’th PMOS transistor if the logic voltage level Vdd« is supplied.

A simple and effective design for an interface pad circuit for an electronic cir¬cuit, such as a microelectronic circuit for use in a hearing aid, may hereby berealized. Although the interface pad circuit is described herein with referenceto specific configurations and embodiments, the interface pad circuit is by nomeans limited to these embodiments but may be realized in many other wayswithout deviating from the limitations provided by the claims.

Although particular features have been shown and described, it will beunderstood that they are not intended to limit the claimed invention, and it willbe made obvious to those skilled in the art that various changes andmodifications may be made without departing from the spirit and scope of theclaimed invention. The specification and drawings are, accordingly to beregarded in an illustrative rather than restrictive sense. The claimedinvention is intended to cover all alternatives, modifications and equivalents.

Claims

1. An interface pad circuit configured for conveying an electrical signalfrom a semiconductor chip component to a component external to thesemiconductor chip component, the interface pad circuit comprising: a control circuit; a plurality of semiconductor elements, the semiconductor elementshaving respective bulk terminals and being controlled by the control circuit;and a connection pad; wherein at least two of the semiconductor elements are configured forproviding a plurality of non-zero iogic voltage levels to the connection pad;and wherein the highest voltage level of the plurality of the provided logicvoltage levels is applied to the bulk terminals of the at least two of thesemiconductor elements providing the non-zero logic voltage levels.

2. The interface pad circuit according to claim 1, wherein at least one ofthe semiconductor elements is configured to provide a logic zero voltagelevel.

3. The interface pad circuit according to claim 1, wherein the controlcircuit is configured for selectively providing a first non-zero logic voltage or asecond non-zero logic voltage to the bulk terminal of one of thesemiconductor elements, wherein the first non-zero logic voltage issubstantially equal to the logic voltage level provided by the one of thesemiconductor elements, and the second non-zero logic voltage issubstantially equal to the highest logic voltage level provided by another oneof the semiconductor elements.

4. The interface pad circuit according to claim 3, wherein the controlcircuit is configured to apply the first non-zero logic voltage to the bulkterminal of the one of the semiconductor elements when the one of the semi¬ conductor elements is providing its associated non-zero logic voltage level tothe interface pad; and wherein the control circuit is configured to appiy the second non-zerologic voltage to the bulk terminal of the one of the semiconductor elementswhen another one of the semiconductor elements is providing its associatedlogic voltage level to the interface pad.

5. The interface pad circuit according to claim t, wherein the voltagelevel applied by the control circuit is the same or substantially the same asthe highest voltage level of the plurality of non-zero logic voltage levels.

6. The interface pad circuit according to claim 1, further comprising a firstswitch configured to supply a first bulk biasing voltage to the bulk terminal ofone of the semiconductor elements controlled by the control circuit.

7. The interface pad circuit according to claim 6, further comprising asecond switch configured to supply a second bulk biasing voltage to the bulkterminal of the one of the semiconductor elements controlled by the control circuit.

8. The interface pad circuit according to claim 7, wherein a first control signal for the first switch and a second control signal for second switch aremutually exclusive.

9. The interface pad circuit according to claim 7, wherein first switch andthe second switch are microelectronic switches embodied in the interface padcircuit.

10. The interface pad circuit according to claim 1, wherein thesemiconductor elements comprises one or more MOS transistors.

11. The interface pad circuit according to claim 1, wherein the controlcircuit has a logic input terminal, a pad level control terminal, and a pluralityof output terminals for controlling the semiconductor elements.

12. The interface pad circuit according to claim 1, wherein the controlcircuit is configured to provide mutually exclusive control signals to theplurality of semiconductor elements.

13. A method of operating a microelectronic integrated circuit, themicroelectronic circuit comprising a plurality of semiconductor elements eachproviding a logic voltage level, the method comprising: providing one of the semiconductor elements with a first bulk biasingvoltage or a second bulk biasing voltage, the first bulk biasing voltage beingsubstantially equal to the logic voltage level provided by the one of thesemiconductor elements, and the second bulk biasing voltage beingsubstantially equal to the highest logic voltage level provided by another oneof the semiconductor elements; wherein the first bulk biasing voltage is provided to the bulk terminai ofthe one of the semiconductor elements when the one of the semiconductorelements is providing its corresponding logic voltage level; and wherein the second bulk biasing voltage is provided to the bulkterminal of the one of the semiconductor elements when another one of thesemiconductor elements is providing its corresponding logic voltage level.

14. The method according to claim 13, wherein the semiconductorelements comprise MOS transistors.

15. The method according to claim 13, wherein the microelectronicintegrated circuit is configured for use in a hearing aid.