DK170848B1 - Digital DQPSK decoder circuit and use of the decoder circuit - Google Patents
Digital DQPSK decoder circuit and use of the decoder circuit Download PDFInfo
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- DK170848B1 DK170848B1 DK717288A DK717288A DK170848B1 DK 170848 B1 DK170848 B1 DK 170848B1 DK 717288 A DK717288 A DK 717288A DK 717288 A DK717288 A DK 717288A DK 170848 B1 DK170848 B1 DK 170848B1
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- DK
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Microcomputers (AREA)
Description
i DK 170848 B1in DK 170848 B1
Opfindelsen angår et digitalt DQPSK dekoderkredsløb for gendannelse af fasedifferensdata fra multibit fasedata, der er til stede ved den oprindelige datahyppighed for DPSK datapar.The invention relates to a digital DQPSK decoder circuit for recovering phase difference data from multibit phase data present at the original data frequency of DPSK data pairs.
55
For at gøre det lettere at forstå opfindelsen vil modulationsfremgangsmåden, der blandt eksperter kaldes "differential kvadratur fase-skift kodning", forkortet DQPSK: "diffential quadrature phase-shift keying", blive beskre-10 vet først. Ved taktimpulsstyret transmission af serielle binærdata på en bånd-begrænset kanal, inddeles strømmen af binærdata i en taktimpulsstyret sekvens af 2-bit datapar, også kaldes "symboler", således at der dannes fire digitale ord 00, 01, 10, 11. Hvis taktimpulsfrekvensen 15 for strømmen af binærdata kaldes "datahyppigheden", er symbolhyppigheden halvt så stor som datahyppigheden.To make it easier to understand the invention, the modulation method, which among experts is called "differential quadrature phase-shift coding," abbreviated DQPSK: "differential quadrature phase-shift keying", will be described first. In clock pulse-controlled transmission of serial binary data on a band-limited channel, the flow of binary data is divided into a clock pulse-controlled sequence of 2-bit data pairs, also called "symbols", so that four digital words 00, 01, 10, 11. are formed. 15 for the flow of binary data called "data frequency", the symbol frequency is half the data frequency.
Hvis disse (2-bit) digitale ord fortolkes som koordinater i et rektangulært koordinatsystem og betragtes som binære 20 tal i 2's komplementære repræsentation, kan de anvendes til at repræsentere koordinataksernes fire gennemskæringer af enhedscirklen, d.v.s. ved de fire vinkler 0°, 90°, 180°, og 270°. Ved differential kvadratur fase-skift kodning anvendes sådanne digitale ord som DPSK datapar til 25 at repræsentere faseforskellen i forhold til den foregående faseværdi, således at DPSK datapar 00, 10, 11 og 01 er ækvivalente med f.eks. faseforskellene 0°, 90° eller -270°, +/- 180°, og 270° eller -90°, respektive.If these (2-bit) digital words are interpreted as coordinates in a rectangular coordinate system and are considered as binary 20 numbers in the complementary representation of 2, they can be used to represent the four intersections of the coordinate axes of the unit circle, i.e. at the four angles 0 °, 90 °, 180 °, and 270 °. In differential quadrature phase-shift coding, such digital words as DPSK data pairs are used to represent the phase difference relative to the previous phase value, so that DPSK data pairs 00, 10, 11 and 01 are equivalent to e.g. the phase differences 0 °, 90 ° or -270 °, +/- 180 °, and 270 ° or -90 °, respectively.
3030
Ved transmission filtreres DPSK dataparrene ved hjælp af analoge eller digitale kredsløb; i sidstnævnte tilfælde vil frekvensen for taktimpulssignalet til de to digitale filtre, der er nødvendige til dette formål, generelt være 35 højere end den tidligere nævnte taktimpulsfrekvens.In transmission, the DPSK data pairs are filtered by analog or digital circuits; in the latter case, the frequency of the clock pulse signal for the two digital filters necessary for this purpose will generally be 35 higher than the previously mentioned clock pulse frequency.
2 DK 170848 B12 DK 170848 B1
Efter filtreringen foretages der på udgangssignalerne en kvadraturamplitudemodulation, nemlig til analog kvadraturmodulation efter analog filtrering, og til digital kvadraturmodulation efter digital filtrering, d.v.s. at 5 bærebølgen herefter ikke er et kontinuert signal, men består (kun) af samplede amplituder af bæresignalet, i overensstemmelse med samplingsteorien.After filtering, a quadrature amplitude modulation is performed on the output signals, namely for analog quadrature modulation after analog filtering, and for digital quadrature modulation after digital filtering, i.e. that the carrier is then not a continuous signal, but consists (only) of sampled amplitudes of the carrier signal, in accordance with the sampling theory.
Efter denne kvadraturmodulation, adderes de indbyrdes or-10 togonale signaler for de to "kanaler”, og dette adderede signal konverteres fra digital til analog form. I denne form sendes signalet ud på en transmissionsbane.After this quadrature modulation, the orbital signals are added to each of the two "channels" and this added signal is converted from digital to analog form. In this form, the signal is transmitted on a transmission path.
Ved modtagelse af signalet foretages der en analog-digi-15 tal konvertering med en tilsvarende høj samplingshyppighed, hvilket efterfølges af en (digital) kvadraturampli-tudedemodulation, således at de to udgangssignaler fra demodulatoren afgiver en serie af digitale ortogonale signalpar. Efter lavpasfiltrering af de to kanaler opnås 20 der et signalpar fra hvilket symbolhyppigheden (lig med halvdelen af datahyppigheden) må gendannes med hensyn til frekvens og fase. Dette kan f.eks. gøres som beskrevet i "IEEE Transactions on Communications", maj 1986, side 423 til 429.Upon receiving the signal, an analog-to-digital conversion is performed with a correspondingly high sampling frequency, which is followed by a (digital) quadrature amplitude demodulation, so that the two output signals from the demodulator output a series of digital orthogonal signal pairs. After low pass filtering of the two channels, a signal pair is obtained from which the symbol frequency (equal to half the data frequency) must be restored in terms of frequency and phase. This can be done, for example. is done as described in "IEEE Transactions on Communications", May 1986, pages 423 to 429.
2525
Efter denne decimering af signalerne til symbolhyppigheden for de to kanaler, tilføres signalerne til en fase-diskriminator, hvis udgang tilvejebringer et fasedatasignal, indeholdende informationen om den ovennævnte fase-30 differens; disse signaler er dog stadig multibit digitale ord, hvorfra fase-differensdata skal separeres.After this decimation of the signals for the symbol frequency of the two channels, the signals are applied to a phase discriminator whose output provides a phase data signal containing the information of the above phase difference; however, these signals are still multibit digital words from which phase difference data must be separated.
Formålet med opfindelsen er at gendanne fase-differensda-ta fra multibit fasedata, ved hjælp af et kredsløb, der 35 er så simpel og elegant designet som muligt, og hvor der kompenseres for fasefejl, der forårsages af transmissionsbanen eller i de efterfølgende signalbehandlings- DK 170848 B1 3 kredsløb. Opfindelsen angår et dekoderkredsløb af den type, som er angivet 1 krav l's Indledning og som er karakteristisk ved den udformning, der er angivet 1 kravets kendetegnende del.The object of the invention is to recover phase difference data from multibit phase data, by means of a circuit which is as simple and elegantly designed as possible, and which compensates for phase errors caused by the transmission path or in the subsequent signal processing DK 170848 B1 3 circuits. The invention relates to a decoder circuit of the type set forth in the preamble of claim 1 and which is characteristic of the embodiment set forth in the characterizing part of the claim.
55
Opfindelsen angår også en anvendelse af dekoderkredsløbet som angivet 1 krav 2.The invention also relates to the use of the decoder circuit as set forth in claim 2.
Opfindelsen forklares mere detaljeret 1 det efterfølgende 10 under henvisning til tegningen, der viser et blokdiagram for en udførelsesform Ifølge opfindelsen.The invention is explained in more detail in the following 10 with reference to the drawing which shows a block diagram of an embodiment according to the invention.
Fasedata tilføres et første konstant adderlngskredsløb kl, der også tilføres et digitalt ord "45°", svarende til 15 fasevinklen 45°. Adderlngskredsløbets udgangssignal er forbundet til en første Indgang på et adderlngskredsløb sm, hvis udgang er forbundet til en subtrahend Indgang på et første subtraktionskredsløb si.Phase data is applied to a first constant adding circuit at 1, which is also supplied with a digital word "45 °", corresponding to the phase angle 45 °. The output signal of the adder circuit is connected to a first input of an adder circuit sm, the output of which is connected to a sub-terminal Input of a first subtraction circuit si.
20 Udgangssignalet fra et andet konstant adderlngskredsløb k2, der som adderlngskredsløbet kl tilføres en konstant 1 form af et digitalt ord "45°", svarende til fasevinklen 45°, er forbundet til en diminuend indgang på det første subtraktionskredsløb si. Et fortegnsbit sb og det mest 25 betydende bit mb fra udgangen på additionskredsløbet sm tilføres som et 2-bit signal til den anden indgang på det konstante additionskredsløb k2, til indgangen af et forsinkelseselement v, og til en diminuend indgang på et andet subtraktionskredsløb s2, på hvis udgang der tilveje-30 bringes fase-differensdata dp. Fra sidstnævnte kan DPSK datapar dannes ved en simpel dekodningsproces. Forsinkelsen, defineret ved forsinkelseselementet v er lig med periodetiden for den oprindelige datahyppighed for DPSK da-tapar.The output of a second constant earth circuit k2 which, as the earth circuit, k1 is applied to a constant 1 form of a digital word "45 °", corresponding to the phase angle 45 °, is connected to a diminishing input of the first subtraction circuit si. A sign bit sb and the most significant bit mb from the output of the addition circuit sm are supplied as a 2-bit signal to the second input of the constant addition circuit k2, to the input of a delay element v, and to a diminutive input of another subtraction circuit s2, on whose output is provided phase difference data dp. From the latter, DPSK data pairs can be formed by a simple decoding process. The delay, defined by the delay element v, is equal to the period of the original data frequency for DPSK da-tapar.
Udgangssignalet fra det første subtraktionskredsløb si er forbundet til den anden indgang på additionskredsløbet sm 35 DK 170848 B1 4 via et lavpasfilter tb, der fungerer som et PLL filter.The output of the first subtraction circuit s1 is connected to the second input of the addition circuit sm 35 DK 170848 B1 4 via a low pass filter tb which acts as a PLL filter.
Ved addition af et 45° digitalt ord til fasedata dd, til fortegnsbit sb, og til det mest betydende bit mb fra ad-5 deringskredsløb sm's udgang, opnås der en pålidelig gendannelse af fasedifferensdata. Ved at addere 45° opnås det, at beslutningsområderne for de respektive vinkelværdier hver er en af de fire koordinatsystemkvadrater, d.v.s. at beslutningsområderne har koordinatakserne som 10 deres grænser. Dette er en betydelig fordel ved opfindelsen.By adding a 45 ° digital word to phase data dd, to sign bit sb, and to the most significant bit mb from the output circuit sm's output, a reliable recovery of phase difference data is obtained. By adding 45 °, it is obtained that the decision ranges for the respective angular values are each one of the four coordinate system squares, i.e. that the decision areas have the coordinate axes as their 10 boundaries. This is a significant advantage of the invention.
Dekoderkredsløbet ifølge opfindelsen kan med fordel anvendes ved demodulation af den tv stereolydsstandard, der 15 tænkes introduceret i Storbritannien og Skandinavien; hvilken standard benævnes "NICAM". Detaljerne ved denne standard er f.eks. beskrevet i en trykt publikation udgivet af 1BA og BBC i december 1986, med titlen "Specification of a Standard for UK Stereo-with-television Trans-20 missions”.The decoder circuit according to the invention can advantageously be used in demodulation of the TV stereo sound standard, which is thought to be introduced in the UK and Scandinavia; which standard is referred to as "NICAM". The details of this standard are e.g. described in a print publication published by 1BA and the BBC in December 1986, entitled "Specification of a Standard for UK Stereo-with-Television Trans-20 Missions".
I denne ansøgning efterfølges udgangssignalet af det andet subtraktionskredsløb sb af en DPSK dekoder, der fra fase-differensdata udleder de ovennævnte 2-bit digitale 25 ord, som derefter tilføres en "NICAM" dekoder.In this application, the output of the second subtraction circuit sb is followed by a DPSK decoder which, from phase difference data, derives the aforementioned 2-bit digital 25 words which are then applied to a "NICAM" decoder.
30 3530 35
Claims (2)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP8700683 | 1987-11-06 | ||
PCT/EP1987/000683 WO1989004572A1 (en) | 1987-11-06 | 1987-11-06 | Digital dqpsk decoder circuit element |
Publications (3)
Publication Number | Publication Date |
---|---|
DK717288D0 DK717288D0 (en) | 1988-12-22 |
DK717288A DK717288A (en) | 1989-06-20 |
DK170848B1 true DK170848B1 (en) | 1996-02-05 |
Family
ID=8165215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DK717288A DK170848B1 (en) | 1987-11-06 | 1988-12-22 | Digital DQPSK decoder circuit and use of the decoder circuit |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0387245B1 (en) |
CN (1) | CN1011463B (en) |
DE (1) | DE3773399D1 (en) |
DK (1) | DK170848B1 (en) |
FI (1) | FI89758C (en) |
NO (1) | NO180140C (en) |
WO (1) | WO1989004572A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69325332T2 (en) * | 1992-10-13 | 1999-11-04 | Nec Corp., Tokio/Tokyo | Frequency stabilizer in a radio communication system with phase shift keyed signals |
CN100438520C (en) * | 2003-12-25 | 2008-11-26 | 电子科技大学 | 1 bit sampling differentiate four-phase PSK demodulation circuit and method |
US7469022B2 (en) * | 2004-11-23 | 2008-12-23 | Via Technologies, Inc. | Methods and apparatus for symmetrical phase-shift keying |
FR2982674B1 (en) * | 2011-11-10 | 2015-01-16 | Renault Sas | METHOD AND SYSTEM FOR MEASURING ELECTRICAL CURRENT |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4019149A (en) * | 1976-01-16 | 1977-04-19 | Bell Telephone Laboratories, Incorporated | Correlative data demodulator |
-
1987
- 1987-11-06 WO PCT/EP1987/000683 patent/WO1989004572A1/en active IP Right Grant
- 1987-11-06 DE DE8787907755T patent/DE3773399D1/en not_active Expired - Lifetime
- 1987-11-06 EP EP87907755A patent/EP0387245B1/en not_active Expired - Lifetime
-
1988
- 1988-11-04 CN CN88107543A patent/CN1011463B/en not_active Expired
- 1988-12-22 DK DK717288A patent/DK170848B1/en not_active IP Right Cessation
-
1989
- 1989-01-04 FI FI890034A patent/FI89758C/en not_active IP Right Cessation
- 1989-05-02 NO NO891817A patent/NO180140C/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN1035597A (en) | 1989-09-13 |
FI890034A (en) | 1989-05-07 |
DK717288A (en) | 1989-06-20 |
DK717288D0 (en) | 1988-12-22 |
EP0387245A1 (en) | 1990-09-19 |
FI89758C (en) | 1993-11-10 |
NO891817L (en) | 1989-05-18 |
NO891817D0 (en) | 1989-05-02 |
WO1989004572A1 (en) | 1989-05-18 |
FI89758B (en) | 1993-07-30 |
NO180140C (en) | 1997-02-19 |
FI890034A0 (en) | 1989-01-04 |
CN1011463B (en) | 1991-01-30 |
DE3773399D1 (en) | 1991-10-31 |
NO180140B (en) | 1996-11-11 |
EP0387245B1 (en) | 1991-09-25 |
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B1 | Patent granted (law 1993) | ||
PUP | Patent expired |