DE69933235D1 - Zwischenschicht zwischen titannitrid und high density plasma oxid - Google Patents

Zwischenschicht zwischen titannitrid und high density plasma oxid

Info

Publication number
DE69933235D1
DE69933235D1 DE69933235T DE69933235T DE69933235D1 DE 69933235 D1 DE69933235 D1 DE 69933235D1 DE 69933235 T DE69933235 T DE 69933235T DE 69933235 T DE69933235 T DE 69933235T DE 69933235 D1 DE69933235 D1 DE 69933235D1
Authority
DE
Germany
Prior art keywords
titannitride
oxid
intermediate layer
high density
density plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69933235T
Other languages
English (en)
Other versions
DE69933235T2 (de
Inventor
L Wooten
W Christian
E Spikes
L Evans
Z Hossain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69933235D1 publication Critical patent/DE69933235D1/de
Application granted granted Critical
Publication of DE69933235T2 publication Critical patent/DE69933235T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69933235T 1998-11-13 1999-05-27 Zwischenschicht zwischen titannitrid und high density plasma oxid Expired - Lifetime DE69933235T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/191,763 US6271112B1 (en) 1998-11-13 1998-11-13 Interlayer between titanium nitride and high density plasma oxide
US191763 1998-11-13
PCT/US1999/011650 WO2000030175A1 (en) 1998-11-13 1999-05-27 Interlayer between titanium nitride and high density plasma oxide

Publications (2)

Publication Number Publication Date
DE69933235D1 true DE69933235D1 (de) 2006-10-26
DE69933235T2 DE69933235T2 (de) 2007-09-13

Family

ID=22706840

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69943414T Expired - Lifetime DE69943414D1 (de) 1998-11-13 1999-05-27 Zwischenschicht zwischen Titannitrid und hochdichtem Plasmaoxid
DE69933235T Expired - Lifetime DE69933235T2 (de) 1998-11-13 1999-05-27 Zwischenschicht zwischen titannitrid und high density plasma oxid

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69943414T Expired - Lifetime DE69943414D1 (de) 1998-11-13 1999-05-27 Zwischenschicht zwischen Titannitrid und hochdichtem Plasmaoxid

Country Status (6)

Country Link
US (1) US6271112B1 (de)
EP (2) EP1135803B1 (de)
JP (1) JP2003526898A (de)
KR (1) KR100577446B1 (de)
DE (2) DE69943414D1 (de)
WO (1) WO2000030175A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007027234A (ja) * 2005-07-13 2007-02-01 Seiko Epson Corp 半導体装置及びその製造方法
US9406574B1 (en) 2007-08-09 2016-08-02 Cypress Semiconductor Corporation Oxide formation in a plasma process
US8119538B1 (en) * 2007-08-09 2012-02-21 Cypress Semiconductor Corporation Oxide formation in a plasma process
US20110204517A1 (en) * 2010-02-23 2011-08-25 Qualcomm Incorporated Semiconductor Device with Vias Having More Than One Material
US8518818B2 (en) 2011-09-16 2013-08-27 Taiwan Semiconductor Manufacturing Co., Ltd. Reverse damascene process

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4829024A (en) 1988-09-02 1989-05-09 Motorola, Inc. Method of forming layered polysilicon filled contact by doping sensitive endpoint etching
JP2655213B2 (ja) 1991-10-14 1997-09-17 三菱電機株式会社 半導体装置の配線接続構造およびその製造方法
US5686761A (en) 1995-06-06 1997-11-11 Advanced Micro Devices, Inc. Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology
US5679606A (en) * 1995-12-27 1997-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. method of forming inter-metal-dielectric structure
US5976993A (en) * 1996-03-28 1999-11-02 Applied Materials, Inc. Method for reducing the intrinsic stress of high density plasma films
US5654216A (en) * 1996-04-08 1997-08-05 Chartered Semiconductor Manufacturing Pte Ltd. Formation of a metal via structure from a composite metal layer
JP2985789B2 (ja) 1996-08-30 1999-12-06 日本電気株式会社 半導体装置の製造方法
US5913140A (en) * 1996-12-23 1999-06-15 Lam Research Corporation Method for reduction of plasma charging damage during chemical vapor deposition
US5759906A (en) * 1997-04-11 1998-06-02 Industrial Technology Research Institute Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
US6046106A (en) * 1997-09-05 2000-04-04 Advanced Micro Devices, Inc. High density plasma oxide gap filled patterned metal layers with improved electromigration resistance

Also Published As

Publication number Publication date
JP2003526898A (ja) 2003-09-09
EP1333484A3 (de) 2004-03-17
US6271112B1 (en) 2001-08-07
WO2000030175A1 (en) 2000-05-25
EP1135803B1 (de) 2006-09-13
KR100577446B1 (ko) 2006-05-10
DE69943414D1 (de) 2011-06-16
EP1333484B1 (de) 2011-05-04
EP1135803A1 (de) 2001-09-26
EP1333484A2 (de) 2003-08-06
KR20010086025A (ko) 2001-09-07
DE69933235T2 (de) 2007-09-13

Similar Documents

Publication Publication Date Title
GB2341484B (en) Barrier layer and fabricating method of the same
DE69929456D1 (de) Nahfeldabtastkopf und herstellungsverfahren
GB9826041D0 (en) Trench-gate semiconductor devices and their manufacture
HK1039686A1 (zh) 多層電極結構物及其製造方法
DE60044974D1 (de) Mehrschichtige leiterplatte und leiterplatten-herstellungsmethode
EP1389901A4 (de) Abschirmmaterial und verfahren zur herstellung des abschirmmaterials
DE69834561D1 (de) Halbleiteranordnung und herstellungsverfahren dafür
HUP0102033A3 (en) Use of peg-ifn-alpha and ribavirin for the treatment of chronic hepatitis c
DE69935701D1 (de) Schalterstruktur und Herstellverfahren
GB0116840D0 (en) Absorbent structure and method for production
DE59901183D1 (de) Plasmareaktor
EP1100136A4 (de) Zelle und verfahren zur herstellung derselben
GB2336469B (en) Semiconductor device and manufacturing method of the same
GB2337470B (en) Barrier coatings and the methods for manufacturing the same
DE69937109D1 (de) Zahnbürste und herstellungsverfahren
DE69915335D1 (de) Vollscheibenfahrzeugrad und herstellungsverfahren
DE69916694D1 (de) 2-Hydroxy-5-methyl-hexan-3-on und 3-hydroxy-5-methyl-hexan-2-on
EP0984276A4 (de) Kapillarkassette und verfahren zu deren herstellung
DE69935994D1 (de) Plasmareaktor
DE69933235D1 (de) Zwischenschicht zwischen titannitrid und high density plasma oxid
GB2363616B (en) Composite materials and method of manufacturing the same
GB9924626D0 (en) Semiconductor device and method of forming the same
DE69914430D1 (de) Festelektrolyt und Herstellungsverfahren
GB9815575D0 (en) Common rail and method of manufacturing the same
DE50013994D1 (de) Symmetrischer Thyristor mit verringerter Dicke und Herstellungsverfahren dafür

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,