DE69931604D1 - Datenübertragungssteuereinrichtung und elektronisches gerät - Google Patents

Datenübertragungssteuereinrichtung und elektronisches gerät

Info

Publication number
DE69931604D1
DE69931604D1 DE69931604T DE69931604T DE69931604D1 DE 69931604 D1 DE69931604 D1 DE 69931604D1 DE 69931604 T DE69931604 T DE 69931604T DE 69931604 T DE69931604 T DE 69931604T DE 69931604 D1 DE69931604 D1 DE 69931604D1
Authority
DE
Germany
Prior art keywords
electronic device
data transfer
transfer controller
controller
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69931604T
Other languages
English (en)
Other versions
DE69931604T2 (de
Inventor
Takuya Ishida
Yoshiyuki Kamihara
Fumitoshi Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Application granted granted Critical
Publication of DE69931604D1 publication Critical patent/DE69931604D1/de
Publication of DE69931604T2 publication Critical patent/DE69931604T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/13—Flow control; Congestion control in a LAN segment, e.g. ring or bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/12—Avoiding congestion; Recovering from congestion
    • H04L47/127—Avoiding congestion; Recovering from congestion by using congestion prediction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/22—Traffic shaping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
DE69931604T 1998-10-27 1999-10-26 Datenübertragungssteuereinrichtung und elektronisches gerät Expired - Lifetime DE69931604T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP32154098 1998-10-27
JP32154098A JP3494042B2 (ja) 1998-10-27 1998-10-27 データ転送制御装置及び電子機器
PCT/JP1999/005903 WO2000025216A1 (fr) 1998-10-27 1999-10-26 Controleur de transfert de donnees et dispositif electronique

Publications (2)

Publication Number Publication Date
DE69931604D1 true DE69931604D1 (de) 2006-07-06
DE69931604T2 DE69931604T2 (de) 2007-03-08

Family

ID=18133707

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69931604T Expired - Lifetime DE69931604T2 (de) 1998-10-27 1999-10-26 Datenübertragungssteuereinrichtung und elektronisches gerät

Country Status (8)

Country Link
US (1) US6834316B1 (de)
EP (1) EP1049020B1 (de)
JP (1) JP3494042B2 (de)
KR (1) KR100464469B1 (de)
CN (1) CN1146799C (de)
DE (1) DE69931604T2 (de)
TW (1) TW451137B (de)
WO (1) WO2000025216A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3608441B2 (ja) * 1999-07-15 2005-01-12 セイコーエプソン株式会社 データ転送制御装置及び電子機器
EP1255377A1 (de) * 2001-05-02 2002-11-06 Deutsche Thomson-Brandt Gmbh Schnittstelle
EP1263169B1 (de) * 2001-05-22 2004-12-01 Sony International (Europe) GmbH Verfahren zur Auswertung von Information über mehrere Knoten eines Netzwerks
FR2837296B1 (fr) * 2002-03-15 2004-06-25 Airbus France Dispositif et procede d'acquisition de mesures a l'aide d'un bus de communication numerique, utilises notamment lors des essais d'un aeronef
DE10302363A1 (de) * 2003-01-22 2004-08-05 Deutsche Thomson-Brandt Gmbh Verfahren zum Betreiben eines Netzwerks von Schnittstellenknoten und Schnittstelleneinrichtung
JP5411612B2 (ja) * 2009-07-29 2014-02-12 アルパイン株式会社 通信装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5758089A (en) 1995-11-02 1998-05-26 Sun Microsystems, Inc. Method and apparatus for burst transferring ATM packet header and data to a host computer system
EP0803821A3 (de) * 1996-04-26 1998-01-28 Texas Instruments Incorporated DMA-Kanalzuordnung in einem Datenpaketübertragungsgerät
JPH1040211A (ja) 1996-04-30 1998-02-13 Texas Instr Inc <Ti> パケット化されたデータ通信インタフェース機器内での直接メモリアクセス優先順位を割り当てるための方法ならびにｄｍａチャンネル回路
US6131119A (en) * 1997-04-01 2000-10-10 Sony Corporation Automatic configuration system for mapping node addresses within a bus structure to their physical location
JPH10285223A (ja) 1997-04-01 1998-10-23 Sony Corp 信号処理回路
US5875313A (en) * 1997-04-08 1999-02-23 National Instruments Corporation PCI bus to IEEE 1394 bus translator employing write pipe-lining and sequential write combining
JPH1117773A (ja) 1997-06-20 1999-01-22 Sony Corp シリアルインタフェース回路
US6157972A (en) * 1997-12-05 2000-12-05 Texas Instruments Incorporated Apparatus and method for processing packetized information over a serial bus
JP3494041B2 (ja) * 1998-10-27 2004-02-03 セイコーエプソン株式会社 データ転送制御装置及び電子機器

Also Published As

Publication number Publication date
KR20010033660A (ko) 2001-04-25
WO2000025216A1 (fr) 2000-05-04
TW451137B (en) 2001-08-21
CN1146799C (zh) 2004-04-21
JP3494042B2 (ja) 2004-02-03
JP2000134232A (ja) 2000-05-12
EP1049020A4 (de) 2002-05-29
US6834316B1 (en) 2004-12-21
EP1049020B1 (de) 2006-05-31
DE69931604T2 (de) 2007-03-08
EP1049020A1 (de) 2000-11-02
KR100464469B1 (ko) 2004-12-31
CN1292122A (zh) 2001-04-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition