DE69836056D1 - Prozessor mit verringerter Zahl von bedingten Befehlen - Google Patents
Prozessor mit verringerter Zahl von bedingten BefehlenInfo
- Publication number
- DE69836056D1 DE69836056D1 DE69836056T DE69836056T DE69836056D1 DE 69836056 D1 DE69836056 D1 DE 69836056D1 DE 69836056 T DE69836056 T DE 69836056T DE 69836056 T DE69836056 T DE 69836056T DE 69836056 D1 DE69836056 D1 DE 69836056D1
- Authority
- DE
- Germany
- Prior art keywords
- processor
- reduced number
- conditional commands
- conditional
- commands
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/447—Target code generation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23435497 | 1997-08-29 | ||
JP23435497A JP3419267B2 (ja) | 1997-08-29 | 1997-08-29 | プロセッサ、コンパイラ及び命令列変換装置 |
JP09564598A JP3843594B2 (ja) | 1998-04-08 | 1998-04-08 | プロセッサ、コンパイラ及び命令列変換装置 |
JP9564598 | 1998-04-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69836056D1 true DE69836056D1 (de) | 2006-11-16 |
DE69836056T2 DE69836056T2 (de) | 2007-04-12 |
Family
ID=26436871
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69836056T Expired - Lifetime DE69836056T2 (de) | 1997-08-29 | 1998-08-28 | Prozessor mit verringerter Zahl von bedingten Befehlen |
Country Status (4)
Country | Link |
---|---|
US (3) | US6230258B1 (de) |
EP (2) | EP1645956A3 (de) |
CN (3) | CN100347668C (de) |
DE (1) | DE69836056T2 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6360316B1 (en) * | 1999-06-16 | 2002-03-19 | Intel Corporation | Method for fast detection of mutually exclusive predicated instructions |
US6321380B1 (en) * | 1999-06-29 | 2001-11-20 | International Business Machines Corporation | Method and apparatus for modifying instruction operations in a processor |
DE10111461B4 (de) * | 2001-03-09 | 2005-08-11 | Fujitsu Siemens Computers Gmbh | Verfahren zum Umsetzen eines Objektcodes für einen ersten Prozessor in einen Objektcode eines zweiten Prozessors |
JP3851228B2 (ja) * | 2002-06-14 | 2006-11-29 | 松下電器産業株式会社 | プロセッサ、プログラム変換装置及びプログラム変換方法、並びにコンピュータプログラム |
US20040230781A1 (en) * | 2003-05-16 | 2004-11-18 | Via-Cyrix, Inc. | Method and system for predicting the execution of conditional instructions in a processor |
US8977837B2 (en) * | 2009-05-27 | 2015-03-10 | Arm Limited | Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes |
CN101739237B (zh) * | 2009-12-21 | 2013-09-18 | 龙芯中科技术有限公司 | 微处理器功能性指令实现装置和方法 |
CN102446112B (zh) * | 2010-10-12 | 2015-05-20 | 无锡江南计算技术研究所 | 指令处理装置和处理器、指令翻译装置和方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5165033A (en) * | 1983-07-25 | 1992-11-17 | Hitachi, Ltd. | Microprocessor and data processor using the former |
JPS6043751A (ja) * | 1983-08-18 | 1985-03-08 | Hitachi Ltd | 情報処理装置 |
JP2810043B2 (ja) * | 1987-11-13 | 1998-10-15 | 株式会社日立製作所 | データ処理装置 |
US5471593A (en) * | 1989-12-11 | 1995-11-28 | Branigin; Michael H. | Computer processor with an efficient means of executing many instructions simultaneously |
JPH0460720A (ja) * | 1990-06-29 | 1992-02-26 | Hitachi Ltd | 条件分岐命令制御方式 |
US5539888A (en) * | 1993-12-23 | 1996-07-23 | Unisys Corporation | System and method for processing external conditional branch instructions |
KR960021079A (ko) * | 1994-12-21 | 1996-07-18 | 김진만 | 골프 스윙 교정 헬스기 |
EP0730220A3 (de) * | 1995-03-03 | 1997-01-08 | Hal Computer Systems Inc | Verfahren und Vorrichtung zur schnellen Ausführung von Verzweigungsbefehlen |
JP3113792B2 (ja) * | 1995-04-27 | 2000-12-04 | 松下電器産業株式会社 | 最適化装置 |
JP3130446B2 (ja) * | 1995-05-10 | 2001-01-31 | 松下電器産業株式会社 | プログラム変換装置及びプロセッサ |
GB2308470B (en) * | 1995-12-22 | 2000-02-16 | Nokia Mobile Phones Ltd | Program memory scheme for processors |
US5826089A (en) * | 1996-01-04 | 1998-10-20 | Advanced Micro Devices, Inc. | Instruction translation unit configured to translate from a first instruction set to a second instruction set |
US6105124A (en) * | 1996-01-26 | 2000-08-15 | Intel Corporation | Method and apparatus for merging binary translated basic blocks of instructions |
US5770894A (en) * | 1996-07-10 | 1998-06-23 | International Business Machines Corporation | Parallel processing method having arithmetical conditions code based instructions substituted for conventional branches |
US5951678A (en) * | 1997-07-25 | 1999-09-14 | Motorola, Inc. | Method and apparatus for controlling conditional branch execution in a data processor |
US6075935A (en) * | 1997-12-01 | 2000-06-13 | Improv Systems, Inc. | Method of generating application specific integrated circuits using a programmable hardware architecture |
US6202198B1 (en) * | 1998-04-21 | 2001-03-13 | Neoprobe Corporation | Programmable integrated analog input/output circuit with distributed matching memory array |
US6353880B1 (en) * | 1998-07-22 | 2002-03-05 | Scenix Semiconductor, Inc. | Four stage pipeline processing for a microcontroller |
US6226716B1 (en) * | 1998-12-22 | 2001-05-01 | Unisys Corporation | Test driver for use in validating a circuit design |
-
1998
- 1998-08-28 DE DE69836056T patent/DE69836056T2/de not_active Expired - Lifetime
- 1998-08-28 CN CNB031243908A patent/CN100347668C/zh not_active Expired - Fee Related
- 1998-08-28 EP EP05017199A patent/EP1645956A3/de not_active Withdrawn
- 1998-08-28 CN CNB2004100053791A patent/CN1282920C/zh not_active Expired - Fee Related
- 1998-08-28 CN CNB981202993A patent/CN1145878C/zh not_active Expired - Fee Related
- 1998-08-28 EP EP98306919A patent/EP0899653B1/de not_active Expired - Lifetime
- 1998-08-31 US US09/144,298 patent/US6230258B1/en not_active Expired - Lifetime
-
2001
- 2001-01-08 US US09/756,068 patent/US6606703B2/en not_active Expired - Lifetime
-
2003
- 2003-07-11 US US10/617,506 patent/US20050091478A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20050091478A1 (en) | 2005-04-28 |
US20010001154A1 (en) | 2001-05-10 |
CN100347668C (zh) | 2007-11-07 |
EP0899653A2 (de) | 1999-03-03 |
CN1516004A (zh) | 2004-07-28 |
EP1645956A3 (de) | 2008-02-13 |
EP1645956A2 (de) | 2006-04-12 |
CN1219703A (zh) | 1999-06-16 |
EP0899653B1 (de) | 2006-10-04 |
CN1282920C (zh) | 2006-11-01 |
DE69836056T2 (de) | 2007-04-12 |
US6606703B2 (en) | 2003-08-12 |
CN1145878C (zh) | 2004-04-14 |
EP0899653A3 (de) | 2000-12-06 |
CN1521618A (zh) | 2004-08-18 |
US6230258B1 (en) | 2001-05-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PANASONIC CORP., KADOMA, OSAKA, JP |